MHEMT with a power-gain cut-off frequency of f max = 0.63 THz on the basis of a In0.42Al0.58As/In0.42Ga0.58As/In0.42Al0.58As/GaAs nanoheterostructure

The method of molecular-beam epitaxy is used to grow a In_0.42Al_0.58As/In_0.42Ga_0.58As/In_0.42Al_0.58As nanoheterostructure with a step-graded metamorphic buffer on a GaAs substrate. The root-mean-square value of the surface roughness is 3.1 nm. A MHEMT (metamorphic high-electron-mobility transistor) with a zigzag-like gate of a length of 46 nm is fabricated on the basis of this nanoheterostructure; for this MHEMT, the cutoff frequencies for the current and power gain are f _T = 0.13 THz and f _max = 0.63 THz, respectively.     

20-nm enhancement-mode metamorphic GaAs HEMT with highly doped InGaAs source/drain regions for high-frequency applications

In this article, the DC and RF performance of a SiN passivated 20-nm gate length metamorphic high electron mobility transistor (MHEMT) on GaAs substrate with highly doped InGaAs source/drain (S/D) regions have investigated using the Synopsys TCAD tool. The 20-nm enhancement-mode (E-mode) MHEMT device also features δ-doped sheets on either side of the In_0.53Ga_0.47As/InAs/In_0.53Ga_0.47As channel which exhibits a transconductance of 3100 mS/mm, cut-off frequency (f_T) of 740 GHz and a maximum oscillation frequency (f_max) of 1040 GHz. The threshold voltage of the device is found to be 0.07 V. The room temperature Hall mobilities of the 2-dimensional sheet charge density are measured to be over 12,600 cm²/Vs with a sheet charge density larger than 3.6 × 10¹² cm^?2. These high-performance E-mode MHEMTs are attractive candidates for sub-millimetre wave applications such as high-resolution radars for space research, remote atmospheric sensing, imaging systems and also for low noise wide bandwidth amplifier for future communication systems.     

Figure of merit for narrowband,wideband and multiband LNAs

In software defined radio, the same radio front end is used to accommodate different wireless standards operating in different frequency bands. The use of wideband or multiband low noise amplifiers (LNAs) is mandatory in such situations. There are several figures of merit (FoMs) proposed for narrowband LNAs. These FoMs are modified for wideband/multiband LNAs just by the inclusion of 3?dB bandwidth, and designers tend to use the one that favours their own design. In this article, a review of the existing FoMs for narrowband LNAs is presented. Based on this analysis, we propose two different FoMs for fair comparison of improvement in LNA parameters due to complementary metal oxide semiconductor (CMOS) technology advancement and circuit optimisation (irrespective of transistor technology), separately. The empirical technology scaling factor for gain, noise figure (NF), f _T and linearity is used to differentiate between these FoMs for different types of LNAs.     

AlGaN/GaN HEMT小信号模型参数提取算法

本文采用了新型的22元件AlGaN/GaN HEMT小信号等效电路模型,较传统的模型,增加了栅漏电导Ggdf和栅源电导Ggsf来表征GaN HEMT的栅极泄漏电流。同时针对新型的栅场板、源场板结构器件,提出了一种改进的寄生电容参数提取方法,使之适用于提取非对称器件的小信号模型参数。为验证此模型,获得了S参数的测试结果和模型仿真结果,此二者的吻合度较高,表明新型的22元件小信号模型精确、稳定而且物理意义明确。     

The performance of resonant tunnelling transistors

An investigation is reported of the performance of the resonant tunnelling transistor based on the solution of Schrödinger's equation. The calculated J-V (current density-voltage) characteristics have been obtained and from the equivalent circuit, which is derived from these calculations, the cut-off frequency f_T and the maximum frequency of oscillation f_max have been estimated.     

Investigation of impact ionization and flicker noise properties in indium aluminum arsenide/indium gallinum arsenide metamorphic high electron mobility transistors with various work function-gate metals

This study investigates the effect of impact ionization using Ir, Pt, Pd, Ti gate metals and the direct correlation between these high work function metals and low frequency noise (LFN) on an In_0.4Al_0.6As/In_0.4Ga_0.6As metamorphic high electron mobility transistor (MHEMT). The effect of impact ionization on DC, RF, and cryogenic LFN is systematically studied and discussed. Gate metals with high work functions are used to suppress the kink effect and gate leakage current. Experimental results suggest that the Ir gate MHEMT exhibits superior thermal stable properties in a strong electrical field at various temperatures, associated with high gain, high current, and excellent low-frequency noise performance.     

Improved temperature model of AlGaN/GaN HEMT and device characteristics at variant temperature

In this paper, an improved temperature model for AlGaN/GaN high electron mobility transistor (HEMT) is presented. Research is being conducted for a high-performance building block for high frequency applications that combine lower costs with improved performance and manufacturability. The effects of channel conductance in the saturation region and the parasitic resistance due to the undoped GaN buffer layer have been included. The effect of both spontaneous and piezoelectric polarization induced charges at the AlGaN/GaN heterointerface has been incorporated. The proposed model is used to determine the transfer characteristics, output current-voltage characteristics and small-signal microwave parameters of HEMTs. The investigated temperature range is from 100–600 K. The small signal microwave parameters have been evaluated to determine the unity current gain cut-off frequency (f _T ). High f _T (10–70 GHz) values and high current levels (～550 mA/mm) are achieved for a 1 μm AlGaN/GaN HEMTs. A custom DC measurement system is used to facilitate the DC characterization of the unpackaged GaN HEMT test device. The calculated critical parameters and the simulation results suggest that the performance of the proposed device degrades at elevated temperatures.     

A Very High-Frequency Transistor-Only Linear Tunable Companding Current-Mode Integrator

A low-distortion tunable transistor-only integrator suitable for applications in the frequency range approaching the f _T of transistors is presented. The circuit is a modified version of the recently introduced companding current-mode integrator utilizing the non-linear base-emitter diffusion capacitance of the BJT. A first-order approximation of the circuit characteristics is explained, followed by a brief discussion on the departure from ideal characteristics due to transistor nonidealities. Experimental and simulated results of practical integrators are given to verify the feasibility of the proposed modified circuit.     

Si‐core/SiGe‐shell channel nanowire FET for sub‐10‐nm logic technology in the THz regime

The p‐type nanowire field‐effect transistor (FET) with a SiGe shell channel on a Si core is optimally designed and characterized using in‐depth technology computer‐aided design (TCAD) with quantum models for sub‐10‐nm advanced logic technology. SiGe is adopted as the material for the ultrathin shell channel owing to its two primary merits of high hole mobility and strong Si compatibility. The SiGe shell can effectively confine the hole because of the large valence‐band offset (VBO) between the Si core and the SiGe channel arranged in the radial direction. The proposed device is optimized in terms of the Ge shell channel thickness, Ge fraction in the SiGe channel, and the channel length (L_g) by examining a set of primary DC and AC parameters. The cutoff frequency (f_T) and maximum oscillation frequency (f_max) of the proposed device were determined to be 440.0 and 753.9 GHz when L_g is 5 nm, respectively, with an intrinsic delay time (τ) of 3.14 ps. The proposed SiGe‐shell channel p‐type nanowire FET has demonstrated a strong potential for low‐power and high‐speed applications in 10‐nm‐and‐beyond complementary metal‐oxide‐semiconductor (CMOS) technology.     

Design of power-controlled class1 Bluetooth CMOS power amplifier

In this paper, an RF power amplifier intended for class 1 Bluetooth application is designed using 0.35 µm CMOS technology. A layout-aware macromodel for the BSIM3v3 MOSFET transistor for RF applications including substrate effect is investigated and used in this design. The model is validated for a 0.35 μm CMOS process using a transistor with total width of 90 μm and 18 fingers and it shows excellent agreement with the f_t and S-parameter measurement data up to 6 GHz. The effects of pads and bond wires are also taken into consideration during the design process of the PA. After post-layout simulations, the amplifier delivers an output power of 19 dBm with 33.7% PAE under 3.3 V supply. This amplifier has a power control feature; its two stage circuit utilizes a cascode configuration in its first stage in order to use its bias pin as a power control input for the amplifier. Using this method, the power control range can be decreased down to 1.4 dBm which satisfies the Bluetooth standard. The chip is fabricated and is currently under testing.     

Impact of gate oxide nitridation process on 1/f noise in 0.18 μm CMOS

The aim of this paper is to study the impact of the nitridation techniques on the 1/f noise performances of dual gate 0.18 μm CMOS transistors. Nitrogen is often introduced to prevent boron penetration in ultrathin oxides especially when BF₂ is used for the PMOS junction implantation, but as a result the MOS transistor exhibits higher 1/f noise because of the increased fixed trap density. We show how the nitridation process can be improved in terms of 1/f noise characteristics, in a fully integrated technology. Projections of the 1/f noise behaviour for different technologies are also shown, to emphasise how the 1/f noise becomes an issue when other downscaling properties are considered for analog/RF CMOS applications.     

一种宽带的InGaP/GaAs HBT 再生频率分频器

A dynamic divide-by-two regenerative GaP/GaAs heterojunction bipolar transistors （HBTs） frequency divider （RFD） is presented in a 60-GHz-fT Intechnology. To achieve high operation bandwidth, active loads instead of resistor loads are incorporated into the RFD. On-wafer measurement shows that the divider is operating from 10 GHz up to at least 40 GHz, limited by the available input frequency. The maximum operation frequency of the divider is found to be much higher than fT/2 of the transistor, and also the divider has excellent input sensitivity. The divider consumes 300.85 mW from 5 V supply and occupies an area of 0.47 × 0.22 mm^2.     

A low-cost horizontal current bipolar transistor (HCBT) technology for the BiCMOS integration with FinFETs

A novel Horizontal Current Bipolar Transistor (HCBT) is processed with the scaled down dimensions and the improved technology. The active transistor region is built in the defect-free sidewall of the 580 nm wide n-hills in the (1 1 0) wafer, implying the reduction of the parasitic region's volume, i.e. the extrinsic base and the collector. The fabricated HCBT exhibits the cutoff frequency (f_T) of 21.4 GHz, the maximum frequency of oscillations (f_max) of 32.6 GHz and the collector–emitter breakdown voltage (BV_CEO) of 5.6 V, which are the highest f_T and the highest f_TBV_CEO product among the lateral bipolar transistors (LBTs).     

A simple analytical model to accurately predict self-resonance frequencies of on-silicon-chip inductors in TEM mode and eddy current mode

For the first time, a simple analytical model in the form of explicit formulas was derived for on-silicon-chip inductors. This analytical model can accurately calculate self-resonance frequencies (f_SR) in TEM mode and eddy current mode corresponding to very high and very low substrate resistivities (ρ_Si). Furthermore, this derived model can predict and explain the interesting result that f_SR keeps nearly a constant independent of ρ_Si in TEM and eddy current modes but is critically determined by the inductance and parasitic capacitances. The simple model is useful in on-silicon-chip inductor design for increasing f_SR under specified inductance target for broadband RF circuit design and applications.     

Subthreshold 1/f noise measurements in MOS transistors aimed at optimizing focal plane array signal processing

In focal plane signal processing applications it is imperative to minimize noise in the associated input circuit. The latter usually consists of MOS transistor preamplifiers and multiplexers. This paper concentrates on the 1/f noise generation in NMOS input signal processing circuits. A 1/f noise model for the subthreshold region is derived and correlated with 1/f noise measurements of NMOS transistors. This model is unique in that slow and fast surface states can be modeled separately. Typical values for slow and fast surface state densities from measured data and model correlation were found to be N _{ss s}=1×10¹¹ cm^-2 eV^-1 and N _{ss f}=3×10¹⁰ cm^-2 eV^-1, respectively. The order of magnitude of these results correlate well with published data [1–3]. The importance of these results is that process changes to minimize the 1/f noise can be monitored and the required minimization of 1/f noise for focal plane signal processing circuits can be achieved.     

Hot-carrier reliability of 20V MOS transistors in 0.13 μm CMOS technology

This paper presents results of reliability investigation of 20 V N-Drift MOS transistor in 0.13 μm CMOS technology. Due to high performances required for CMOS applications, adding high voltage devices becomes a big challenge to guarantee the reliability criteria. In this context, new reliability approaches are needed. Safe Operating Area are defined for switch, V_ds limited and V_gs limited applications in order to improve circuit designs. For V_ds limited applications, deep doping dose effects in drift area are investigated in correlation to lifetime evaluations based on device parameter shifts under hot carrier stressing. To further determine the amount and locations of hot carriers injections, accurate 2D technological and electrical simulations are performed and permit to select the best compromise between performance and reliability for N-Drift MOS transistor.     

High frequency small signal characteristics of the SCL heterojunction transistor

The space-charge-limited (SCL) heterojunction transistor is represented as a planar unit area structure. The internal small signal admittances of the device are derived as functions of transit angle or frequency and the base width and built-in-field. A practical GaAs-Ge heterojunction transistor is used to illustrate the derived admittance characteristics. It is shown, for the model chosen, that the internal transconductance is controlled predominantly by the collector region.The SCL heterojunction transistor is subsequently represented by an equivalent circuit constructed of the internal admittances. The two port Y parameters of the device are then derived from the equivalent circuit and shown as functions of transit angle or frequency. The unilateral gain is also derived as a function of transit angle or frequency.Finally the f_τ and f_max of the GaAsGe model are calculated and it is shown that the maximum value of f_max of 50 GHz obtainable is limited by collector transit time effects.     

22 nm In0.75Ga0.25As channel-based HEMTs on InP/GaAs substrates for future THz applications

In this work, the performance of L_g=22 nm In_0.75Ga_0.25As channel-based high electron mobility transistor (HEMT) on InP substrate is compared with metamorphic high electron mobility transistor (MHEMT) on GaAs substrate. The devices features heavily doped In_0.6Ga_0.4As source/drain (S/D) regions, Si double δ-doping planar sheets on either side of the In_0.75Ga_0.25As channel layer to enhance the transconductance, and buried Pt metal gate technology for reducing short channel effects. The TCAD simulation results show that the InP HEMT performance is superior to GaAs MHEMT in terms of f_T, f_max and transconductance (g_{m_max}). The 22 nm InP HEMT shows an f_T of 733 GHz and an f_max of 1340 GHz where as in GaAs MHEMT it is 644 GHz and 924 GHz, respectively. InGaAs channel-based HEMTs on InP/GaAs substrates are suitable for future sub-millimeter and millimeter wave applications.     

An input-free V extractor circuit using a series connection of three transistors

This paper describes a self-biased MOS transistor circuit with the ground referenced output voltage equal to the threshold voltage V _T. The circuit employs a series connection of three transistors where the middle transistor is in linear operation and external transistors are in saturation. The circuit can be applied for V _T extraction of both n-channel and p-channel transistors. The range of currents for better measuring of V _T in each case is established by simulation.     

Study of the influence of strained superlattices introduced into a metamorphic buffer on the electrophysical properties and the atomic structure of InAlAs/InGaAs MHEMT heterostructures

The results of studying the influence of strained superlattices introduced into a metamorphic buffer on the electrophysical properties and atomic crystal structure of In_0.70Al_0.30As/In_0.76Ga_0.24As/In_0.70Al_0.30As metamorphic high-electron-mobility transistor (MHEMT) nanoheterostructures on GaAs substrates are presented. Two types of MHEMT structures are grown by molecular beam epitaxy, namely, one with a linear increase in x in the In _x Al_{1 ? x} As metamorphic buffer, and the second with two mismatched superlattices introduced inside the metamorphic buffer. The electrophysical and structural parameters of the grown samples are studied by the van der Pauw method, transmission electron microscopy (including scanning and high-resolution microscopy), atomic-force microscopy, and energy dispersive X-ray analysis. It is revealed that the introduction of superlattices into a metamorphic buffer substantially improves the electrophysical and structural characteristics of MHEMT structures.