Electromigration challenges for advanced on-chip Cu interconnects

As technology scales down, the gap between what circuit design needs and what technology allows is rapidly widening for maximum allowed current density in interconnects. This is the so-called EM crisis. This paper reviews the precautions and measures taken by the interconnect process development, circuit design and chip integration to overcome this challenge. While innovative process integration schemes, especially direct and indirect Cu/cap interface engineering, have proven effective to suppress Cu diffusion and enhance the EM performance, the strategies for circuit/chip designs to take advantage of specific layout and EM failure characteristics are equally important to ensure overall EM reliability and optimized performance. To enable future technology scaling, a co-optimization approach is essential including interconnect process development, circuit design and chip integration.     

Evaluation of ultra-low-k dielectric materials for advanced interconnects

The International Technology Roadmap for Semiconductors predicts that continued scaling of devices will require ultra-low-k materials with k values less than 2.5 for the 100 nm technology node and beyond. Incorporation of porosity into dense dielectrics is an attractive way to obtain ultra-low-k materials. Electrical and physical properties of ultra-low-k materials have been characterized. Integration evaluations showed both feasibility and challenges of porous ultra-low-k materials. This paper discusses issues and recent progress made with porous ultra-low-k material properties, deposition processes, characterization metrologies, and process integration.     

Copper metallization for advanced IC: requirements and technological solutions

Due to the scaling down, the contribution of interconnects should become preponderant for the performance of IC. The use of low-k dielectrics and/or low resistivity metals in order to decrease the parasitic capacitance of interconnect is a technological requirement. Especially the use of copper, with mineral dielectric as IMD, instead of aluminium alloy is now commonly accepted. In this paper we compare the intrinsic performance of two damascene architectures. The planarization by metal CMP, which will determine the final metal thickness, may induce killer defects (shorts between lines) or degraded metal sheet resistance uniformity for multi-level metallization devices. The impact on electromigration of the damascene structure is presented: due to the reverse architecture, the grain sizes and orientations are found to be linewidth dependent. On the other hand, the life times extrapolated with different copper and barrier deposition processes vary on a large range: from similar to those obtained with aluminium for a full CVD metallization (barrier+copper) to more than one order of magnitude higher for a CVD barrier and a mixed CVD+PVD copper deposition.     

New copper seed-layer enhancement process metrology for advanced dual-damascene interconnects

The extendibility of the physical vapor deposition (PVD), seed-layer deposition process for future devices needs to be enhanced with electrochemical techniques. Developing analytical techniques for the plating bath is a particular challenge because bath ingredients are often proprietary and difficult to ascertain. The feasibility of using an ion chromatography for an electrochemical copper, seed-layer enhancement (SLE) process metrology is studied. It is shown that the ion-chromatography method can be used to precisely determine the composition dynamics in a copper SLE plating bath. The bath concentration dynamics are found to be significant in influencing the electroplated Cu film properties, i.e., the resistivity and surface roughness. An excellent correlation exists between the ion chromatograms and the electroplated Cu film properties, suggesting that the ion-chromatography method is a powerful method.     

先进DSP框架体系中的ANSI标准互连

对三种ANSI标准互联技术RACEway、FPDP以及串行FPDP进行了概述和介绍,这 些标准对数字信号处理(DSP)系统高效、廉价的处理高速数据提供了依据,可大大的方便设计 人员工作。     

Investigation of the effects of byproduct components in Cu plating for advanced interconnect metallization

This paper discusses the effects of byproduct components generated from a commercially available two components additive package on the copper plating performance for advanced interconnect metallization. The increase in accumulative breakdown products from the sulfur-containing type-A additive during the electroplating (ECP) process, measured using high performance liquid chromatography (HPLC), showed a detrimental effect on via fill performance. These vias with voids may fail by open circuit sooner due to electromigration. Besides, increase of in-film sulfur content was found from the analysis of secondary-ion mass spectrometry (SIMS) on the film electroplated using heavily used plating solution. It was suggested that the increase of incorporated sulfur impurities could render in slower self-annealing rate of the as-plated copper film due to the grain boundary pinning effect.     

Thermal performance of sputtered insoluble Cu(W) films for advanced barrierless metallization

The thermal performance of sputtered Cu films with dilute insoluble W (1.3 at.%) on barrierless Si substrates has been studied, using the analyses of focused ion beam, x-ray diffraction, and electrical resistivity measurement. The role of the Cu(W) film as a seed layer has been confirmed based on the thermal performance evaluations in both thermal cycling and isothermal annealing at various temperatures. The electrical resistivity of ∼1.8 μΩ-cm for Cu/Cu(W) film is obtained after thermal annealing at 400°C. Because of the good thermal stability, the Cu(W) seed layer is also considered to act as a diffusion buffer and is stable up to 490°C for the barrierless Si scheme. The results indicate that the Cu/Cu(W) scheme has potential in advanced barrierless metallization applications.     

Multilayer metallization for LSI

Recent advances in the manufacture of complex bipolar integrated circuits have led to a variety of techniques for metal interconnection on the chip. As the need for more and more devices has increased chip size, the problem of random defects has become catastrophic. Functional yields are often seen to drastically decrease or even vanish with attempts to fabricate very large bipolar parts. Since the major factor determining die size is the metal interconnect size and spacing, one way to conserve "real estate" while achieving highly complex circuits is to employ more than a single layer of interconnection metal. At present both double- and triple-layer schemes are being used. These multilayer metallizations, while solving the problem of chip defects, are not without serious drawbacks of their own. These problems are discussed. The Motorola multilayer systems considered are all aluminum based; i.e., pure aluminum or lightly doped aluminum. Although other metals are being experimented with, aluminum systems make up nearly all of the commercially available ICs at this time. In general, these metal layers are insulated from one another by a deposited dielectric, usually SiO2. The most prominent yield limiting problems are discussed. These include coverage of both metal edges and oxide steps with additional metal and/or another layer of oxide. Processing parameters such as profiles, thickness, temperature, composition, etc., that influence coverage are discussed as well as innovations for improving less-than-desirable results.     

Interactions between solder and metallization during long-term aging of advanced microelectronic packages

The reactions between the eutectic PbSn solder and the Au/Ni/Cu tri-layer metallization in advanced microelectronic packages were studied. In this investigation, reflowed packages were subjected to aging at 160°C for times as long as 4000 h. Immediately after the reflow, all the Au had left the Au/Ni/Cu metallization, forming many (Au_1−xNi_x)Sn₄ particles distributed throughout the whole solderjoint. In addition, there was a thin layer of Ni₃Sn₄ (1.4 μm) at the interface. After 500 h of aging, most of the (Au_1−xNi_x)Sn₄ particles regrouped at the interface as a continuous (Au_0.45Ni_0.55)Sn₄, layer over the Ni₃Sn₄ layer. After 2500 h of aging, nearly all the Ni layer had been consumed. A 15 μm layer of (Au_0.45Ni_0.55) Sn₄ and a 20 μm Ni₃Sn₄ were found over the remaining Ni. At 3000 h, the Cu had started to react with both Ni₃Sn₄ and (Au_1−xNi_x)Sn₄, forming a layer of (Cu_1−p−pAu_pNi_q)₆Sn₅, a layer of (Cu_1−r−sAu₁Ni_s)₆Sn₅, and a layer of Cu₃Sn over the Cu layer. A small amount of Cu (2.7–5.7 at.%) was found to dissolve in this Ni₃Sn₄, forming a ternary compound (Ni_1−yCu_y)₃Sn₄. It was revealed that Au diffused up-hill during the reaction. After aging for 4000 h, all the (Au_1−xNi_x)Sn₄ had disappeared and Au atoms had diffused into the (Cu_1−p−qAu_pNi_q)₆Sn₅ and (Cu_1−r−sAu_rNi_s)₆Sn₅ phases. The practical implications for the above findings were pointed out in this paper.     

Monolayer metallic nanotube interconnects: promising candidates for short local interconnects

Mono- or bi-layer metallic single-wall carbon nanotube interconnects have lateral capacitances more than four times smaller than those of copper interconnects. The resistance and time-of-flight of these monolayer nanotubes would be larger than that of copper interconnects. For short lengths, however, driver resistance is quite dominant, and latency is determined by interconnect capacitance. Monolayer nanotube interconnects are therefore promising candidates for local interconnects. The average capacitance per unit length of these nanotube interconnects can be 50% smaller than that of copper interconnects and that leads to significant saving in power dissipation.     

Differential current-sensing for on-chip interconnects

This paper presents a differential current-sensing technique as an alternative to existing circuit techniques for on-chip interconnects. Using a novel receiver circuit, it is shown that, delay-optimal current-sensing is a faster (20% on an average) option as compared to the delay-optimal repeater insertion technique for single-cycle wires. Delay benefit for current-sensing increases with an increase in wire width. Unlike repeaters, current-sensing does not require placement of buffers along the wire, and hence, eliminates any placement constraints. Inductive effects are negligible in differential current-sensing. Current-sensing also provides a tighter bound on delay with respect to process variations. However, current-sensing has some drawbacks. It is power inefficient due to the presence of static-power dissipation. Current-sensing is essentially a low-swing signaling technique, and hence, it is sensitive to full swing aggressor noise.     

Optimal global interconnects for GSI

Performance of a high-speed chip is largely affected by both latency and bandwidth of global interconnects, which connect different macrocells. Therefore, one of the important goals is to design high-bandwidth and fast buses that connect a processor and its on-chip cache memory or link different processors within a multiprocessor chip. In this paper, the width of global interconnects is optimized to achieve a large "data-flux density" and a small latency simultaneously. Data-flux density is the product of interconnect bandwidth and reciprocal wire pitch, which represents the number of bits per second that can be transferred across a unit-length bisectional line. The optimal wire width, which maximizes the product of data-flux density and reciprocal latency, is independent of interconnect length and can be used for all global interconnects. It is rigorously proved that the optimal wire width is the width that results in a delay that is 33% larger than the time-of-flight (ToF). Using the optimal wire width decreases latency, energy dissipation, and repeater area considerably, compared to a sub-optimal wire width (e.g., 42% smaller latency, 30% smaller energy-per-bit, and 84% smaller repeater area compared with the W/sub opt//2 case) at the cost of a small decrease in data-flux density (e.g., 14% smaller compared with W/sub opt//2 case). A super-optimal wire width, however, causes a slight decrease in latency (e.g., 14% for 2W/sub opt/) at the cost of a large decrease in data-flux density (e.g., 35% for 2W/sub opt/).     

Development of a permittivity extraction method for ultra low k dielectrics integrated in advanced interconnects

An extraction method to determine the permittivity of ultra low k (ULK) dielectrics on real integrated structures is presented. It is a two-step method based on a comparison between measured and simulated capacitance. A best-estimate value of the k_ULK value is first extracted with optimization software coupled to capacitance extraction software. Secondly, uncertainties on material and process parameters are considered to determine an error margin on the best-estimate extracted k value. The uncertainty on the best-estimate value is approximated by a function of the uncertainties on material and process variables. This function is calculated using a multi-linear approximation model and a numerical design of experiments. The same method is applied for the extraction of a ULK material k value (k_ULK) value and an effective k value (k_eff) but with two different simulation structures. In the simulation structure used for k_eff extraction, an equivalent dielectric layer including the ULK layer, the etch-stop and capping layers is used. This method was applied to metal 1 single damascene structures. First results of extraction are presented for two different ULK dielectrics. With the estimated uncertainty used for the parameters in this work, the uncertainties obtained for the best-estimate value of k_ULK and k_effective are significant. Due to the linearity of the model, the method is still applicable with different values for parameters uncertainty. An analysis work will be realized to improve the parameters uncertainty estimation. Future work will also include extraction of ULK permittivity for more complex structures like double damascene structures.     

Reliability challenges for copper interconnects

In the past few years, copper has been widely used as interconnect metallization for advanced ultralarge-scale integration (ULSI) circuits. Due to the unique chemical properties of copper compared to its predecessor, aluminum, different integration processes must be used for circuit fabrication, that is, the damascene versus reactive ion etch (RIE) process. This difference in integration processes introduces a series of reliability concerns for copper interconnects. After a brief comparison of copper and aluminum interconnects, this article discusses the impact of the differences in the material properties and integration process on reliability. Details are provided on two advanced metallization reliability failure mechanisms: electromigration and stress migration. For copper interconnects, the interface between the cap and the copper metal serves as the fast diffusion path. To improve copper interconnect reliability, development efforts have focused on suppressing copper or copper vacancy diffusion along the interface. Two copper interfaces, the copper/cap interface and the copper/liner (or diffusion barrier) interface, are critical for copper reliability. For commonly used liners, such as Ta/TaN, the copper/liner interface is relatively easy to control compared to the copper/cap interface. For dual-damascene copper lines, a copper via is used to connect the lower level to the upper level. Unlike the robust tungsten stud used in aluminum interconnects, the copper via has been identified as a weak link in dual-damascene copper connections; the majority of early reliability failures can be attributed to the copper vias. The three most critical process factors and elements affecting copper interconnect reliability are copper vias and interfaces and the liner coverage. Using a low-k dielectric with a copper interconnect introduces several new challenges to reliability, including dielectric breakdown, temperature cycle, and stability within packages. Extensive knowledge is urgently needed to understand these issues.     

Barrier layers for Cu ULSI metallization

Barrier layers are integral parts of many metal interconnect systems. In this paper we review the current status of barrier layers for copper metallization for ultra-large-scale-integration (ULSI) technology for integrated circuits (ICs) manufacturing. The role of barrier layers is reviewed and the criteria that determine the process window, i.e. the optimum barrier thickness and the deposition processes, for their manufacturing are discussed. Various deposition methods are presented: physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), electroless deposition (ELD), and atomic layer CVD (ALCVD) for barrier layers implementation. The barrier integration methods and the interaction between the barrier and the copper metallization are presented and discussed. Finally, the common inspection and metrology for barrier layer are critically reviewed.     

Factors influencing open circuit decomposition behavior of sulfur-containing additive component used in Cu plating for advanced interconnect metallization

Accelerated decomposition of organic additives during open circuit condition was observed only when both copper wire and oxygen are present in the copper sulfate solution. The data suggest that the accelerating mercapto species could form a complex with cuprous ions from copper anode in the plating solution. The copper complexes formed then undergo oxidation reaction and lose its original electrochemical activity by introducing byproducts. Adsorption behavior of various chemical components in the plating solution on the copper anode surface was found to have a significant influence on the sulfur-containing brightening agent degradation rate. The degradation mechanisms attributed to the interactions among different chemical components are also addressed and discussed.     

Thick-film metallization for solar cell applications

The use of an integral printing technique for the fabrication of silicon solar cells is attractive due to its throughput rate, materials utilization, and modular, automatable design. The transfer of this technology from single crystal to semicrystalline silicon requires a significant amount of process optimization. Processing parameters found to be critical include the optimum glass frit content in the silver-based inks, the silver ink firing temperature, and the formation of the back-surface field using screen-printed aluminum layers. Open-circuit voltages as high as 617 mV have been achieved using a novel BSF approach on 4-in wafers. Important mechanisms controlling ink contact resistance, ink sheet resistivity, and ohmic contact on and silicon materials are discussed in this paper. The solar cell stability is a function of the glass frit and the firing temperature of the silver-based inks. Finally, a simple economic analysis, based on the IPEG technique, indicates that screen printing is a cost-effective option when the cell manufacturing is done on a large scale.     

New precursors for CVD copper metallization

A novel CVD copper process is described using two new copper CVD precursors, KI3 and KI5, for the fabrication of IC or TSV (Through Silicon Via) copper interconnects. The highly conformal CVD copper can provide seed layers for subsequent copper electroplating or can be used to directly fabricate the interconnect in one step. These new precursors are thermally stable yet chemically reactive under CVD conditions, growing copper films of exceptionally high purity at high growth rates. Their thermal stability can allow for elevated evaporation temperatures to generate the high precursor vapor pressures needed for deep penetration into high aspect ratio TSV vias. Using formic acid vapor as a reducing gas with KI5, copper films of >99.99 atomic % purity were grown at 250 °C on titanium nitride at a growth rate of > 1500 Å/min. Using tantalum nitride coated TSV type wafers, ∼ 1700 Å of highly conformal copper was grown at 225 °C into 32 μm × 5 μm trenches with good adhesion. With ruthenium barriers we were able to grow copper at 125 °C at a rate of 20 Å/min to give a continuous ∼ 300 Å copper film. In this respect, rapid low temperature CVD copper growth offers an alternative to the long cycle times associated with copper ALD which can contribute to copper agglomeration occurring.     

Saddle add-on metallization for RF-IC technology

A cost-effective add-on process module for reducing ohmic losses of radio-frequency (RF) inductors and interconnects in RF/BiCMOS and RF/CMOS technologies built on CMOS logic processes is proposed. The module is based on the local thickening of the top metal layer of the thin CMOS interconnects through copper (Cu) electroplating in selected areas. The combination of dense Cu-interconnects in the CMOS logic sections, of thick Cu top-level wiring through local Cu electroplating in the RF sections, and of aluminum (Al) capping of the bond pads provides an optimum tradeoff between packaging requirements, quality of passive components and interconnects, and cost. A special wet-etch process sequence for removal of the Cu-seed and adhesion films from the exposed top metal layer is described. A record quality factor of /spl sim/13 for a 10-nH inductor on a conventional 5-/spl Omega/-cm silicon substrate is demonstrated.     

Time-domain macromodel for lossy VLSI interconnects

A new time-domain model that enables loss effects on the input impedance of on-chip transmission lines during switching transients to be accurately taken into account is presented. The model has been specifically developed for use in conjunction with MOS macromodels to predict the electrical behaviour of matched CMOS buffers. It solves the problem of mixed frequency/time domain analysis by replacing the lines with a lumped time-varying resistor