Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder

Architecture for Dynamically Reconfigurable Embedded Systems (ADRES) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications which demand high-performance, low-power and high-level language programmability. Compared with typical very long instruction word-based digital signal processor, ADRES can exploit higher parallelism by using more scalable hardware with support of novel compilation techniques. We developed a complete tool-chain, including compiler, simulator and HDL generator. This paper describes the design case of a media processor targeting at H.264 decoder and other video tasks based on the ADRES template. The whole processor design, hardware implementaiton and application mapping are done in a relative short period. Yet we obtain C-programmed real-time H.264/AVC CIF decoding at 50 MHz. The die size, clock speed and the power consumption are also very competitive compared with other processors.

Reconfigurable Filter Coprocessor Architecture for DSP Applications

Digital Signal Processing (DSP) is widely used in high-performance media processing and communication systems. In majority of these applications, critical DSP functions are realized as embedded cores to meet the low-power budget and high computational complexity. Usually these cores are ASICs that cannot be easily retargeted for other similar applications that share certain commonalities. This stretches the design cycle that affects time-to-market constraints. In this paper, we present a reconfigurable high-performance low-power filter coprocessor architecture for DSP applications. The coprocessor architecture, apart from having the performance and power advantage of its ASIC counterpart, can be reconfigured to support a wide variety of filtering computations. Since filtering computations abound in DSP applications, the implementation of this coprocessor architecture can serve as an important embedded hardware IP.     

基于流媒体的天气预报电视会商VOD系统设计

结合流媒体技术实施要点,设计了中国气象局天气预报电视会商VOD系统,并对系统的流媒体架构、系统配置架构、软件流程等进行了详细说明.深入分析了系统实施的技术要点,如并发客户端数、流发布类型、信号同步等,设计的系统实现了多路视频信号的采集、上传、直播、点播、下载功能等,特别是视频流和VGA流双路信号的同步、同屏、可控播放.通过实际运行验证,系统运行稳定,有效拓展了电视会商系统的服务范围,有助于天气预报业务的发展.     

VLIW Processor Codesign for Video Processing

A codesign approach for complex video compression systems is presented. The system is based on a flexible and programmable VLIW (Very Long Instruction Word) architecture. The design approach can be subdivided into two phases: a quantitative analysis for deriving the main processor structure and a cosynthesis for generating the processor hardware and the compiler back-end. The analysis results of different video compression algorithms are summarized. This permits to adapt the processor to a set of related applications rather than to a particular task. A compiled instruction-set simulator for analyzing large data sets is presented. An HTML-based codesign framework is shown which documents and organizes the analysis data.     

A New FPGA for DSP Applications Integrating BIST Capabilities

This work proposes a new FPGA architecture, to meet the requirements of signal processing and testing of current system-on-chip designs. The proposed architecture provides the hardware reuse and the reconfigurability advantages of an FPGA, not only for the system functionality, but also for the system testing, while keeping the performance level required by current signal processing applications. This paper presents the new FPGA model, along with preliminary experimental results that clearly show the possible advantages at the system level of merging design and test in a reconfigurable device.     

System-Level Synthesis Using Evolutionary Algorithms

In this paper, we consider system-level synthesis as the problem of optimally mapping a task-level specification onto a heterogeneous hardware/software architecture. This problem requires (1) the selection of the architecture (allocation) including general purpose and dedicated processors, ASICs, busses and memories, (2) the mapping of the specification onto the selected architecture in space (binding) and time (scheduling), and (3) the design space exploration with the goal to find a set of implementations that satisfy a number of constraints on cost and performance. Existing methodologies often consider a fixed architecture, perform the binding only, do not reflect the tight interdependency between binding and scheduling, do not consider communication (tasks and resources), or require long run-times preventing design space exploration, or yield only one implementation with optimal cost. Here, a model is introduced that handles all mentioned requirements and allows the task of system-synthesis to be specified as an optimization problem. The application and adaptation of an Evolutionary Algorithm to solve the tasks of optimization and design space exploration is described.     

ASIP Approach for Implementation of H.264/AVC

This paper presents an Application Specific Instruction Set Processor (ASIP) for implementation of H.264/AVC, called Video Specific Instruction-set Processor (VSIP). The proposed VSIP has novel instructions and optimized hardware architectures for specific applications, such as intra prediction, in-loop deblocking filter, integer transform, etc. Moreover, VSIP has coprocessors for computation intensive parts in video signal processing, such as inter prediction and entropy coding. The proposed VSIP has much smaller area and can dramatically reduce the number of memory access compared with commercial DSP chips, which result in low power consumption. Moreover, the proposed hardware accelerators have small size, consume low power consumption, and thus, they can support real-time video processing. VSIP has been thoroughly verified using an FPGA board having the Xilinx™ Virtex II. VSIP can implement a real-time H.264/AVC decoder. The proposed VSIP is one of promising solutions for video signal processing.

一种动态可重构协处理器参数化系统级模型研究

提出了参数化系统级模型.该模型不依赖于具体结构,以任务布局与重构处理分离的两级结构处理任务调用,通过参数方式实现不同设计方案的硬件结构和布局算法的配置.采用SystemC语言对模型进行了建模验证,仿真结果表明,通过指定上下文的下载、配置和执行等时间开销参数,在系统级设计空间探索中,能很好地模拟动态重构协处理器.     

A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems

We present a methodology for the exploration of signal processing architectures at the system level. The methodology, named SPADE, provides a means to quickly build models of architectures at an abstract level, to easily map applications, modeled as Kahn Process Networks, onto these architecture models, and to analyze the performance of the resulting system by simulation. The methodology distinguishes between applications and architectures, and uses a trace-driven simulation technique for co-simulation of application models and architecture models. As a consequence, architecture models need not be functionally complete to be used for performance analysis while data dependent behavior is still handled correctly. We have used the methodology for the exploration of architectures and mappings of an MPEG-2 video decoder application.     

Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip

The exploration of the design space for heterogeneous Systems on Chip (SoC) becomes more and more important. As modern SoCs include a variety of different architecture blocks ensuring flexibility as well as highest performance, it is mandatory to prune the design space in an early stage of the design process in order to achieve short innovation cycles for new products. Thus, the goal of this work is to provide estimations of implementation specific parameters like throughput rate, power dissipation and silicon area by means of cost functions featuring reasonable accuracy at low modeling effort. A model based exploration strategy supporting the design flow for heterogeneous SoCs is presented. In order to demonstrate the feasibility of this exploration strategy, in a first step implementation cost parameters are provided for a variety of basic operations frequently required in digital signal processing which were implemented on discrete components like DSPs, FPGAs or dedicated ASICs. These implementation parameters serve as a basis for deriving cost models for the design space exploration concept.Holger Blume received his Dipl.-Ing. degree in electrical engineering from the University of Dortmund, Germany in 1992. From 1993 to 1998 he worked as a research assistant with the Working group on Circuits and Systems for Information Processing of Prof. Dr. H. Schröder in Dortmund. There he finished his PhD on Nonlinear fault tolerant interpolation of intermediate images in 1997. In 1998 he joined the Chair of Electrical Engineering and Computer Systems of Prof. Dr. T. G. Noll at the University of Technology RWTH Aachen as a senior engineer. His main research interests are in the field of heterogeneous reconfigurable Systems on Chip for multimedia applications. Dr. Blume is chairman of the German chapter of the IEEE Solid State Circuits Society.Hendrik T. Feldkaemper received the Dipl.-Ing. degree from the University of Technology RWTH Aachen, Germany, in 1997. After half a year of employment in an industrial project at Infineon Technologies in Munich he joined the Chair of Electrical Engineering and Computer Systems (Prof. Dr. T. G. Noll), University of Technology RWTH Aachen as a research assistant. His current research interest include design space exploration for digital signal processing in ultrasound, heterogeneous reconfigurable Systems-on-Chip and VLSI CMOS design.Tobias G. Noll received the Ing. (grad.) degree in Electrical Engineering from the Fachhochschule Koblenz, Germany in 1974, the Dipl-Ing. degree in Electrical Engineering from the Technical University of Munich in 1982, and the Dr.-Ing. degree from the Ruhr-University of Bochum in 1989.From 1974 to 1976, he was with the Max-Planck-Institute of Radio Astronomy, Bonn, Germany, being active in the development of microwave waveguide and antenna components. From 1976 to 1982, he was with the MOS Integrated Circuits Department and from 1982 to 1984, the MOS-Design Team trainee program of Siemens AG, Munich. In 1984, he joined the Corporate Research and Development Department of Siemens, and since 1987, he has headed a group of laboratories concerned with the design of algorithm-specific integrated CMOS circuits for high speed digital signal processing.Since 1992, he has been a Professor for Electrical Engineering and Computer Systems with the University of Technology (RWTH), Aachen, Germany. In addition to teaching, he is involved in research activities on VLSI architectural strategies for high-speed digital signal processing, circuit concepts, and design methodologies, as well as on digital signal processing for medicine electronics.     

Reconfigurable Antenna for Future Wireless Communication Systems

This paper deals with the processing techniques which are known as reconfigurable antennas: these methods are foreseen to be a booster for the future high rate wireless communications, both for the benefits in terms of performance and for the capacity gains. In particular, adaptive digital signal processing can provide improved performance for the desired signal in terms of error probability or signal-to-noise ratio while the bandwidth efficiency can be increased linearly with the number of transmitting and receiving antennas. In this article, the main antenna processing techniques are reviewed and described, aiming at highlighting performance/complexity trade-offs and how they could be implemented in the future systems. The coexistence of all these different technologies in a wireless environment requires high efficiency and flexibility of the transceiver. Future transceiver implementations which are based on the Software Defined Radio technology are also reviewed and described.