A portable digitally controlled oscillator using novel varactors

This work presents a portable digitally controlled oscillator (DCO) by using two-input NOR gates as a digitally controlled varactor (DCV) in fine-tuning delay cell design. This novel varactor uses the gate capacitance difference of NOR gates under different digital control inputs to establish a DCV. Thus proposed DCO can improve delay resolution 256 times better than a single buffer design. This study also examines different types of NOR/NAND gates (2-input or 3-input) for DCV. The proposed DCO with novel DCV can be implemented with standard cells, and thus it can be ported to different processes in short time. Furthermore, the final circuit layout can be generated using an auto placement and routing (APR) tools. A test chip demonstrates that LSB resolution of the DCO can be improved to 1.55 ps with standard 0.35-/spl mu/m 2P4M CMOS digital cell library. The proposed DCO has good performance in terms of fine resolution, high portability, and short design turnaround cycle compared with conventional DCO designs.     

A digitally controlled PLL for SoC applications

A fully integrated digitally controlled phase-locked loop (PLL) used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. The design is, therefore, portable between technologies as an IP block. Using a 0.35-/spl mu/m standard CMOS process and a 3.0-V supply voltage, the PLL has a frequency range of 152 to 366 MHz and occupies an on-chip area of 0.07 mm/sup 2/. In addition, the next version of this all-digital PLL is described in synthesizable VHDL code, which simplifies digital system simulation and change of process. A new time-to-digital converter with higher resolution is designed for the improved PLL. An improved digitally controlled oscillator is also suggested.     

Ring voltage controlled oscillator for high-speed PLL systems

A circuit of a ring voltage controlled oscillator (VCO), which is to be used in high-speed phase-locked loop (PLL) systems integrated into programmable logic integrated circuits, is proposed. The maximum operating frequency of a VCO in 180 nm CMOS is shown by simulation to be able to reach 2 GHz in all operating conditions with the phase noise being ?99 dB/Hz and detuning frequency being 1 MHz.     

A portable high-frequency digitally controlled oscillator (DCO)

A novel digitally-controlled oscillator (DCO) is reported. Utilizing a new capacitive load, the new DCO is capable of producing much higher output frequencies than existing DCOs. All other components are fully digital and modular, allowing portability to any CMOS process and customization for different applications. At the heart of the DCO is a digital ring oscillator (DRO) that utilizes the new shunt-capacitive loads. Unprecedented higher frequencies are obtained through a novel idea of electrically removing the effect of un-enabled loads. Simple design conditions for achieving proper operation of the DRO are provided and verified through simulations with several technologies. Spice simulations verified the correct and superior operation of the DCO even with device mismatch. A custom layout of the DRO was generated using LFoundry's 150 nm technology. The total DRO area was found to be 418 µm². Comparison with other DCOs and VCO shows that the new DCO outperforms conventional DCOs in all aspects; maximum attainable frequency, power efficiency and required number of control bits to achieve a certain resolution.     

A first multigigahertz digitally controlled oscillator for wireless applications

A novel digitally controlled oscillator (DCO) architecture for multigigahertz wireless RF applications, such as short-range wireless connectivity or cellular phones, is proposed and demonstrated. It deliberately avoids any use of an analog tuning voltage control line. Fine frequency resolution is achieved through high-speed dithering, yet the resulting spurious tones are very low. This enables to employ fully digital frequency synthesizers in the most advanced deep-submicrometer digital CMOS processes, which allow almost no analog extensions. It promotes cost-effective integration with the digital back-end onto a single silicon die. The demonstrator test chip has been fabricated in a digital 0.13 /spl mu/m CMOS process together with a digital signal processor to investigate noise coupling. The 2.4 GHz DCO core consumes 2.3 mA from a 1.5 V supply and has a very large tuning range of 500 MHz. The phase noise is -112 dBc/Hz at 500 kHz offset. The presented ideas have been incorporated in a commercial Bluetooth transceiver.     

All-digital PLL and transmitter for mobile phones

We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.     

基于自由环振和飞加法器结构的时域数字控制振荡器

A time-domain digitally controlled oscillator （DCO） is proposed. The DCO is composed of a free-running ring oscillator （FRO） and a two lap-selectors integrated flying-adder （FA）. With a coiled cell array which allows uniform loading capacitances of the delay cells, the FRO produces 32 outputs with consistent tap spacing for the FA as reference clocks. The FA uses the outputs from the FRO to generate the output of the DCO according to the control number, resulting in a linear dependence of the output period, instead of the frequency on the digital controlling word input. Thus the proposed DCO ensures a good conversion linearity in a time-domain, and is suitable for time-domain all-digital phase locked loop applications. The DCO was implemented in a standard 0.13μm digital logic CMOS process. The measurement results show that the DCO has a linear and monotonic tuning curve with gain variation of less than 10%, and a very low root mean square period jitter of 9.3 ps in the output clocks. The DCO works well at supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.     

A time-domain digitally controlled oscillator composed of a free running ring oscillator and flying-adder

t supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.     

Novel digitally programmable multiphase voltage controlled oscillator and its stability discussion

In this paper, a novel programmable current-mode multiphase voltage controlled oscillator (MVCO) is presented. The proposed MVCO consists of four identical first-order all-pass filters, which act for delay cells of the MVCO. By switching the programmable MOS switches on and off, the MVCO can provide six or eight different phase sinusoidal signals. Theoretically, the proposed MVCO can provide 2n (n ? 3) different phase sinusoidal signals by cascading n (n ? 3) first-order all-pass delay cells. Compared with previous reported works, this MVCO has the advantages of lower supply voltage, lower power consumption, a smaller chip area and more multi-outputs than other reported works. In particularly, by using programmable switches and cascading more first-order all-pass delay cells, the proposed MVCO can theoretically provide 2n (n ? 3) different phase sinusoidal signals.     

A digitally controlled 2.4-GHz oscillator in 65-nm CMOS

This article presents a 2.4-GHz digitally controlled oscillator (DCO) for the ISM band. The circuit is designed using a 65-nm CMOS technology with an operating voltage of 1.2 V. The DCO comprises an LC oscillator core and the digital interface logic. The measured total frequency range is from 2.26 to 3.04 GHz. Its frequency quantization step is approximately 20 kHz, and using a digital ΣΔ-modulator (SDM), its effective frequency resolution is better than 1 kHz. Current consumption of the oscillator core is tunable through a 6-bit digital word. The measured phase noise is −122 dBc/Hz at 1-MHz offset frequency with 4.8-mA current consumption.     

应用于DVB电视调谐器的低相位噪声数控晶体振荡器设计

本文提出了一种全集成的25-MHz数字控制晶体振荡器。该数控晶体振荡器基于Colpitts结构实现。通过自动幅度控制电路实现相位噪声的优化。通过10位的温度计译码电容阵列实现自动频率控制。测试结果表明,该数控晶体振荡器在1kHz和10kHz频偏处的相位噪声分别为–139 dBc/Hz和–151 dBc/Hz。频率调谐范围约为35ppm,频率精度为0.04ppm。该数控晶体振荡器在SMIC 0.18μm CMOS工艺下实现,电源电压1.8V,消耗电流1mA。     

应用于数字锁相环的NCO设计

本文鉴于数字锁相环在实际应用中对信号频率的准确度和稳定度有较为严格的要求,设计一种应用于数字锁相环的数控振荡器(NCO,Number Controlled Oscillator)。基于直接数字频率合成(DDS)技术,介绍NCO工作原理,基于FPGA实现NCO,关键是相位累加器与波形存储器两个模块的设计,并利用QUARTUS对设计结果进行编译仿真。对NCO杂散信号进行频谱分析,并提出解决方法。该设计有效抑制杂散,修改灵活,便于调试,在数字锁相环设计中可有广泛应用。     

A low-phase-noise digitally controlled crystal oscillator for DVB TV tuners

This paper presents a 25-MHz fully-integrated digitally controlled crystal oscillator(DCXO) with automatic amplitude control(AAC).The DCXO is based on Colpitts topology for one-pin solution.The AAC circuit is introduced to optimize the phase noise performance.The automatic frequency control is realized by a 10-bit thermometer-code segmental tapered MOS capacitor array,ensuring a～35 ppm tuning range and～0.04 ppm frequency step.The measured phase noise results are-139 dBc/Hz at 1 kHz and-151 dBc/Hz at 10 k...     

LMS-based calibration of an RF digitally controlled oscillator for mobile phones

We propose a least-mean square based gain calibration technique of an RF digitally controlled oscillator (DCO) in an all-digital phase-locked loop (ADPLL). The DCO gain of about 12-kHz/least significant bit is subject to process, voltage and temperature variations, but is tracked and compensated in real time. Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wide-band frequency modulation that is independent from the ADPLL loop bandwidth. The technique is part of a single-chip fully compliant Global System for Mobile Communications (GSM)/EDGE transceiver in 90-nm digital CMOS.     

A digitally controlled oscillator system for SAW-less transmitters in cellular handsets

A complete digitally controlled oscillator (DCO) system for mobile phones is presented with a comprehensive study. The DCO is part of a single-chip fully compliant quad-band GSM transceiver realized in a 90-nm digital CMOS process. By operating the DCO at a 4 /spl times/ GSM low-band frequency followed by frequency dividers, the requirement of on-chip inductor Q and the amount of gate oxide stress are relaxed. It was found that a dynamic divider is needed for stringent TX output phase noise while a source-coupled-logic divider can be used for RX to save power. Both dividers are capable of producing a tight relation between four quadrature output phases at low voltage and low power. Frequency tuning is achieved through digital control of the varactors which serve as an RF DAC. Combining a MIM capacitor array and two nMOS transistor arrays of the varactors for the RF DAC, a highly linear oscillator gain which is also insensitive to process shift is achieved. The finest varactor step size is 12 kHz at the 1.6-2.0 GHz output. With a sigma-delta dithering, high frequency resolution is obtained while having negligible phase noise degradation. The measured phase noise of -167 dBc/Hz at 20 MHz offset from 915 MHz carrier and frequency tuning range of 24.5% proves that this DCO system can be used in SAW-less quad-band transmitters for mobile phones.     

Microwave multidiode integral oscillator modules with a controlled range of varactor frequency tuning

Three-and six-diode integral oscillator modules were considered the designs of which ensure the possibility of electric tuning of both the output signal and the bandwidth of varactor frequency tuning. In addition, the six-diode oscillator module simultaneously ensures both the efficient combining of power of diodes with negative resistance at the level of semiconductor chips. Such oscillator modules are designed for operation in the centimeter and millimeter wavelength bands. The results of experimental investigations of prototypes of integral multidiode IMPATT-oscillator modules manufactured with due regard for the results of mathematical simulation were presented.     

A low-power and low-phase-noise LC digitally controlled oscillator featuring a novel capacitor bank

A monolithic low-power and low-phase-noise digitally controlled oscillator(DCO) based on a symmetric spiral inductor with center-tap and novel capacitor bank was implemented in a 0.18μm CMOS process with six metal layers.A third new way to change capacitance is proposed and implemented in this work.Results show that the phase noise at 1 MHz offset frequency is below -122.5 dBc/Hz while drawing a current of only 4.8 mA from a 1.8 V supply. Also,the DCO can work at low supply voltage conditions with a 1.6 ...     

600MHz BiCMOS digitally controlled oscillator for clock recovery and frequency synthesis PLLs

A 16-bit digitally controlled BiCMOS ring oscillator (DCO) is described. This BiCMOS DCO design provides improved frequency stability under thermal fluctuations. Simulations of a 5-stage DCO using 1μm BiCMOS process parameters achieved a controllable frequency range of 90-640MHz with a linear/quasi-linear range of around 300MHz. A tiny test chip was fabricated using MOSIS Orbit 2μm low-cost analogue CMOS process technology that provides a lateral NPN bipolar device option. Monotone frequency gain (frequency vs control-word transfer function) with fine stepping (tuning) over several kHz was verified experimentally, thus auguring the prospect of accurate frequency lock in an all-digital phase-locked loop (ADPLL) application. Worstcase jitter due to digital control transitions at pathological control-word boundaries for the BiCMOS DCO was observed to be less than 50 ps. This BiCMOS design would thus provide performance enhancement in PLL applications such as clock recovery and frequency synthesis.     

Adaptive sidelobe nulling using digitally controlled phase-shifters

Adaptive null-steering arrays which use phase-only weights are examined. The optimal phase weightings are developed and the mathematical equations are reduced to a simplified computational form. Approximations for low sidelobe arrays allow more efficient computations and demonstrate the decomposition of the antenna pattern into a sum of patterns which place gain towards each directional emitter. Computer simulations and breadboard array measurements substantiate the mathematical development and indicate the practicality of the method.