New insights into the relation between channel hot carrier degradation and oxide breakdown short channel nMOSFETs

In this letter, we report new findings in the relation between channel hot-carrier (CHC) degradation and gate-oxide breakdown (BD) in short-channel nMOSFETS biased at V/sub G/>V/sub D/. We observe that the time-to-BD is strongly reduced in the hot carrier regime and that although the channel hot-electron injection into the oxide occurs mainly at the drain side, stress-induced leakage current (SILC) generation and oxide BD always occur at the source side. The results of these measurements indicate that not solely the energy of the injected electrons but also the oxide electric field is determinant in the oxide BD process.     

Characterizing wearout, breakdown and trap generation in thin silicon oxide

A model describing how wearout leads to breakdown in thin silicon oxides has been developed. During wearout defects or traps are generated inside the oxide and at the oxide interfaces. The signature of the trap generation is the permanent change in the transient current, in response to a voltage pulse, from an exponential decay to a 1/time decay. In oxides thinner than approximately 20 nm the dominant trap generation mechanism appears to be determined by the high fields across the oxides and not electron flow through the oxides. Locally higher current densities, flowing through the traps generated during wearout, lead to local breakdown. This model is critically dependent on the measurement of the properties of the traps generated inside the oxides during the wearout phase. The techniques for measurement of these traps and some of their properties have been described. The ability of this model to describe oxide charging, low-level leakages, transient currents, the role of asperities, polarity dependences, and the fluence, time, thickness, voltage and temperature dependences of oxide breakdown distributions has been discussed.     

New insights in polarity-dependent oxide breakdown for ultrathin gate oxide

In this work, a quantitative analysis is applied to resolve the newly reported polarity-dependent charge-to-breakdown (Q/sub BD/) data from thick oxides of 6.8 nm down to ultrathin oxides of 1.9 nm. Three independent sets of Q/sub BD/ data, i.e., n/sup +/poly/NFET stressed under inversion and accumulation, and p/sup +/ poly/PFET under accumulation are carefully investigated. The Q/sub BD/ degradation observed for p-type anodes, either poly-Si or Si-substrate, can be nicely understood with the framework of maximum energy released by injected electrons. Thus, this work provides a universal and quantitative account for a variety of experimental observations in the time-to-breakdown (T/sub BD/) and Q/sub BD/ polarity-dependence of oxide breakdown.     

New insights into the change of voltage acceleration and temperature activation of oxide breakdown

A large database of time-dependent dielectric breakdown study was conducted on 50 Å SiO₂ film over a wide range of temperature (125–300 °C) and a large range of voltage stress (−4.4 to −6.8 V). Using an accurate methodology, we suppress any correlation between voltage and temperature dependence of the voltage acceleration factor and the activation energy. A possible origin of the non-Arrhenius temperature dependence is discussed and a valid window for E-model lifetime prediction is defined. This study shows the high temperature impact on the reliability projection and point at the difficulty to predict the time-to-breakdown using activation energy as an extrapolation parameter.     

Comparison of neutral electron trap generation by hot-carrierstress in n-MOSFET's with oxide and oxynitride gate dielectrics

A comparative study of neutral electron-trap generation due to hot-carrier stress in n-MOSFETs with pure oxide, NH₃-nitrided oxide (RTN), and reoxidized nitrided oxide (RTN/RTO) as gate dielectrics is reported. Results show that neutral electron trap generation is considerably suppressed by nitridation and reoxidation. The nature of neutral traps is described based on the kinetics of trap filling by electron injection into the gate dielectrics immediately after channel hot-electron stress (CHES). Improved endurance of the RTN and RTN/RTO oxides is explained using physical models related to interfacial strain relaxation     

Bipolar stressing, breakdown, and trap generation in thin siliconoxides

Thin silicon oxide films were stressed with bipolar pulses in which the magnitudes of both the positive and negative pulses were independently varied, The time-to-breakdown, the charge-to-breakdown, and the number of traps generated inside of the oxides during the stresses were measured and compared with oxides that had been stressed with unipolar pulses or stressed with constant dc voltages. For the bipolar stresses it was found that the time-to-breakdown, the charge-to-breakdown, and the number of traps generated inside of the oxide all increased as the magnitude of the opposite polarity, nonstressing pulse was increased, until the opposite polarity pulse became large enough to become the stressing pulse. The time-to-breakdown reached a maximum when the magnitude of the stressing pulse was approximately 1 V larger than the magnitude of the nonstressing pulse. The model that was used to explain these increases involved generation of traps inside of the oxide and the lack of spatial correlation between the traps generated by injection from one interface with the traps generated by injection from the other interface     

Hole trap generation in the gate oxide due to plasma-inducedcharging

The paper presents results of hole trapping studies in-thin gate oxide of plasma damaged MOS transistors. Process-induced damage was investigated with antenna test structures to enhance the effect of plasma charging. In addition to neutral electron traps and passivated interface damage, which are commonly observed plasma charging latent damage, we observed and identified hole traps, generated by plasma stress. The amount of hole traps increases with increasing antenna ratio, indicating that the mechanism of hole trap generation is based on electrical stress and current flow, forced through the oxide during plasma etching. The density of hole traps in the most damaged devices was found to be larger than that in reference, undamaged devices by about 100%     

Investigation into the correct statistical distribution for oxide breakdown over oxide thickness range

A critical aspect of integrated circuit manufacturing is the reliability of the components, in particular the gate oxide of transistors and capacitors. There are two statistical distributions, which can be applied to accelerated stress test failure data, namely the Lognormal or the Weibull distributions. The failure data can fit each distribution equally well. However both distributions will give vastly different lifetime predictions and their correct use is crucial for accurate lifetime prediction. A statistical based test, developed with Monte Carlo data, which is designed to decide if a failure data set has an underlying Lognormal or Weibull distribution is applied to empirical Time Dependent Dielectric Breakdown (TDDB) failure tests. The TDDB tests are carried out on 7 nm, 15 nm and 20 nm thick gate oxides. The results generated show the importance of making the correct choice between the two distributions for accurate lifetime prediction and validate the test for different oxide thickness. Also investigated are the effects of choosing the incorrect statistical distribution has on the voltage and temperature acceleration factors.     

Neutral electron trap generation under irradiation in reoxidizednitrided gate dielectrics

In this study we report for the first time results on neutral electron trap generation in reoxidised nitrided oxide dielectrics under various radiation doses and bias conditions and compare the results with the conventional oxides. We see very little electron trap creation in RNO dielectrics for radiation doses up to 5 Mrad (Si) and for bias fields up to ±2.5 MV/cm. We explain our results in RNO and oxide dielectrics using a three step defect creation model     

An approach to statistical analysis of gate oxide breakdown mechanisms

A credible statistical algorithm is required to determine the parameters of the bimodal Weibull mixture distribution exhibited by the gate oxide breakdown phenomenon, consisting of extrinsic early-life defect-induced failures and intrinsic wear-out failure mechanisms. We use a global maximization algorithm called simulated annealing (SA) in conjunction with the expectation–maximization (EM) algorithm to maximize the log-likelihood function of multi-censored gate oxide failure data. The results show that the proposed statistical algorithm provides a good fit to the stochastic nature of the test failure data. The Akaike information criterion (AIC) is used to verify the number of failure mechanisms in the given set of data and the Bayes’ posterior probability theory is utilized to determine the probability of each failure data belonging to different failure mechanisms.     

Onefold coordinated oxygen atom: an electron trap in the silicon oxide

It has been long suggested that the SiOH defect is an electron or “water” trap in silicon dioxide based on some indirect evidences. In this work, quantum calculation on the capturing properties of non-bridging oxygen hole center with unpaired electron SiO^√ and hydrogen defect SiOH in silicon oxide are performed with the ab initio density-functional method. It was found that the SiO^√ defect is an electron trap and this defect should be the responsible candidate for better hardness against radiation for the metal–oxide-semiconductor gate oxide produced by wet oxidation. We found that the SiOH defect could not be an electron trap according to the present calculation results.     

The statistical distribution of percolation current for soft breakdown in ultrathin gate oxide

Soft breakdown in ultrathin gate oxide has been studied using constant voltage stressing. The behavior of current increments resulting from a number of soft breakdown events has been characterized by statistical distribution. It is shown that the distribution of the current increment follows Weibull distribution rather than log normal distribution. The newly established Weibull slope is shown to be independent of the stressed voltage in the range investigated between 4.5 and 5.1 V. The temperature effect study shows that the Weibull slope reduces with increasing testing temperature. Furthermore, a strong dependence of the Weibull slope on the oxide thickness has been found. These observations can be explained well by geometrical configurations of the percolation path.     

Correlation between oxide breakdown and defects in SiC wafers

A correlation between gate oxide breakdown in metal oxide semiconductor (MOS) capacitor structures and structural defects in SiC wafers is reported. The oxide breakdown under high applied fields, in the accumulation regime of the MOS capacitor structure, is observed to occur at locations corresponding to the edge of bulk structural defects in the SiC wafer such as polytype inclusions, regions of crystallographic misorientation, or different doping concentration. Breakdown measurements on more than 50 different MOS structures did not indicate any failure of the oxide exactly above a micropipe. The scatter in the oxide breakdown field across a 10 mm × 10 mm square area was about 50%, and the highest breakdown field obtained was close to 8 MV/cm.     

Impact of correlated generation of oxide defects on SILC and breakdown distributions

A three-dimensional Monte Carlo model for analysis of the reliability of flash memory arrays is developed, and applied to thin tunnel oxide (t/sub ox/ = 5 nm) samples. Good agreement between experimental data and simulation results are obtained, assuming a correlated defect generation in the tunnel oxide of our samples as evidenced in (Ielmini et al., 2004). The impact of correlated defect generation on dielectric breakdown is also addressed by means of a percolation model. It is shown that correlated generation provides no significant degradation of the breakdown lifetime with respect to Poisson statistics.     

Transient isothermal generation at the silicon-silicon oxide interface and the direct determination of interface trap distribution

The theory of transient isothermal generation through the interface traps at the semiconductor-insulator interface is presented. The generation current (I_g) vs time (t) characteristic is obtained in terms of the interface trap distribution throughout the bandgap. It is shown that a plot of I_et vs log_et is a direct image of the energy distribution of the traps in the upper-half of the bandgap (in the case of an n-type semiconductor) and a plot of I_gt vs log_et is a direct image of the trap distribution in the lower-half of the bandgap.     

The effect of hydrogen on trap generation, positive chargetrapping, and time-dependent dielectric breakdown of gate oxides

The effect of high-temperature (≈900°C) hydrogen on the gate oxides of MOS devices is studied. Hydrogen is introduced into devices by either high-temperature anneal or conventional process steps such as low-pressure chemical vapor deposition (LPCVD) of Si₃N₄. In all cases, measurements of high-field stress behavior show that high-temperature hydrogen steps reduce time to breakdown and increase bulk and interface trap generation, but do not affect the generation of positive charge. These results indicate that the wear-out mechanism of gate oxides at high fields is related to trap generation rather than to accumulation of positive charge     

Correlation of trap generation to charge-to-breakdown (Qbd): a physical-damage model of dielectric breakdown

Ultrathin gate and tunnel oxides in MOS devices are subjected to high-field stress during device operation, which degrades the oxide and eventually causes dielectric breakdown. Oxide reliability, therefore, is a key concern in technology scaling for ultra-large scale integration (ULSI). Here we provide critical new insight into oxide degradation (and consequently, reliability) by a systematic study of five technologically relevant parameters, namely, stress-current density, oxide thickness, stress temperature, charge-injection polarity (gate versus substrate), and nitridation of pure oxide. For all five parameters, a strong correlation has been observed between oxide degradation and the generation of new traps (distinct from the filling of intrinsic traps). Further, we observe that this correlation is independent of the trap polarity (positive versus negative). Based on this correlation, and based on the fundamental link between electronic properties and atomic structure, a physical-damage model of dielectric breakdown has been proposed. The concept of the physical-damage model is that the oxide suffers dielectric breakdown when physical damage due to broken bonds forms a defect-filled filamentary path in the oxide, that conducts excessive current. A good monitor of this physical damage is trap generation, which we believe is caused by physical bond breaking in the oxide and at the interface. The model has been quantified empirically by the correlation between trap generation and Q_bd     

A lifetime prediction method for oxide electron trap damage createdduring hot-electron stressing of n-MOS transistors

Electron trap creation under conditions of hot-electron stress (i.e., stress at V_d=V_g) is examined. It is shown that a relationship exists linking lifetime to the injected gate current and drain current, offering a lifetime prediction method for these types of traps. Comparing this type of damage to interface trap (N_it) creation, it is found that larger energies (approximately 1.5 times that for N_it) are required to generate this defect. It is shown that an extrapolation technique can be used to obtain gate currents at working circuit voltages, extending the prediction of lifetimes for oxide trap creation to low voltages     

Introduction of modern telecommunications equipment in Russia andthe New Republics

We describe the process of introducing new equipment for the telecommunications networks of the former USSR, taking into account our personal experience. First, it is important that we are dealing mainly with local switching, so the examples discussed are mainly from this particular field. Today the former Soviet Union is still a united country from the point of view of telecommunications (and telephony in particular). Though different countries have gained their independence, the telephone network is still united and built according to the same technical standards and regulations. In all the new countries; local calls are not billed as yet and additional services are virtually nonexistent, so it is impossible to generate revenue providing them. Local administrations need to install new equipment in order to upgrade their services, thus making it possible to earn more income from users. The three main sources of income are: installation and subscriber fees; payments on a per-call or per-time-unit basis; and payments for services and special features. Currently, the Republic's administrations are trying to increase the first item, which can be achieved by upgrading the old electromechanical switches and the analog network     

Analysis of the relationship between defect site generation anddielectric breakdown utilizing A-mode stress induced leakagecurrent

The dielectric breakdown mechanism is studied from the viewpoint of the relationship with the generation of defect sites in the oxide film, utilizing the “A-mode” stress induced leakage current (A-mode SILC) under the constant-voltage stressing. It is demonstrated that the breakdown occurs when the A-mode SILC becomes a threshold level, I_th. In spite of that, the constant I_th for various stress fields is expected by the conventional model which assumes that each defect site is generated randomly in the oxide film, I _th, increases with the stress field. To explain this variety of I_th by the stress field, the concept of “breakdown-path creation efficiency” (γ_BPC), is proposed, which represents the amount of defect sites in the whole gate area required to create a breakdown path from one side of oxide film to the other side at a local spot. According to this concept, it is demonstrated that the efficiency becomes smaller with the increase in the stress field. These results require us to take account the nonuniform distribution of defect sites in the oxide film into the model for the breakdown mechanism. The introduction of the stress-field dependent depth profile of defect sites allows to explain the variety of I_th