A scalable switched-capacitor filter implemented in 1.25-μmtechnology

An experimental fifth-order, elliptic, PCM filter designed and fabricated in 1.25-μm technology to investigate the scalability of switched-capacitor filters is discussed. The prototype has been experimentally evaluated and meets all D3 requirements. The filter, which was realized in a silicon area of 510 mil², is compared with previous filter implementations     

A real-time programmable switched-capacitor filter

Four independent real-time programmable switched-capacitor filters have been fabricated on a single NMOS chip. The filters are second-order sections with digitally programmable Q and center frequency. Either low-pass or bandpass functions are available by selecting the appropriate input. The device is microprocessor compatible and includes permanent programming capability as well as an on-chip oscillator. The circuit implementation, programming capability, and operation are described.     

A z plane Lerner switched-capacitor filter

The design of a switched-capacitor filter that optimizes both amplitude and phase response simultaneously is described. Conceptually derived from a Lerner function, the filter architecture is efficient and simple.     

A 10.7-MHz switched-capacitor bandpass filter

An experimental 10.7-MHz switched-capacitor bandpass filter is demonstrated that exhibits a 400-kHz bandwidth with a 42-MHz sampling rate. Basic design issues of such high-frequency filters are also addressed with emphasis on dynamic range and power constraints. A theoretical square relation between power and center frequency agrees well with experimental results. The sixth-order differential bandpass filter chip occupies 2 mm² using a 2.25-μm gate double-poly CMOS technology     

A micropower fourth-order elliptical switched-capacitor low-pass filter

A micropower fourth-order elliptical switched-capacitor (SC) low-pass filter for biomedical applications has been designed and measured. The charge transfer error of an SC integrator using a transconductance amplifier is discussed. Also first-order noise and PSRR calculations are performed and compared with the results of simulations and measurements. The measurements show that by careful optimization of the gain bandwidth, slew rate, and gain of the amplifiers, high-performance low-power SC filters can be constructed. The cutoff frequency of the filter is 5 kHz, the ripple in the passband is 0.27 dB, and stopband rejection is 49 dB. The power consumption of the filter is 190 /spl mu/W with /spl plusmn/2.5-V power supplies. The dynamic range of the filter is 75 dB, and the total harmonic distortion over the whole passband range is below 0.25% for a 2-V/SUB pp/ input signal. The PSRR of the filter is above 40 dB at frequencies below 3 kHz.     

Novel switched-capacitor pseudo-N-path filter

The letter presents novel fully stray-insensitive switched-capacitor (SC) pseudo-N-path filters based on the theory of wave-flow networks. N-path filters are well suited for the realisation of narrowband bandpass and bandreject filters. The two main drawbacks of N-path filters, i.e. unwanted mirror frequencies due to path mismatch, and clock feedthrough located in the passband, are overcome by applying the pseudo-N-path principle. The design procedure will be demonstrated using an example of a 6-path filter based on a 3rd-order highpass prototype filter.     

A novel two-amplifier universal active switched-capacitor filter

A switched-capacitor (SC) filter circuit realizing low-pass (LP), high-pass (HP), and bandpass (BP) transfer functions is described. This circuit uses only two operational amplifiers (OAs) and is bottom-plate stray-insensitive.     

Integrated switched-capacitor FDNR filter

A switched-capacitor filter using a frequency-dependent negative resistance (FDNR) is described. FDNR filters closely simulate passive LC filters, thereby retaining passband stability and design simplicity. The filter has been implemented in LSI and designed to perform the transmit/receive filtering for PCM codecs. Circuits are described that overcome the floating node and floating amplifier problems previously associated with FDNRs.     

Recent advancements in continuously scalable conversion-ratio switched-capacitor converter

<正>Switched-capacitor (SC) DC-DC converter^[1] is an important alternative to inductive DC-DC converter, in terms of removing the bulky power inductor. Hence, it is widely used in low-profile, low-power applications, such as the internet of things (IoT) sensor nodes and energy harvesting^[2].     

A scalable high-performance active network node

Active networking in environments built to support link rates up to several gigabits per second poses many challenges. One such challenge is that the memory bandwidth and individual processing power of the router's microprocessors limit the total available processing power of a router. In this article we identify and describe three components, which promise a high-performance active network solution. This implements the key features typical to active networking, such as automatic protocol deployment and application specific processing, and it is suitable for a gigabit environment. First, we describe the hardware of the active network node (ANN), a scalable high-performance platform based on off-the-shelf CPUs connected to a gigabit ATM switch backplane. Second, we introduce the ANN's modular, extensible, and highly efficient operating system (NodeOS). Third, we describe an execution environment running on top of the NodeOS, which implements a novel large-scale active networking architecture called distributed code caching     

开关电容低通滤波器的设计

为了滤除信号中掺杂的高频噪声,设计一种六阶级联式开关电容低通滤波器,以数据采样技术代替传统有源RC滤波器中的大电阻,有利于电路的大规模集成。滤波器由双二阶子电路级联而成,电路中的电容值利用动态定标技术计算确定。用Hspice进行仿真验证,结果表明:开关电容低通滤波器能较好地对信号进行整形,其频率特性符合设计指标。     

A low-power BiCMOS switched-capacitor filter for audio codecapplications

A fully integrated fourth-order filter embedded in a complete 16-b oversampled D/A converter to be used in an audio stereo codec is presented. The possible noise and distortion sources have been accurately evaluated in the design and their contributions have been properly limited. This allows the reduction of the power consumption while satisfying the application requirements. The filter is realized in 0.7-μm BiCMOS technology with an active area of about 1.3 mm² . A total harmonic distortion (THD) of -75 dB for a full scale input signal and an SNR of 96 dB have been achieved. The power consumption of the filter has been maintained within about 40 mW from a single 5-V supply voltage     

Low-distortion switched-capacitor filter design techniques

The distortion mechanism in switched-capacitor (SC) filters are considered, and closed-form expression relating switched-capacitors filter distortion to circuit parameters are derived. Design techniques for low-distortion applications are discussed and are applied to a sixth-order experimental filter. The filter design uses a fully differential class A/B op amp with a continuous-time common-mode feedback circuit. Distortion measurements show that for 82-dB dynamic range (relative to noise floor) the total harmonic distortion of 0.02% within the whole 4-kHz bandwidth and 0.07% within 20-kHz bandwidth.     

1V电源的CMOS开关电容滤波器

本文设计实现了一种低压的开关电容滤波器,该电路采用上华0.8微米标准CMOS工艺实现.本电路是基于一种新的时钟倍增电路实现的一个双二阶带通滤波器,测试结果表明该带通滤波器可以在1V电源电压下正常工作,测试结果与仿真一致.     

A digitally programmable switched-capacitor universal active filter/oscillator

A universal second-order switched-capacitor filter section has been fabricated on an NMOS chip. The device can perform all five basic filter types as well as a sine wave oscillator without external components, while requiring only an external clock. The filter type is determined by selecting one or more of three input pins. The filter response is determined by ten external programming pins which may be either digitally controlled or hard wired.     

A prototype switched-capacitor voltage-wave filter realized in NMOS technology

Presents a novel approach to the realization of monolithic filters. The method is based on using sampled analog signals and is related to the wave digital filter in its design techniques. The eventual monolithic realization in NMOS technology is in the form of a switched-capacitor structure. The design is exact and there is no requirement for a high relative clock frequency. Only unity-gain buffers are required, as opposed to high-gain differential-input operational amplifiers, and so the technique is well suited to CMOS technology. Performance is determined by capacitance ratios and the design is optimally insensitive to parameter variations. Capacitance ratios are moderate relative to those encountered in existing switched-capacitor filters. Results are presented for a prototype integrated circuit design containing fifth- and seventh-order low-pass Chebyshev filters with a designed cutoff at one-eighth clock frequency. The responses achieved for the prototype design show excellent agreement with the theory.     

NOVEL LINEAR TRANSFORMATION SWITCHED-CAPACITOR FILTER DESIGN

This paper presents a novel method that is applied to realize the Linear Transformation(LT)Switched-Capacitor Filter(SCF).It adopts the Voltage Control Voltage Source(VCVS)equalized transfor-mation to revise the original LC ladder filter and induce it into 16 basic sections and then extend the princi-ple of the LT in order to fit active and 3 port networks and give out switched-capacitor circuits corre-sponding to the 16 basic sections,which can realize all four kinds of filters——LP,HP,BP,BS filters.De-signed examples are given here.An Nth order filter only requires N amplifiers and the circuit is insensitive toparasitic capacitances.The experimental results of a 3rd order elliptic LP and a 6th order elliptic BP are giv-en and agree with the theory.     

High-frequency switched-capacitor filter using unity-gain buffers

The implementation of high-frequency switched-capacitor filters using unity-gain amplifiers in a balanced configuration is described. The effect of parasitic capacitances is analyzed for different structures, single-ended and balanced. Experimental results from a third-order elliptic filter integrated in a standard NMOS process are presented.