共查询到19条相似文献,搜索用时 46 毫秒
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高隔离度宽带双极化微带天线设计 总被引:2,自引:0,他引:2
双极化天线由于具有极化分离的优异性能,在无线通信系统中引起了广泛关注,因此本文设计了一个高隔离度宽带双极化微带缝隙天线.为了获得高隔离度特性,该天线采用两个不同结构的微带线馈电,分别激励起垂直极化和水平极化模式.同时在地板上开缝隙来展宽天线带宽和实现天线的小型化.仿真优化结果表明,该天线端口1和端口2的阻抗带宽分别为51%和62%,在1.71GHz~2.69GHz整个工作频带范围内两端口之间的隔离度高于40dB,且结构简单,适用于移动通信的实际应用中. 相似文献
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在固态毫米波功率放大器设计中,单片MMIC 输出功率较小,提高系统功率的有效方法是采用功率合成技术,目前的功率合成技术存在的设计难点是提高各分配支路间的隔离度。本文基于对传统魔T 的分析和改进,提出了一种高隔离度的3 dB 功率分配结构。经实验测试,运用该结构设计的功率分配器,在29.3-39.3GHz 的频带内两等分支路之间的隔离度可高达-42dB,两支路的不平衡度低于0.1dB,插入损耗优于-0.25dB,很好地满足了实际应用的要求。 相似文献
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基于电磁场全波分析方法,设计了一种V 波段Y 型结E 面波导功分器,采用多节阶梯阻抗匹配结构实现宽频带;在主传输波导H 面中心插入阻性薄膜的陶瓷基板来提高输出端口隔离度。波导功分器采用硅铝材料制作,具有重量轻、热膨胀系数低、导热良好的优点,与陶瓷基片匹配良好。实测结果表明,在50~60 GHz 频带内,传输损耗优于0. 4 dB,典型隔离度25 dB,两路输出幅度一致性优于0. 19 dB,相位不平衡度优于1. 4°;功率容量理论值可达33 kW。经可靠性试验验证,证明该功分器可靠性高、适合工程使用。 相似文献
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Ali Reza Hazeri 《International Journal of Electronics》2013,100(4):575-584
The challenge facing SerDes (Serialiser De-Serialiser) designers is common with all current communications technologies. Industry advances show a trend to increase speed, reduce power and improve efficiency. In this article a novel line driver that can operate at speeds of up to 40 Gbps with a power supply of 1?V and a power consumption of 4.54?mW/Gb/s is presented. Pre-distortion on the front-end is used to maintain signal integrity. 相似文献
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A novel dual-frequency power divider with isolation stubs is presented. To reduce the parasitic effects between the two stubs that are connected by the isolation resistor in traditional Wilkinson power dividers, a structure consisting of isolation stubs is proposed. The corresponding design equations are obtained to calculate the design parameters of the desired dual-frequency power divider. Finally, this design concept is validated by experimental results on a 0.95/2.09 GHz dual-frequency power divider. 相似文献
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Yu X.P. Do M.A. Jia L. Ma J.G. Yeo K.S. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2005,13(9):1098-1103
The design of a high-speed wide-band high resolution programmable frequency divider is investigated. A new reloadable D flip-flop for the high speed programmable frequency divider is proposed. It is optimized in terms of propagation delay and power consumption as compared with the existing designs. Measurement results show that an all-stage programmable counter implemented with this D flip-flop using the Chartered 0.18 /spl mu/m CMOS process is capable of operating up to 1.8 GHz for a 1.8 V supply voltage and a 5.8-mW power consumption. By using this counter, an ultra-wide range high resolution frequency divider is achieved with low power consumption for 5-6-GHz wireless LAN applications. 相似文献
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介绍了微带任意分配比的混合型功率分配器的设计原理及关键技术,着重描述了研制出的一种微带混合型2路功率分配器的设计和性能,并给出了它的性能测试结果。通过这种方法,可设计出任意比的混合型2路功率分配器,通过级联的方式还可得到任意比的混合型多路功率分配器。 相似文献