Charge trapping and interface states in hydrogen annealed HfO2–Si structures

Metal–oxide–semiconductor (MOS) capacitors based on HfO₂ gate stacks with Al and TiN gates are compared to study the effect of the gate electrode material to the properties of insulator–semiconductor interface. The structures under study were shown to contain interface trap densities of around 2 × 10¹¹ cm⁻² eV⁻¹ for Al gate and up to 5.5 × 10¹² cm⁻² eV⁻¹ for TiN gate. The peak in the surface state distribution was found at 0.19 eV above the valence band edge for Al electrode. The respective capture cross-section is 6 × 10⁻¹⁷ cm² at 200 K.The charge injection experiments have revealed the presence of hole traps inside the dielectric layer. The Al-gate structure contains traps with effective capture cross-section of 1 × 10⁻²⁰ cm², and there are two types of traps in the TiN-gate structure with cross-sections of 3.5 × 10⁻¹⁹ and 1 × 10⁻²⁰ cm². Trap concentration in the structure with Al electrode was considerably lower than in the structure with TiN electrode.     

Walk-out phenomena in 6H-SiC mesa diodes with SiO2/Si3N4 passivation and charge trapping in dry and wet oxides on N-type 6H-SiC

The drift or “walk-out” of the breakdown voltage in 6H-SiC mesa diodes passivated by a double layer of 1000 Å SiO₂ and 3000 Å Si₃N₄ was studied and related to the charge trapping in the oxide. The first-order trapping kinetics using four distinct electron traps with trapping cross-sections in the range 10⁻¹⁶ to 10⁻¹⁹ cm² were found to best describe the breakdown voltage drift curves. The wet oxide trapping cross-sections are 2 to 10 times larger compared to the dry oxide ones, resulting in about one order of magnitude faster charging of the traps. No significant differences in the amount of drift and saturation level of breakdown voltage were found between the different passivations. The influence of UV illumination, supplied by a HeCd laser with wavelength 325 nm, on the walk-out characteristics and on the reverse current was also investigated. The build-up of the surface states was observed in wet oxide under UV illumination and DC stress. The results are consistent with the coexistence of large concentrations of positive charge and acceptor type deep interface electron traps. The walk-out is a result of the acceptor states being filled by hot electrons supplied by the mechanism of avalanche injection. The suitability of the walk-out measurements as a tool for characterisation of the charge trapping properties of the passivation is demonstrated.     

Effects of oxygen partial pressure on structural and electrical characteristics of HfAlO high-k gate dielectric grown on strained SiGe by pulsed-laser deposition

Dependence of oxygen partial pressures on structural and electrical characteristics of HfAlO (Hf:Al=1:1) high-k gate dielectric ultra-thin films grown on the compressively strained Si₈₃Ge₁₇ by pulsed-laser deposition were investigated. The microstructure and the interfacial structure of the HfAlO thin films grown under different oxygen partial pressures were studied by transmission electron microscopy, and the their electrical properties were characterized by capacitance–voltage (C−V) and conductance–voltage measurements. Dependence of interfacial layer thickness and C–V characteristics of the HfAlO films on the growth of oxygen pressure was revealed. With an optimized oxygen partial pressure, an HfAlO film with an effective dielectric constant of 16 and a low interface state density of 2.1×10¹⁰ cm⁻² eV⁻¹ was obtained.     

Investigation of high-K gate stacks with epitaxial Gd2O3 and FUSI NiSi metal gates down to CET=0.86 nm

Novel gate stacks with epitaxial gadolinium oxide (Gd₂O₃) high-k dielectrics and fully silicided (FUSI) nickel silicide (NiSi) gate electrodes are investigated. Ultra-low leakage current densities down to 10^–7 A cm^–2 are observed at a capacitance equivalent oxide thickness of CET=1.8 nm. The influence of a titanium nitride (TiN) capping layer during silicidation is studied. Furthermore, films with an ultra-thin CET of 0.86 nm at a Gd₂O₃ thickness of 3.1 nm yield current densities down to 0.5 A cm⁻² at V_g=+1 V. The extracted dielectric constant for these gate stacks ranges from k=13 to 14. These results emphasize the potential of NiSi/Gd₂O₃ gate stacks for future material-based scaling of CMOS technology.     

Study of electrically active defects in n-GaN layer

Deep level defects in both p⁺/n junctions and n-type Schottky GaN diodes are studied using the Fourier transform deep level transient spectroscopy. An electron trap level was detected in the range of energies at E_c−E_t=0.23–0.27 eV with a capture cross-section of the order of 10⁻¹⁹–10⁻¹⁶ cm² for both the p⁺/n and n-type Schottky GaN diodes. For one set of p⁺/n diodes with a structure of Au/Pt/p⁺–GaN/n–GaN/n⁺–GaN/Ti/Al/Pd/Au and the n-type Schottky diodes, two other common electron traps are found at energy positions, E_c−E_t=0.53–0.56 eV and 0.79–0.82 eV. In addition, an electron trap level with energy position at E_c−E_t=1.07 eV and a capture cross-section of σ_n=1.6×10⁻¹³ cm² are detected for the n-type Schottky diodes. This trap level has not been previously reported in the literature. For the other set of p⁺/n diodes with a structure of Au/Ni/p⁺–GaN/n–GaN/n⁺–GaN/Ti/Al/Pd/Au, a prominent minority carrier (hole) trap level was also identified with an energy position at E_t−E_v=0.85 eV and a capture cross-section of σ_n=8.1×10⁻¹⁴ cm². The 0.56 eV electron trap level observed in n-type Schottky diode and the 0.23 eV electron trap level detected in the p⁺/n diode with Ni/Au contact are attributed to the extended defects based on the observation of logarithmic capture kinetics.     

Electrically active defects induced by hydrogen and helium implantations in Ge

Results of a study of electrically active defects induced in Sb-doped Ge crystals by implantations of hydrogen and helium ions (protons and alpha particles) with energies in the range from 500 keV to 1 MeV and doses in the range 1×10¹⁰–1×10¹⁴ cm⁻² are presented in this work. Transformations of the defects upon post-implantation isochronal anneals in the temperature range 50–350 °C have also been studied. The results have been obtained by means of capacitance–voltage (C–V) measurements and deep-level transient spectroscopy (DLTS).It was found from an analysis of DLTS spectra that low doses (<5×10¹⁰ cm⁻²) of H and He ion implantations resulted in the introduction of damage similar to that observed after MeV electron irradiation. The Sb–vacancy complex was the dominant deep-level defect in the lightly implanted samples. After implantations with doses higher than 5×10¹⁰ cm⁻² peaks due to more complex defects were observed in the DLTS spectra. Implantations with heavy (5×10¹³ cm⁻²) doses of both H and He ions caused the formation of a sub-surface layer with a high (up to 1×10¹⁷ cm⁻³) concentration of donors. These donors were eliminated by anneals at temperatures in the range 100–200 °C. Heat treatments of the heavy proton-implanted Ge samples in the temperature range 250–300 °C resulted in the formation of shallow hydrogen-related donors, the concentration of which was the highest in a region close to the projected depth of implanted protons. The maximum peak concentration of the H-related donors was higher than 1×10¹⁵ cm⁻³ for a proton implantation dose of 1×10¹⁴ cm⁻².     

ZrAlO ternary oxide as a candidate for high-k dielectrics

ZrAlO thin films were prepared by the pyrosol process. Four different cases were considered taking as basis a solution of 0.025 M zirconium acetylacetonate (ZrAAc) and 5 at% of aluminum acetylacetonate (AlAAc) dissolved in pure methanol. Films of case A, were deposited with the mentioned solution and subjected to rapid thermal annealing (RTA). For case B, a small volume of water was added to start solution. Case C, were similar samples of case B, but with a post-deposition RTA. Case D, were Si/Al₂O₃/ZrAlO/Al stacks with post-deposition RTA, using water in the start solution. XPS profiles show that the relative chemical composition of deposited materials is affected by the volume of water added (Vw). The aluminum concentration in the films acquires values as high as or higher than zirconium concentration for increasing Vw. All the prepared samples were amorphous as indicated by the X-ray diffraction (XRD) spectra, even for large integration times. Current–voltage (I–V) and capacitance measurements were carried out in metal–insulator–metal (MIM) devices (Corning-glass/TCO/ZrAlO/Al) and I–V and simultaneous capacitance–voltage (C–V) measurements were performed in metal–oxide–semiconductor (MOS) devices (Si/ZrAlO/Al and Si/Al₂O₃/ZrAlO/Al). Leakage currents of the order of 10⁻⁴ A/cm², were typically obtained in MIM devices, whereas for some MOS devices, leakage currents of the order of 10⁻⁷ A/cm² were obtained. Dielectric constant (k) values of the order of 24 were calculated for MIM devices and k values ranging from 12.5 up to 17 were calculated for MOS devices.     

Charge trapping in ultrathin Gd2O3 high-k dielectric

Charge trapping in ultrathin high-k Gd₂O₃ dielectric leading to appearance of hysteresis in C-V curves is studied by capacitance-voltage and current-voltage techniques. It was shown that the large leakage current at a negative gate voltage causes the generation of the positive charge in the dielectric layer, resulting in the respective shift of the C-V curve. The capture cross-section of the hole traps is around 2 × 10⁻²⁰ cm². The distribution of the interface states was measured by conductance technique showing the concentration up to 7.5 × 10¹² eV⁻¹ cm⁻² near the valence band edge.     

Carrier effective mobilities in germanium MOSFET inversion layer investigated by Monte Carlo simulation

This paper presents the Monte Carlo studies of inversion mobility in Ge MOSFETs covering a wide range of bulk-impurity concentrations (10¹⁴ cm⁻³–10¹⁷ cm⁻³), and substrate bias (0–10 V). Carrier mobilities in Ge MOSFETs have obviously increased compared with those in Si MOSFETs. At low effective field, both electron and hole mobilities have increased over 100%; while at high effective field the increase is reduced due to the effect of surface roughness. Similar to Si MOSFETs, the carrier effective mobilities in Ge MOSFETs also have a universal behavior. The universality of both electron and hole mobilities holds up to a bulk-impurity concentration of 10¹⁷ cm⁻³. On substrates with higher bulk-impurity concentrations, the carrier effective mobilities significantly deviate from the universal curves under low effective field because of Coulomb scattering by the bulk impurity.     

Process integration and nanometer-scale electrical characterization of crystalline high-k gate dielectrics

Crystalline praseodymium oxide (Pr₂O₃) high-k gate dielectric has been successfully integrated into a polysilicon gate CMOS technology. Fully functional MOSFETs with an equivalent oxide thickness (EOT) of 1.8 nm and gate leakages below 10⁻⁶ A/cm² have been fabricated. However, at this early stage of development the transistors show Vt-instabilities and unusual high gate leakage for L > 10 μm. As a first attempt to explain the observed macroscopic device characteristics, topographical and electrical measurements at the nanometer scale have been performed directly on the Pr₂O₃ surface by Conductive Atomic Force Microscopy (C-AFM). This technique allows to discriminate between structural defect sites and charge trapping centers.     

High temperature characterization of high-κ dielectrics on SiC

We have fabricated thin catalytic metal–insulator–silicon carbide based structure with palladium (Pd) gates using TiO₂ as the dielectric. The temperature stability of the capacitor is of critical importance for use in the fabrication of electronics for deployment in extreme environments. We have evaluated the response to temperatures in excess of 450 °C in air and observed that the characteristics are stable. Results of high temperature characterization are presented here with extraction of interface state density up to 650 °C. The results show that at temperatures below 400 °C the capacitors are stable, with a density of interface traps of approximately 6×10¹¹ cm² eV⁻¹. Above this temperature the C–V and G–V characteristics show the influence of a second set of traps, with a density around 1×10¹³ cm² eV⁻¹, which is close to that observed for slow states near the conduction band edge. The study of breakdown field as a function of temperature shows two distinct regions, below 300 °C where the breakdown voltage has a strong temperature dependence and above 300, where it is weaker. We hypothesize that the oxide layer dominates the breakdown voltage at low temperature and the TiO₂ layer above 300 °C. These results at high temperatures confirms the suitability of the Pd/TiO₂/SiO₂/SiC capacitor structure for stable operation in high temperature environments.     

Effects of the metal gate on the stress-induced traps in Ta2O5/SiO2 stacks

The degradation of Ta₂O₅-based (10 nm) stacked capacitors with different top electrodes, (Al, W, Au) under constant current stress has been investigated. The variation of electrical characteristics after the stress is addressed to gate-induced defects rather than to poor-oxidation related defects. The main wearout parameter in Ta₂O₅ stacks is bulk-related and a generation only of bulk traps giving rise to oxide charge is observed. The post-stress current–voltage curves reveal that stress-induced leakage current (SILC) mode occurs in all capacitors and the characteristics of pre-existing traps define the stress response. The results are discussed in terms of simultaneous action of two competing processes: negative charge trapping in pre-existing electron traps and stress-induced positive charge generation, and the domination of one of them in dependence on both the stress level and the gate used. The charge build-up and the trapping/detrapping processes modify the dominant conduction mechanism and the gate-induced defects are precursors for device degradation. It is concluded that the impact of the metal gate on the ultimate reliability of high-k stacked capacitors should be strongly considered.     

Fabrication and characterization of air-stable, ambipolar heterojunction-based organic light-emitting field-effect transistors

We present our first application of the neutral cluster beam deposition (NCBD) method to fabricate bilayer heterojunction-based organic light-emitting field-effect transistors (OLEFETs) by superimposing two layers of α,ω-dihexylsexithiophene (DH6T) and N,N′-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (P13) successively. Based upon well-balanced ambipolarity (hole and electron field-effect mobilities of 2.22 × 10⁻² and 2.78 × 10⁻² cm²/Vs), the air-stable OLEFETs have demonstrated good field-effect characteristics, stress-free operational stability and electroluminescence under ambient condition.     

Low-temperature conductance measurements of surface states in HfO2–Si structures with different gate materials

Metal-oxide-semiconductor capacitors based on HfO₂ gate stack with different metal and metal compound gates (Al, TiN, NiSi and NiAlN) are compared to study the effect of the gate electrode material on the trap density at the insulator–semiconductor interface.C–V and G–ω measurements were made in the frequency range from 1 kHz to 1 MHz in the temperature range 180–300 K. From the maximum of the plot G/ω vs. ln(ω) the density of interface states was calculated, and from its position on the frequency axis the trap cross-section was found. Reducing temperature makes it possible to decrease leakage current through the dielectric and to investigate the states located closer to the band edge.The structures under study were shown to contain significant interface trap densities located near the valence band edge (around 2×10¹¹ cm⁻²eV⁻¹ for Al and up to (3.5–5.5)×10¹² cm⁻² eV⁻¹ for other gate materials). The peak in the surface state distribution is situated at 0.18 eV above the valence band edge for Al electrode. The capture cross-section is 5.8×10⁻¹⁷ cm² at 200 K for Al–HfO₂–Si structure.     

Electrical properties of SiO2/TiO2 high-k gate dielectric stack

The trapping/detrapping behavior of charge carriers in ultrathin SiO₂/TiO₂ stacked gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Titanium tetrakis iso-propoxides (TTIP) was used as the organometallic source for the deposition of ultra-thin TiO₂ films at low temperature (<200 °C) on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. Stress-induced leakage current (SILC) through SiO₂/TiO₂ stacked gate dielectric is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of TiO₂ layer. The increase in the gate current density observed during CVS from room temperature up to 125 ^oC has been analyzed and modeled considering both the buildup of charges in the layer as well as the SILC contribution. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. A temperature-dependent trap generation rate and defects have also been investigated using time-dependent current density variation during CVS. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating high-k stacked layers. SILC generation kinetics, i.e. defect generation probability under different injected fluences for various high-constant stress voltages in both polarities have been studied. An empirical relation between trap generation probability and applied stress voltage for various injected fluences has been developed.     

Determination of the electronic parameters of nanostructure SnO2/p-Si diode

The current–voltage and capacitance–voltage characteristics of the nanostructure SnO₂/p-Si diode have been investigated. The optical band gap and microstructure properties of the SnO₂ film were analyzed by optical absorption method and scanning electron microscopy, respectively. The optical band of the film was found to be 3.58 eV with a direct optical transition. The scanning electron microcopy results show that the SnO₂ film has the nanostructure. The ideality factor, barrier height and series resistance values of the nanostructure SnO₂/p-Si diode were found to be 2.1, 0.87 eV and 36.35 kΩ, respectively. The barrier height obtained from C–V measurement is higher than obtained from I–V measurement and this discrepancy can be explained by introducing a spatial distribution of barrier heights due to barrier height inhomogeneities, which are available at the nanostructure SnO₂/p-Si interface. The interface state density of the diode was determined by conductance technique and was found to be 8.41 × 10¹⁰ eV⁻¹ cm⁻².It is evaluated that the nanostructure of the SnO₂ film has an important effect on the ideality factor, barrier height and interface state density parameters of SnO₂/p-Si diode.     

An investigation of surface state capture cross-sections for metal–oxide–semiconductor field-effect transistors using HfO2 gate dielectrics

MOSFETs and MOSCs incorporating HfO₂ gate dielectrics were fabricated. The I_DS–V_DS, I_DS–V_GS, gated-diode and C–V characteristics were investigated. The subthreshold swing and the interface trap density were obtained. The surface recombination velocity and the minority carrier lifetime in the field-induced depletion region measured from the gated diodes were about 2.73 × 10³ cm/s and 1.63 × 10⁻⁶ s, respectively. The effective capture cross section of surface state was determined to be 1.6 × 10⁻¹⁵ cm² using the gated-diode technique in comparison with the subthreshold swing measurement. A comparison with conventional MOSFETs using SiO₂ gate oxide was also made.     

Hole trapping in E-beam irradiated SiO2 films

Low energy (25 kV) electron beam irradiation of MOS capacitors is shown to produce neutral hole traps in thin ‘radiation hardened’ SiO₂ films. These traps are found in an uncharged state after irradiation and are populated by passing a small hole current, generated by avalanche breakdown of then-type silicon substrate, through the oxide. From the time dependence of the observed trapping, a capture cross-section between 1 × 10∼⁻¹³ and 1 × 10⁻¹⁴ cm² is deduced. The trap density is found to depend on the annealing conditions and incident electron beam dosage. The density of traps increases with incident electron beam exposure. Once introduced into the oxide by the radiation the traps can be removed by thermal anneals at temperatures above 500° C. Parallels between electron and hole trapping on these neutral centers are strong evidence for an amphoteric uncharged trap generated by ionizing radiation.     

Investigation of Au/Ti/Al ohmic contact to N-type 4H–SiC

In this study, investigation on Au/Ti/Al ohmic contact to n-type 4H–SiC and its thermal stability are reported. Specific contact resistances (SCRs) in the range of 10⁻⁴–10⁻⁶ Ω cm², and the best SCR as low as 2.8 × 10⁻⁶ Ω cm² has been generally achieved after rapid thermal annealing in Ar for 5 min at 800 °C and above. About 1–2 order(s) of magnitude improvement in SCR as compared to those Al/Ti series ohmic systems in n-SiC reported in literature is obtained. XRD analysis shows that the low resistance contact would be attributed to the formation of titanium silicides (TiSi₂ and TiSi) and Ti₃SiC₂ at the metal/n-SiC interface after thermal annealing. The Au/Ti/Al ohmic contact is thermally stable during thermal aging treatment in Ar at temperature in the 100–500 °C range for 20 h.     

Low temperature processed hafnium oxide: Structural and electrical properties

In this work hafnium oxide (HfO₂) was deposited by r.f. magnetron sputtering at room temperature and then annealed at 200 °C in forming gas (N₂+H₂) and oxygen atmospheres, respectively for 2, 5 and 10 h. After 2 h annealing in forming gas an improvement in the interface properties occurs with the associated flat band voltage changing from −2.23 to −1.28 V. This means a reduction in the oxide charge density from 1.33×10¹² to 7.62×10¹¹ cm⁻². After 5 h annealing only the dielectric constant improves due to densification of the film. Finally, after 10 h annealing we notice a degradation of the electrical film's properties, with the flat band voltage and fixed charge density being −2.96 V and 1.64×10¹² cm⁻², respectively. Besides that, the leakage current also increases due to crystallization. On the other hand, by depositing the films at 200 °C or annealing it in an oxidizing atmosphere no improvements are observed when comparing these data to the ones obtained by annealing the films in forming gas. Here the flat band voltage is more negative and the hysteresis on the C–V plot is larger than the one recorded on films annealed in forming gas, meaning a degradation of the interfacial properties.