Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF（2^m）

An error tolerant hardware efficient verylarge scale integration （VLSI） architecture for bitparallel systolic multiplication over dual base, which canbe pipelined, is presented. Since this architecture has thefeatures of regularity, modularity and unidirectionaldata flow, this structure is well suited to VLSIimplementations. The length of the largest delay pathand area of this architecture are less compared to the bitparallel systolic multiplication architectures reportedearlier. The architecture is implemented using Austria Micro System＇s 0.35 μm CMOS （complementary metaloxide semiconductor） technology. This architecture canalso operate over both the dual-base and polynomialbase.     

一种高速自适应Reed-Solomon译码结构及其VLSI优化实现

该文给出了一种自适应Reed-Solomon(RS) 译码器结构。该结构可以自适应地处理长度变化的截短码编码数据块,适合于高速译码处理。该结构使译码处理不受数据块间隙长短的约束,既可以处理独立的编码数据块也可以处理连续发送的编码数据块。另外本译码器结构可以保证输出数据块间隔信息的完整性,满足无线通信和以太网中特殊业务的要求。本文还基于该结构对RS(255,239)译码器予以实现,该译码器经过Synopsys综合工具综合并用TSMC 0.18 CMOS工艺实现,测试结果验证了该译码器的自适应功能和译码正确性,其端口处理速率可达1.6Gb/s。     

Novel direct designs for 3-input XOR function for low-power and high-speed applications

Novel direct designs for 3-input exclusive-OR (XOR) function at transistor level are proposed in this article. These designs are appropriate for low-power and high-speed applications. The critical path of the presented designs consists of only two pass-transistors, which causes low propagation delay. Neither complementary inputs, nor V _DD and ground exist in the basic structure of these designs. The proposed designs have low dynamic and short-circuit power consumptions and their internal nodes dissipate negligible leakage power, which leads to low average power consumption. Some effective approaches are presented for improving the performance, voltage levels, and the driving capability and lowering the number of transistors of the basic structure of the designs. All of the proposed designs and several classical and state-of-the-art 3-input XOR circuits are simulated in a realistic condition using HSPICE with 90 nm CMOS technology at six supply voltages, ranging from 1.3 V down to 0.8 V. The simulation results demonstrate that the proposed circuits are superior in terms of speed, power consumption and power-delay product (PDP) with respect to other designs.     

Feasibility of BCB as an interlevel dielectric in integrated circuits

This paper investigates the feasibility of using an organic polymer based on benzocyclobutene as an interlevel dielectric material in very large scale integrated (VLSI) circuits. The material is a thermoset resin with attractive electrical and mechanical properties for application as an interlevel dielectric in VLSI circuits. It has a low relative dielectric constant of 2.7. The single coating planarization achieved by spin coating the material is superior to currently used materials and makes it a very attractive material for the fabrication of multilevel metal systems. The planarization properties of this material are presented and compared with those of polyimide. The patterning and dry etching of BCB to define 1 μm vias is described. As the material has limited thermal stability at temperatures greater than 350°C, compatible materials for low via resistivity have been investigated using a double level metal structure. The effect of post metal anneals on via resistivity of various via structures is presented. It is found that a low via resistivity of 3 × 10^-9 gW-cm² without any post metal anneal is obtained by using an AlCu/Pd-AlCu metallurgy.     

基于基金会现场总线协议的接口芯片设计

介绍了一个基于基金会现场总线协议的专用接口芯片设计。该芯片（HKFF）依据IEC61158标准的物理层及数据链路层规范设计,实现接收和发送31．25kbit／s的数据处理,帧同步,自动地址匹配,帧检测序列产生／校验。曼彻斯特编解码等功能。为便于软件的操作,该芯片含有若干特殊寄存器。HKFF芯片设计完成后,采用TSMC0．25微米工艺一次流片成功。     

基于VHDL语言实现FPGA设计

介绍采用VHDL语言在现场可编程门阵列器件(FPGA)上实现通用芯片8255的设计,并简要介绍8255的结构,给出VHDL语言设计程序。     

超大规模集成电路的可制造性设计

以Synopsys推出的TCAD软件TSUPREM-Ⅳ和Medici为蓝本,结合100nm栅长PMOSFET的可制造性联机仿真与优化实例,阐述了超大规模集成电路DFM阶段所进行的工艺级、器件物理特性级优化及工艺参数的提取。     

Edge‐Preserving Algorithm for Block Artifact Reduction and Its Pipelined Architecture

This paper presents a new edge‐protection algorithm and its very large scale integration (VLSI) architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge‐protection maps. Based on these maps, a two‐step adaptive filter which includes offset filtering and edge‐preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory‐reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is verified on FPGA Cyclone II and implemented using the ANAM 0.25 µm CMOS cell library. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details. The PSNR performance of our algorithm using pixel classification is better than that of previous algorithms using block classification.     

CDPD系统中RS译码器的改进设计与实现

以蜂窝数字分组数据(CDPD)系统中的RS(63,47)码为例,提出了一种建立在伽罗华域(GaloisFields)广义三角基乘法器基础上的改进的Reed-Solomon译码器电路。在该译码器的设计中,针对CDPD系统中RS(63,47)码的特点,采用了改进的快速钱氏-BRS根搜索算法来求解它的根并且应用流水线等技术来优化系统设计,从而节省了硬件资源并且提高了速度,使得译码器的性能得到很大的改善。所设计的译码器不但完全满足CDPD系统的设计要求,而且电路结构易于超大规模集成电路(VLSI)的实现,具有广泛的适用范围。     

SSN研究及其在VLSI设计流程中的应用

本文详述了同步开关噪声(SSN)影响VLSI电路可靠性的一个主要因素:芯片-封装界面的寄生电感.根据在芯片中插入电源/地线引脚,减小芯片-封装界面的寄生电感的思想,提出一种简便有效的基于SSN性能的输出驱动器优化布局方法并将之集成到VLSI设计流程中.用0.6微米CMOS工艺进行了验证.结果表明 :该优化设计可有效降低SSN对VLSI电路可靠性的影响.     

基于MPEG-4的视频联合信源信道编码

该文提出了一种用于提高MPEG-4码流在噪声信道下的抗误码性能的联合信源信道编码方法。该方法将MPEG-4基本层按重要性进行码流重排后进行交织打包,并根据率失真函数将基本层纹理信息进一步划分为多个子层。编码器根据反映信道状态的反馈信息动态地调整传输的子层数目和每个子层的纠错强度(信道编码速率),使得系统失真最小。仿真结果表明,该方法明显优于未保护的MPEG-4方法,在相同信道带宽及丢包率条件下比等纠错保护的MPEG-4编码方法获得更加稳定的性能。同时由于该方法根据反馈的出错分组数进行传输子层数和纠错强度的联合优化,与Puri等人提出的按照确定信道条件设计目标函数进行优化的MDFEC方法相比,更能够适应信道条件的变化,从而获得更高的性能。     

一种低资源消耗的运动估计VLSI实现算法

现有的VLSI(verylarge scale integration)视频编码芯片多使用全搜索运动估计(ME)方法,且没有搜索中心偏移(CB)的并行实现方法。本文提出一种适合VLSI的H.264、AVS CB并行搜索方案,减少搜索点数量,降低逻辑资源的消耗,并且使用预测高概率区域的方法,保证ME精度。实验表明,本方法具备较好的率失真性能。在现场可编程门阵列(FPGA)平台上实现了本算法,逻辑综合的数据表明,硬件资源消耗降低了64%。本算法可应用于标清和高清电视(HDTV,hign-definition television)视频编码器。     

基于VHDL语言的GF(28)上快速乘法器设计

基于有限域上多项式乘法理论,采用高层次设计方法,采用CPLD实现了GF(2^8)上8位快速乘法器,利用XILINX公司的Foundation Series3．1i集成设计环境完成了快速乘法器的VHDL源代码输入、功能仿真、布局与布线、时序仿真,并用XC9572PC84可编程逻辑芯片验证了该电路设计。该乘法器可以应用于RS(255,223)码编／译码器。     

基于中国剩余定理分解的RS码快速盲识别算法

该文提出一种新的RS (Reed Solomon)码盲识别方法。该方法利用RS码等效二进制准循环码的代数结构,将截获到的二进制码序列映射为环上的线性码,应用中国剩余定理(Chinese Remainder Theorem, CRT)将环上的线性码进行直和分解,计算不同码长下所有本原多项式对应分量码在相应码空间的归一化维数,通过寻找归一化维数的最小值,实现对RS码码长和本原多项式的识别;最后通过对码字进行因式分解识别RS码的生成多项式。该方法具有使用数据量少,运算量低等方面的特点。仿真结果表明,能完成在较高误码率的情况下对RS码的快速盲识别。     

长距离高速光纤通信中的前向纠错编码技术

前向纠错编码是实现长距离高速光纤通信的关键技术。简述了纠错码与差错控制的基本概念, 结合ITU-T的最新标准G. 707, G. 709和G.975, 着重分析并比较了目前光纤通信中所采用的两种差错控制编码技术(带内FEC与带外FEC)及其性能, 最后给出了计算机仿真结果。     

多通道PCI总线DMA控制器的软硬件联合设计

对一种支持128个用户的PCI(Peripheral Component Interconnect)总线直接存储器访问控制器(DMAC：Direct Memoory Access Controller)电路所采用的电路结构进行了分析，在任务级上对电路的功能进行了划分，并通过仿真得到了不同任务分别在采用嵌入式软件和硬件逻辑电路实现时的时间开销和硬件资源开销。在此基础上，采用面向软件的软硬件联合设计方法，以13．5万等效门实现了整个设计，并通过现场可编程门阵列(FPGA)在实际应用系统中进行了功能验证。     

一种电迁移测试失效时间判定方法

采用铜大马士革工艺制备了用于电迁移测试的样品,对电迁移测试过程中存在的两类电阻-时间(R-t)特征曲线进行了研究.研究发现采用固定电阻变化率作为失效判定标准所得的失效时间分布曲线不能真实地反映样品的实际寿命,而采用第一次阻值跳变点对应的时间作为失效时间所得的分布曲线则更符合电迁移理论.针对两种失效判定方法所得到的不同结果进行了机理分析,结果表明,采用第一次阻值跳变点对应的时间作为失效时间分析电迁移失效更合理.     

OFDM系统同步算法研究及其VLSI实现

针对正交频分复用（OFOM, Orthogonal Frequency Division Multiplex）无线传输系统,提出并设计了一种适用于802．11a标准前导序列的同步算法。首先基于接收基带数据能量判断信道空闲状态,再计算数据归一化自相关值检测帧起始位置,最后利用基带数据与参考训练序列的互相关运算检测OFDM符号的起始位置,实现同步功能。算法的硬件实现采用移位加和流水线技术来提高系统的性能与效率。实践表明,所提算法能有效地实现同步并且硬件实现复杂度低,适合于超大规模集成电路（VLSI,Very LargeScale Integration）的实现。