Power–Delay–Area–Noise Margin Tradeoffs in Positive-Feedback MOS Current-Mode Logic

In this paper, positive feedback source-coupled logic (PFSCL) gates are analyzed from a design point of view. The design space is explored through analytical relationships which relate the gate delay, power consumption and noise margin, which are modeled through a simplified circuit analysis. To be more specific, a simple and accurate model of the noise margin is used to derive a systematic design strategy to size the transistors' aspect ratios ensuring an assigned noise margin for a given bias current. From the knowledge of the transistor sizes, the gate delay is then expressed as a function of the bias current and the supply voltage, both of which define the static power consumption of PFSCL gates, as well as of the logic swing, which determines the noise margin. Therefore, this delay model simply relates the speed performance, the power consumption and the noise margin of PFSCL gates, and accounts for the dependence on the fan-in and fan-out. Extensive SPICE simulations with a 0.18-m CMOS process confirm the adequate accuracy of the analytical models and the validity of the approximations introduced to simplify the analysis, and a practical design example of an equality comparator is also presented. In order to derive clear guidelines to manage the delay-power-noise margin tradeoff, PFSCL gates are analyzed in typical design cases (i.e., design for high speed, low power and power efficiency). For the sake of completeness, the effect of each design parameter on the silicon area occupied by a PFSCL gate is also qualitatively analyzed. The resulting criteria are thus useful to design PFSCL gates without resorting to time-consuming design iterations with a trial and error approach based on simulations.     

Subterranean power lines in high-density integrated Josephsoncircuits

We found from simulations that wide power lines are required to make bias currents of Josephson gates uniform. Magnetic noise due to large power current decreases the critical current of the adjacent gate. To enhance circuit integration and to stabilize circuit operation, we proposed a power line laid under the ground plane. The gates can be located above the power line inserting the ground plane. The new power line can make whole chip areas active for gates however wide the line is. We confirmed that the ground plane shields the gates from magnetic noise. We fabricated some test circuits using the new power lines and confirmed their operations     

High-speed demonstration of a superconducting pseudo-randombit-sequence generator

This paper describes the design, analysis and test results for a 4-bit pseudo-random bit-sequence generator (PRBSG) implemented with complementary output switching logic (COSL) gates. The PRBSG was optimized using a Monte Carlo simulation method for 10-GHz operation. The circuit has been fabricated using niobium technology with critical current density of 1 kA/cm² and sheet resistance of 1 Ω/sq. The 4-bit PRBSG consists of 12 gates and its area is 1530×950 μm². It has been fully tested with a three-phase power supply, and its power consumption is 0.15 mW. The correct operations have been verified experimentally at clock frequencies of up to 2 GHz     

Simultaneous switching noise in on-chip CMOS power distribution networks

Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra large scale integration (VLSI/ULSI) circuits. An inductive model is used to characterize the power supply rails when a transient current is generated by simultaneously switching the on-chip registers and logic gates in a synchronous CMOS VLSI/ULSI circuit. An analytical expression characterizing the SSN voltage is presented here based on a lumped inductive-resistive-capacitive RLC model. The peak value of the SSN voltage based on this analytical expression is within 10% as compared to SPICE simulations. Design constraints at both the circuit and layout levels are also discussed based on minimizing the effects of the peak value of the SSN voltage.     

基于施密特触发的高鲁棒性亚阈值标准单元

亚阈值电路是低功耗重要发展方向之一。随着电源电压降低,晶圆代工厂提供的标准单元电路性能容易受噪声和工艺偏差的影响,已经成为制约亚阈值芯片的瓶颈。该文提出一种基于施密特触发(ST)与反向窄宽度效应(INWE)的亚阈值标准单元设计方案。该方案首先利用ST的迟滞效应与反馈机制,在电路堆叠结点处添加施密特反馈管以优化逻辑门、减少漏电流、增强鲁棒性;然后,采用INWE最小宽度尺寸与分指版图设计方法,提高电路的开关阈值与MOS管的驱动电流;最后,在TSMC 65 nm工艺下构建标准单元的物理库、逻辑库和时序库,完成测试验证。实验结果表明,所设计的亚阈值标准单元与文献相比,功耗降低7.2%～15.6%,噪声容限提升11.5%～15.3%,ISCAS测试电路的平均功耗降低15.8%。     

On circuit techniques to improve noise immunity of CMOS dynamic logic

Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation of VLSI chips designed using deep submicron process technology. In the literature, a number of design techniques have been proposed to enhance the noise tolerance of dynamic logic gates. An overview and classification of these techniques are first presented in this paper. Then, we introduce a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect. We have demonstrated through analysis and simulation that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained. Simulation results on large fan-in dynamic CMOS logic gates have shown that, at a supply voltage of 1.6 V, the input noise immunity level can be increased to 0.8 V for about 10% delay overhead and to 1.0 V for only about 20% delay overhead.     

Power supply noise in accurate delay model for the sub-threshold domain

Ultra-Low-Power circuits demand has dramatically increased in the last few years. One of the main challenges in designing these circuits is that transistors often run in the sub-threshold regime and their on current is exponentially dependent on the gate-to-source voltage, thus making sub-threshold gates extremely susceptible to power and ground noise phenomena. This paper provides a complete mathematical model in closed form for the delay of sub-threshold CMOS inverters. The novel model can predict the behavior of inverters output signal and therefore it can be extremely useful in the design phase to analyze the variations caused by noise on the output over/undershoot and the gate delay. The proposed model has a general validity since it considers the ground and supply noises completely uncorrelated both in frequency and in amplitude. When a commercial CMOS 45 nm process technology is referenced, the proposed model exhibits a maximum error of only ~16% under different conditions in terms of output load capacitance, input signal rising/falling time, noise phase and frequency.     

Simulation Based Framework for Accurately Estimating Dynamic Power-Supply Noise and Path Delay

Power-supply noise is one of the major contributing factor for yield loss in sub-micron designs. Excessive switching in test mode causes supply voltage to droop more than in functional mode leading to failures in delay tests that would not occur otherwise under normal operation. Thus, there exists a need to accurately estimate on-chip supply noise early in the design phase to meet power requirements in normal mode and during test to prevent overstimulation during the test cycle and avoid false failures. Simultaneous switching activity (SSA) of several logic components is one of the main sources of power-supply noise (PSN) which results in reduction of supply voltages at the power-supplies of the logic gates. Most existing techniques and tools predict static IR-drop, which accounts for only part of the total voltage drop on the power grid. To our knowledge, inductive drop is not included in current noise analysis for simplification. The power delivery networks in today’s very deep-submicron chips are susceptible to slight variations and cause sudden large current spikes leading to higher Ldi ? dt than resistive drop essentiating the need to account for this drop. Power-supply noise also impacts circuit operation incurring a significant increase in path delays. However, it is infeasible to carry out full-chip SPICE-level simulations on a design to validate the ATPG generated test patterns. Accurate and efficient techniques are required to quantify supply noise and its impact on path delays to ensure reliable operation in both mission mode and during test. We present a scalable current-based dynamic method to estimate both IR and Ldi / dt drop caused by simultaneous switching activity and use the technique to predict the increase in path delay. Our technique uses simulations of individual extracted paths in comparison to time-consuming full-chip simulations and thus it can be integrated with existing ATPG tools. The method uses these path simulations and a convolution-based technique to estimate power-supply noise and path delays. Simulation results for combinational and sequential benchmark circuits are presented demonstrating the effectiveness of our techniques.     

Stacked PMOS clamps for high voltage power supply protection

Large p-channel MOS (PMOS) field-effect transistors (FETs) with multiple gates can be arranged to provide ESD protection to high voltage on-chip power supplies in submicron integrated circuits. These clamps divide the supply voltage among several gate oxides; the circuitry accompanying the large series FETs provides near-maximum gate drive during the ESD for high pulsed current. Layouts are densely packed because minimum dimensions can be used and because no contact is needed between the stacked gates. The designs for high voltage are extensions of the large PMOS FET ESD clamps and timed drive circuitry that are used to clamp ordinary on-chip power supply lines.     

Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

Usage of dual supply voltages in a digital circuit is an effective way of reducing the dynamic power consumption due to the quadratic relation of supply voltage to dynamic power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design. The overhead of level shifters forces designers to increase the granularity of dual voltage assignment, reducing the maximum obtainable savings. We propose a method of incorporating voltage level conversion into regular CMOS gates by using a second threshold voltage. Proposed level shifter design makes it possible to apply dual supply voltages at gate level granularity with much less overhead compared to traditional level shifters. We modify the threshold voltage of the high voltage gates that are driven by low voltage gates in order to obtain the level shifting operation together with the logic operation. Using our method, we obtained an average of 20% energy savings for ISCAS'85 benchmark circuits designed using 180-nm technology and 17% when 70-nm technology is used.     

Current-mode digital circuits operating in mixed analogue-digitalsystems

Novel current-mode gates are presented. The current-mode circuits operate with an almost constant current drawn from the power supply, significantly reducing interference with other circuits located on the same silicon die     

基于DSP技术的等离子切割机电源系统的研究

该设计应用DSP技术对等离子切割电源系统的功率因数进行校正,减小了谐波对电网的干扰,提高了电源输出的稳定性。该系统的各级控制环节采用德州仪器生产的DSP芯片TMS320F2812数字信号处理器进行处理,建立等离子切割电源功率因数的数字化控制系统。该系统应用电流传感器检测boost模块的输入电流,通过采样与A/D变换和PID控制实现稳定的恒电流输出,从而有效地提高了电源系统的功率因数和工作稳定性,增强了系统的抗高频干扰能力。     

Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doubler

Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doublers based on cross-coupled structure are presented. The intuitive analysis of the shoot-through current and switching noise generation processes in the doubler is first reported. Break-before-make mechanism is adopted to minimize the shoot-through current, thereby greatly reducing the no-load supply current dissipation and improving the light-load power efficiency of the voltage doubler. In addition, by employing gate-slope reduction technique at the serial power transistor during turn-on, the switching noise of the voltage doubler is significantly lowered. Two voltage doublers with and without the proposed circuit techniques have been fabricated in a 0.6-/spl mu/m CMOS process. Experimental results verify that the total supply current at no-load condition of the proposed voltage doubler is reduced by two fold and its switching noise is decreased by 2.5 times.     

A high-efficiency,low-noise power solution for a dual-channel GNSS RF receiver

A high-efficiency low-noise power solution for a dual-channel GNSS RF receiver is presented.The power solution involves a DC-DC buck converter and a followed low-dropout regulator(LDO).The pulsewidth -modulation(PWM) control method is adopted for better noise performance.An improved low-power highfrequency PWM control circuit is proposed,which halves the average quiescent current of the buck converter to 80μA by periodically shutting down the OTA.The size of the output stage has also been optimized to achieve high efficiency under a light load condition.In addition,a novel soft-start circuit based on a current limiter has been implemented to avoid inrush current.Fabricated with commercial 180-nm CMOS technology,the DC-DC converter achieves a peak efficiency of 93.1%under a 2 MHz working frequency.The whole receiver consumes only 20.2 mA from a 3.3 V power supply and has a noise figure of 2.5 dB.     

面向电源噪声的动态电流测试

电源噪声在深亚微米设计中正变得越来越突出，而因电源噪声引起的电路故障测试也变得越来越重要。本文针对这一情况提出了动态电流测试来实现由电源噪声引起的故障测试。与IddQ测试不同，动态电流测试依据电路中的器件切换时电源电流的动态变化情况来判断电路中是否存在故障。通过仿真分析，动态电流测试是可行的。     

MOS varactors with n- and p-type gates and their influence on an LC-VCO in digital CMOS

The influence of the gate doping type of the MOS varactor on frequency tuning, phase noise, and frequency sensitivity to supply-voltage variations of a fully integrated inductance-capacitance voltage-controlled oscillator (LC-VCO) is presented. Three varactors in multifinger layout with shallow trench isolation (STI) are compared. The polysilicon gate is either entirely n- or p-doped or the fingers have alternating n and p doping. Differences in capacitance and quality factor are shown. Two identical VCOs with the varactors having n gates or np gates are realized. Homogenous doping increases the VCO tuning range to 1.31 GHz (/spl plusmn/20%) in comparison to 1.06 GHz (/spl plusmn/15%) obtained by mixed doping. However, mixed doping has the advantages of more linear VCO frequency tuning, lower close-in phase noise, and reduced maximum sensitivity to variations in supply voltage. Several varactor parameters are introduced. They allow prediction of the influence of varactors on the performance of a given VCO. With a current consumption of only 1 mA from a supply voltage of 1.5 V, both VCOs show a phase noise of -115 dBc/Hz at 1-MHz offset from a 4-GHz carrier and a VCO figure of merit of -185.3 dBc/Hz.     

Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint

We propose a multiple supply voltage scaling algorithm for low power designs. The algorithm combines a greedy approach and an iterative improvement optimization approach. In phase I, it simultaneously scales down as many gates as possible to lower supply voltages. In phase II, a multiple way partitioning algorithm is applied to further refine the supply voltage assignment of gates to reduce the total power consumption. During both phases, the timing correctness of the circuit is maintained. Level converters (LCs) are adjusted correctly according to the local connectivity of the different supply voltage driven gates. Experimental results show that the proposed algorithm can effectively convert the unused slack of gates into power savings. We use two of the ISPD2001 benchmarks and all of the ISCAS89 benchmarks as test cases. The 0.13-mum CMOS TSMC library is used. On average, the proposed algorithm improves the power consumption of the original design by 42.5% with a 10.6% overhead in the number of LCs. Our study shows that the key factor in achieving power saving is including the most comfortable supply voltage in the scaling process.     

一种用于半桥功率IC的新型高压电平位移电路

In order to reduce the chip area and improve the reliability of HVICs,a new high-voltage level-shifting circuit with an integrated low-voltage power supply,two PMOS active resistors and a current mirror is proposed.The integrated low-voltage power supply not only provides energy for the level-shifting circuit and the logic circuit,but also provides voltage signals for the gates and sources of the PMOS active resistors to ensure that they are normally-on.The normally-on PMOS transistors do not,therefore,need to be fabricated in the depletion process.The current mirror ensures that the level-shifting circuit has a constant current,which can reduce the process error of the high-voltage devices of the circuit.Moreover,an improved RS trigger is also proposed to improve the reliability of the circuit.The proposed level-shifting circuit is analyzed and confirmed by simulation with MEDICI,and the simulation results show that the function is achieved well.     

AM and FM Noise of BARITT Oscillators

AM, FM, and baseband noise of a BARITT diode oscillator in the range 100 Hz-50 kHz off the carrier has been measured under various operating conditions. A simple calculation has been made, relating the baseband noise to the oscillator AM and FM noise via measured amplitude and frequency modulation sensitivities and the results have been compared with the noise measured. It is shown that, depending on the bias current applied, both AM and FM noise performance can be degraded by up-conversion. Complete removal of up-converted noise requires a high-impedance low-noise bias supply since both the diode noise and bias supply noise at baseband frequencies may be significant when up-converted. Even with all modulation suppressed, the AM and FM noise has a flicker component almost completely correlated with the diode flicker noise at baseband frequencies. The RF power dependence of the AM and FM noise has also been investigated. It is shown that the BARITT oscillator noise compares very favorably with that of IMPATT's and TEO's. Values of -142 dB/100 Hz (AM noise) and 3.5 Hz/(100 Hz)/sup 1/2/ for Q/sub ext/ = 200 (FM noise) have been measured at 30 kHz off the carrier.     

Dual-threshold voltage assignment with transistor sizing for lowpower CMOS circuits

We demonstrate a novel algorithm for assigning the threshold voltage to the gates in a digital random logic complementary metal-oxide-semiconductor (CMOS) circuit for a dual-threshold voltage process. The tradeoff between static and dynamic power consumption has been explored. When used along with device sizing and supply voltage reduction techniques for low power, the proposed algorithm can reduce the total power dissipation of a circuit by as much as 50%