C-V characteristics of metal-titanium dioxide-silicon capacitors

Titanium dioxide capacitors were fabricated on silicon wafers using electron-beam evaporation. The TiO₂ films varied in thickness from 500 to 2000 Å. Post-deposition oxidation at 1000°C in dry O₂ was used to promote stoichiometric conversion of the films to the rutile phase. Capacitive densities of greater than 2 pf/sq. mil were obtained (dielectric constants ranged from 4 to 40). For long oxidation times, significant silicon dioxide grows under the TiO₂ as a result of oxygen diffusing through the TiO₂ film. Titanium was also shown to diffuse into the silicon during the oxidation cycle resulting in an n-type diffusion. Surface state densities ranging from 10¹¹ to 5 × 10¹¹ cm^?2 eV^?1 at midgap were obtained for good devices. Longer oxidation times result in lower capacitance, leakage current and surface state density.     

Theoretical analysis of kink effect in C-V characteristics ofIndium-implanted NMOS capacitors

Experimental observation of an anomalous “kink” effect in C-V characteristics of Indium-doped NMOS capacitors is reported and explained, for the first time, via the impact of incomplete ionization of Indium. A new analytical formulation of the total semiconductor capacitance is developed, that takes incomplete ionization phenomenon into account. Thanks to this new C_SC(φ_s) relation, we have demonstrated that the carrier freeze-out is responsible for this kink near V_FB in C-V curves, and also for an intrinsic lowering in the threshold voltage. This kink has been shown to be very sensitive to Indium dose and temperature. It is also demonstrated that the deformation of the C-V characteristics due to Indium incomplete ionization may be (and probably has often been) miss-interpreted as appearance of high fixed charge densities in parameter extraction from C-V fitting. Our analysis is in full agreement with experimental results     

Numerical solution of Poisson's equation with application to C-V analysis of III-V heterojunction capacitors

The numerical solution to Poisson's equation under quasi-equilibrium conditions, using a formulation that includes carrier degeneracy, multiple conduction band minima, nonparabolicity of the Γ valley, and dopant deianization, is discussed. Moment theorems are shown to provide stringent tests for the accuracy of numerically simulated capacitance versus voltage characteristics. The numerical model is also used to quantify errors in a widely used technique for extracting band discontinuities byC-Vanalysis.     

Electrical behavior of decoupling capacitors embedded inmultilayered PCBs

We describe the modeling of prototype capacitors embedded in multilayered printed circuit boards. We present the design of these devices. We also report measurement and characterization results. The emphasis is on the modeling of via hole connections to the embedded capacitor, not on the technology of buried capacitors. Several designs have been compared with respect to their electrical behavior. In particular, several via hole configurations have been studied, because they are the main cause of parasitic behavior. With these buried capacitors, we obtained a reduction of the parasitic inductance of 80% compared to an equivalent discrete capacitor. This work has been carried out under a European Brite-EuRAM funded project COMPRISE (BE 96-3371). The objective of this project was to develop new materials and manufacturing processes to embed passive components (R, L, and C) within printed wiring structures fabricated from laminate materials. This technology enables the manufacture of space efficient and radio frequency (RF) optimal performing types of modules or board assemblies particularly suited to the market domain of portable and handheld communication and information technology products     

Modeling of high-frequency characteristics for epoxy-sealed micro vacuum capacitors

The high-frequency loss tangent of micro vacuum dielectric capacitors (VDCs) is modeled based on the experimental results using equivalent circuit approach. We found that the dielectric loss of the capacitor at high frequency mainly arises from the dielectric loss of the periphery sealant for the capacitors. Meanwhile, the resonant frequency of the VDCs also depends on that of the sealant. However, within the constraint of sealant material, the characteristics of the VDC can still be optimized by properly choosing the geometric factors. Smaller value of the width of boundary sealant layer to the capacitor side length ratio will result in a smaller value of loss tangent.     

Modeling and optimization of series resistance of planar MIM capacitors

Integrated circuits for analog and telecom applications require metal insulator metal (MIM) capacitors with not only a high capacitance value (typically 5 nF/mm²), but also a low series resistance R_s. The optimization of this latter parameter is investigated in this paper, by means of a simple analytical model, taking into account both the impact of material parameters and device architectures, suggesting possible strategies for R_s minimization. Such a model is also suitable for MIM circuit simulation, and can be also extended to other devices, such as to the gate series resistance modeling of RF MOSFET. Results are in good agreement with numerical simulations and HF measurements, performed on state of the art planar MIM devices. Moreover, discussion on via placement to access the top electrode has been held, in order to optimize the series resistance of the capacitor.     

Mode optimization of retrograde pocket doping in SOI-MOS VLSI transistors

A two-stage optimization technique for the parameters of SOI-MOS structures is proposed based on the correction of the pocket formation modes of an active structure. As a result of the use of this technique, the threshold voltage of the bottom (parasitic) transistor doubles, while maintaining the values of the parameters of the upper (main) transistor. The experimental investigations confirmed the effectiveness of using this optimization technique when doping the pockets of a SOI-MOS structure to provide the radiation hardness to the accumulated dose.     

Modeling and simulation of integrated capacitors for high frequencychip power decoupling

Power and ground decoupling is typically accomplished using a hierarchy of discrete capacitors spread throughout the power distribution network. Many of the limitations of discrete decoupling capacitors can be overcome with integrated capacitors. A modeling approach for integrated capacitors based on the partial-element-equivalent-circuit (PEEC) formulation is presented. This approach has been applied to 3M C-ply, a flexible planar integrated capacitor technology that can be laminated into multilayer substrates, such as printed wiring boards. The decoupling capability of 3M C-Ply technology for chip power distribution has been compared with conventional surface-mount technology (SMT)     

The Use of Finite Element Modeling for Calculating the C-V Curve of Capacitor Mems Microphone

The C-V curve is an important characteristic of a MEMS microphone as it determines its operating voltage and sensitivity. Due to the complicated geometry of its fixed perforated backplate and thin movable diaphragm, it requires finite element modeling to calculate the C-V curve. Various methods to solve this problem are considered in this work, and implementation of the iterative calculation method using the ANSYS software package is proposed. The results obtained using the iterative method and the two calculating methods of electrostatic interaction built into the ANSYS software are compared and analyzed.     

多信道传播模型下C-V2X模式4通信建模与性能分析

C-V2X或LTE-V作为车联网(Vehicular Communication Networks, VCN)领域的新兴通信技术,能够有效提高道路安全和交通通信效率。在3GPP发布的R14标准中,引入不依赖于任何蜂窝基础设施的直连通信模式4,在模式4中车辆自主选择和管理其无线电资源。在不结合实际的交通场景的情况下对C-V2X模式4通信性能进行评估,提出了一种多信道传播模型下C-V2X模式4通信性能分析模型,验证了不同传输参数以及不同信号传播信道对性能的影响,试图设计更为完备的分析模型,探索参数的影响并调整参数来进一步提升C-V2X模式4通信性能的可能性。     

Determination of generation lifetime from the small-signal transient behavior of MOS capacitors

The theory and an experimental proof of a method for determining generation-lifetime in silicon with impurity concentrations up to 10¹⁸ cm^?3 are described. Generation-lifetime is obtained by analyzing the transient behavior of the total charge stored in a MOS-capacitor after a very small depleting voltage step. The analytical expression allowing this analysis is deduced from the Shockley-Read-Hall-expression of the carrier generation rate by considering small deviations from thermal equilibrium. The small signal expression thus obtained differs in a constant factor only from the well known large signal expression. A comparison of this small-signal method with well known large signal methods practiced on samples with doping levels of 10¹⁵ cm^?3 shows that the results are in very good agreement.     

MFIS结构的C-V特性

研究了运用SOL-GEL方法制备的Au/PZT(铅锆钛)/ZrO2/Si结构电容即MFIS(Metal/Ferroelectr c/Irsulator/Semiconductor)电容的方法,并对其进行了SEM、C-V特性测试及ZrO2介质层介电常数分析.研究了C-V存储窗口(Memory WindoW)电压与铁电薄膜和介质层厚度比的关系,得出MFIS电容结构中最佳铁电薄膜和介质层厚度比为7 10左右,在外加电压5V-+5V时存储窗口可达2.52V左右.     

MFIS结构的C-V特性

研究了运用SOL-GEL方法制备的Au/PZT(铅锆钛)/ZrO2/Si结构电容即 MFIS(Metal/Ferroelectric /Insulator/Semiconductor)电容的方法,并对其进行了SEM、C- V特性测试及ZrO2介质层介电常数分析 .研究了C-V存储窗口(Memory Window)电压与铁电薄膜和介质层厚度比的关系,得出MFIS电容结构中最佳铁电薄膜和介质层厚度比为7～10左右 ,在外加电压-5V～+5V时存储窗口可达2.52 V左右 .     

Modeling of ESR in metallized film capacitors and its implication on pulse handling capability

Metallized film capacitors (MFC) are widely used in pulsed power systems and power electronics applications. The pulse handling capability of MFC is one of important performances and drastically depends on the quality of contact states between the spray and metallization. The equivalent series resistance (ESR) is a significant parameter to the capacitor. This paper presents a model to calculate ESR with consideration of the end contact status. This model shows that ESR at low frequency (∼100 Hz) is more efficient to reflect the end contact status than that at high frequencies (∼10 kHz). Lifetime experiments are designed to demonstrate that MFC with significantly lower ESR enjoy longer pulse lifetime and better pulse handling capability. Thus measured at low frequency (∼100 Hz) can be regarded as a parameter to reflect the disconnections of weak contact in high current densities applications and to evaluate the pulse handling capability.     

C-V profiling of GaAs FET films

The depletion layer capacitance of a Schottky barrier on a GaAs FET film can only be measured in series with the resistance of the undepleted portion of the film. This inherent series resistance may be significant at all values of bias and causes large errors inC-Vprofile determinations. By treating the depletion layer capacitance and the series resistance as a distributedRCtransmission line, it is possible to define an effective series resistance which can be related directly to the resistivity of the film. Using parameters typical of epitaxial films grown for GaAs FET applications, general criteria are developed for the profilability of these films. It is shown that, in general, films with small pinchoff voltages (i.e., films intended for low-noise FET applications)     

C-V profiling of steep dopant distributions

An exact expression for the incremental capacitance of a partially depleted n-channel with steep dopant gradient is given in terms of the position dependence of the peak electron concentration when the gate bias voltage is changed. The C-V concentration profile derived from this expression differs from the actual dopant profile in two respects: (i) The peak of the C-V profile for a heavily doped implant is about twice the peak dopant concentration, and lies somewhat closer to the depleting contact. This discrepancy arises from the gradual decay of the electron distribution into the depletion layer. (ii) The tail of the C-V profile extends far beyond the dopant profile. This discrepancy arises from the variation with applied voltage of the built-in potential between the position of peak electron concentration in the partially depleted channel and the bulk of the substrate. A procedure is given to reconstruct the actual dopant distribution from the tail of the C-V profile, a task for which the Kennedy method is found to be inadequate.     

Modeling of thermal behavior in SOI structures

Several physics-based analytical steady-state heat flow models for silicon-on-insulator (SOI) devices are presented, offering approaches at different levels of accuracy and efficiency for prediction of temperature profiles induced by power dissipated in SOI MOSFETs. The approaches are verified with the rigorous device simulation based on the energy transport model coupled with the heat flow equation. The models describe the one-dimensional temperature profile in the silicon film of SOI structure and two-dimensional heat flow in FOX, accounting for heat loss to the substrate via BOX and FOX, heat loss to (or gain from) interconnects, and heat exchanges between devices. These models are applied to investigate thermal behavior in single SOI devices and two-device SOI structures.     

a—Si：H／c—Si异质结的高频C—V特性

测量了GD a-Si:H/n-c-Si异质结的高频C-V特性,由平带电压的偏移,计算了有效表面电荷和表面态密度,应用突变异质结能带模型对结果作了分析.     

平面栅条状Schottky结容压特性

<正> 人们在研究微波单片集成电路时,提出了平面栅条状Schottky结变容管。本文根据“椭圆柱面结耗尽层分析”结果,分析了平面栅条状Schottky结电容与偏压的关系。 平面栅条状Schottky结变容管示意于图1,图中电极A(长为l_a,宽为W)是Schottky势垒金属,电极B(长为l_b)与n-GaAs间呈欧姆接触,电极A、B间距为l_(ab)。显然,这种“栅状”变容管的制作与GaAs MESFET器件工艺类似。 如图1(b)所示,在电极A上外加一偏压V_A(负值)后,电极A下n-GaAs中即出现相应的耗尽层,假设完全耗尽,在椭圆坐标中(图2),外加偏压与耗尽层的关系可表示为     

有机薄膜电容器替代电解电容器应用分析

分析了有机薄膜电容器的结构特点及发展趋势,并通过典型电路中的电容器应用实例结合电容器的应用性能参数对比分析,总结得出了有机薄膜电容器替代电解电容器的优势。在电源旁路、滤波、电源开关等对耐纹波电流能力、损耗和电容量稳定性要求较高的电路中,有机薄膜电容器可替代钽电解电容器。