A Network Time Interface M-Module for Distributing GPS-Time over LANs

This paper provides a comprehensive overview of our Network Time Interface (NTI) M-Module, which facilitates high-accuracy time distribution in LAN-based distributed real-time systems. Built around our custom UTCSU VLSI chip, it hosts all the hardware support required for interval-based external clock synchronization: A high-resolution state- and rate-adjustable clock, local accuracy intervals, interfaces to GPS receivers, and various timestamping features. Maximum network controller and CPU independence ensures that the available NTI prototype can be employed in virtually any COTS-based system with MA-Module interface. Our experimental evaluation shows that time distribution with s-accuracy is possible even in Ethernet-based system architectures, provided that the available configuration parameters are suitably chosen to cope with the various hidden sources of timing uncertainty.     

FLOPSYNC-QACS: Quantization-aware clock synchronization for wireless sensor networks

Distributed real-time systems often rely on clock synchronization. However, the achievement of precise synchronization in Wireless Sensor Networks (WSNs) is hampered by competing design challenges, which finally causes many WSN hardware platforms to rely on low frequency clock crystal for local timebase provision. Although this solution is inexpensive and with a remarkably low energy consumption, it limits the resolution at which time can be measured. The FLOPSYNC synchronization scheme was then introduced to compensate for possible quartz crystal imperfections. The main limitation of FLOPSYNC is that it does not account for the effects of quantization. In this paper we propose a switched control variant of the base FLOPSYNC scheme to address quantization explicitly in the compensator design, providing clock synchronization in cost-sensitive WSN node platforms with a minimal additional overhead. Experimental evidence is given that the approach reaches a synchronization error of at most 1 clock tick in a real WSN.     

矿用分布式采集系统时钟同步方案设计与实现

单一的时钟同步技术由于其精度及应用局限性,无法满足矿用分布式采集系统高精度、高可靠性的时钟同步性能要求。针对上述问题,提出了基于北斗+IEEE 1588V2+本地后备时钟的三级协同时钟同步方案。选用部署在地面的T600-BDGOCXC型北斗授时服务器作为主时钟,为系统提供纳秒级精度的绝对时钟;采用STM32F407+DP83848及PTPd协议栈实现支持IEEE 1588V2协议的采集节点,通过井下工业环网将北斗的绝对时钟同步到各采集节点;本地后备时钟采用STM32F407内部RTC(实时时钟)实现,给各采集节点提供秒级精度的时间戳初值,便于各采集节点用最短时间实现与主时钟的同步。测试结果表明,北斗授时服务器与采集节点通过交换机直连的情况下,1 min后时钟同步精度达162 ns;北斗授时服务器与采集节点通过三级交换机连接的情况下,时钟同步精度为565 ns;在北斗授时服务器失效的情况下,优先级高的采集节点升级为主时钟并为其余采集节点授时,具有较强的可靠性。     

基于SNTP同步模型的时钟同步系统

使用ORBUS作为开发平台,以CORBA时间服务的已有同步模型作为开发基础,试图在局域网内实现时钟同步系统.在分析影响同步精度和系统性能因素的基础上,设计并实现了SNTP同步模型.在局域网环境中的系统测试表明,时钟同步系统可将同步时间误差范围由原来的5毫秒缩短至1毫秒以内,达到了系统的预期设计要求.     

一种全数字锁相环的设计与应用

介绍一种采用FPGA设计实现的ADPLL的结构及特点,并用该锁相环产生SDH设备的外同步时钟。由于该锁相环的负反馈时钟采用了初始受控分频设计、并采用了合理的环路滤波算法,该ADPLL同传统的数字锁相环(DPLL)一样,在参考源切换过程中输出时钟平滑稳定;同时也和传统的模拟锁相环(APLL)一样,在锁定状态下有稳态相差。对输出时钟的测试表明,该ADPLL产生的SDH外同步输出时钟满足系统的应用要求。     

基于本地时钟自校正的无线传感器网络同步方法

通过分析TPSN同步协议和造成时钟偏差不确定性的各种因素,结合无线传感器网络低功耗的特点及其对时钟同步算法精度的要求,针对TPSN未对时钟频率漂移进行估计的问题,提出一种节点本地时钟自校正方法,并设计了平均时钟偏差指标对一个同步周期内时钟精度进行评价。对比实验结果表明本方法易于实现,在保证同步精度的同时可以延长同步周期,减少同步开销,节约了能耗。     

民航西南地区传输网时钟同步系统设计与探讨

时钟同步网作为当前异地时钟同步实现的主要方式,在当前民航西南地区有着广阔的应用前景。介绍了民航西南地区传输网的技术现状及时钟同步面临的问题,阐述了利用现有的传输设备来实现构建西南地区传输同步时钟网的设计。     

Fault-tolerant cluster-wise clock synchronization for wireless sensor networks

Wireless sensor networks have received a lot of attention recently due to their wide applications, such as target tracking, environment monitoring, and scientific exploration in dangerous environments. It is usually necessary to have a cluster of sensor nodes share a common view of a local clock time, so that all these nodes can coordinate in some important applications, such as time slotted MAC protocols, power-saving protocols with sleep/listen modes, etc. However, all the clock synchronization techniques proposed for sensor networks assume benign environments; they cannot survive malicious attacks in hostile environments. Fault-tolerant clock synchronization techniques are potential candidates to address this problem. However, existing approaches are all resource consuming and suffer from message collisions in most of cases. This paper presents a novel fault-tolerant clock synchronization scheme for clusters of nodes in sensor networks, where the nodes in each cluster can communicate through broadcast. The proposed scheme guarantees an upper bound of clock difference between any nonfaulty nodes in a cluster, provided that the malicious nodes are no more than one third of the cluster. Unlike the traditional fault-tolerant clock synchronization approaches, the proposed technique does not introduce collisions between synchronization messages, nor does it require costly digital signatures.     

Scalable Clock Synchronization Analysis: A Symmetric Noncooperative Output Feedback Tubes-MPC Approach

In the cyber-physical environment, the clock synchronization algorithm is required to have better expansion for network scale. In this paper, a new measurement model of observability under the equivalent transformation of minimum mean square error (MMSE) is constructed based on basic measurement unit (BMU), which can realize the scaled expansion of MMSE measurement. Based on the state updating equation of absolute clock and the decoupled measurement model of MMSE-like equivalence, which is proposed to calculate the positive definite invariant set by using the theoretical-practical Luenberger observer as the synthetical observer, the local noncooperative optimal control problem is built, and the clock synchronization system driven by the ideal state of local clock can reach the exponential convergence for synchronization performance. Different from the problem of general linear system regulators, the state estimation error and state control error are analyzed in the established affine system based on the set-theory-in-control to achieve the quantification of state deviation caused by noise interference. Based on the BMU for isomorphic state map, the synchronization performance of clock states between multiple sets of representative nodes is evaluated, and the scale of evaluated system can be still expanded. After the synchronization is completed, the state of perturbation system remains in the maximum range of measurement accuracy, and the state of nominal system can be stabilized at the ideal state for local clock and realizes the exponential convergence of the clock synchronization system.      

基于时钟同步技术在数据采集系统中的应用

介绍了一种系统时钟信号同步设计。为了提高系统时钟同步技术以及系统的可靠性,以现场可编程阵列（FPGA）代替传统的处理器为控制核心,采用锁相环（PLL）和Verilog硬件描述语言进行设计,达到复位实现时钟同步目的。实践证明,该设计运行稳定,可靠性强,适合在高速工作时钟下工作。     

EtherCAT分布时钟机制在数控系统中的研究与应用

为了提升数控系统的同步性能,提出了将EtherCAT分布时钟机制引入到数控系统的解决方案。首先重点研究了EtherCAT分布时钟的系统时间和从站本地应用的同步机制;接着详细阐述了分布时钟机制在数控系统中的实现过程;最后搭建了EtherCAT分布时钟同步性能测试平台,经测试主站时钟、参考时钟和从时钟均达到了纳秒级的同步。     

GPS-based Clock Synchronization in a Mobile,Distributed Real-Time System

In a vehicle tracking system computers aboard moving vehicles determine periodically their geographical position and transmit it to a control center. This paper presents a commercial vehicle tracking system as an example of a distributed real-time system with mobile components and focuses on the issue of clock synchronization. The mobile components of the system obtain highly accurate timing information from the Global Positioning System which is used to synchronize their local clocks to UTC world time. Thus a tight clock synchronization is achieved without imposing additional load on the communication channels of the system.     

电网卫星驯服时钟的网络时间同步服务器设计

在分析网络时间同步协议的基础上,设计了一种ARM＋FPGA的网络时间同步服务器。研究了用卫星驯服时钟的方法解决了网络时间服务器中时钟源精度不高,易受干扰的特点,采用了PI调节器的时钟驯服模型。通过实验测试,该服务器可满足对电力系统二次设备的同步授时。     

面向安全关键嵌入式系统的时钟同步设计

为了满足安全关键性实时嵌入式系统对实时行为正确性和确定性的要求,本文应用ETSEC网络控制器的硬件时间戳特性, ReWorks嵌入式实时操作系统的实时特性,结合IEEE 1588精密度时钟同步协议,设计并实现了一个面向安全关键性领域的时钟同步系统原型.其同步精度达到100纳秒以内,并通过软件插桩测试和验证了该时钟同步系统的正确性和精度.     

低开销的星型结构无线传感器网络同步技术

通过分析TPSN同步协议和星型网络结构的特征,针对无线传感器网络低功耗的特点及其对时钟同步算法精度的要求,提出了一种广播式TPSN同步协议和节点本地时钟自校正相结合的方法.实验结果表明,本方法在保证同步精度的同时可以延长同步周期,大幅减少网络同步分组数量,显著降低了同步开销,节约了能耗.     

EPA最佳主时钟的控制算法研究

为满足EPA网络时间同步的高精度要求，建立了一种二维模糊控制器来确定设备自身时钟的优劣层次，系统采用公平竞争的方法从众多现场设备中快速、准确地决策一个时钟性能最好的设备作为EPA系统的最佳主时钟，保证了系统运行的稳定性，降低了本地时钟的波动，使现场设备的时钟同步精度提高到50μs。     

仿真系统中的时钟同步算法

研究当前仿真系统中的时钟同步问题和网络时间协议（NTP）。在NTP的基础上通过引入“主从服务器”模式、客户端时间推进和事件注册机制,实现一种适用于分布式仿真系统的、具有较高精度的软件时钟同步算法,给出同步系统的设计和实验方案。根据对实验数据的分析,验证该算法是一种简单有效的高精度时钟同步算法。     

基于概率同步算法的计算机外时钟同步系统设计与仿真

在计算机软件时钟同步系统中，网络延迟的测量与建模、同步算法的设计及算法性能的评估是要解决的三个主要问题。该文研究了基于概率同步算法的计算机外时钟同步系统设计。首先研究了基于PC高分辨计数器接口的网络延迟精确测量方法，对几种典型网络环境进行了测量，建立了网络延迟的对数正态分布统计模型。然后推导了网络延迟为对数正态分布模型下的同步包数目的计算公式，研究了基于该公式的概率同步算法参数设计。最后，对单个从节点情况下改进的概率同步算法的性能进行了仿真检验。结果表明，基于网络延迟的对数正态模型的推导和设计是正确、可靠的。改进的概率同步算法具有较高的同步效率和同步精度，可以用于实际的仿真系统。     

基于TSDPLL的时钟漂移补偿算法容错研究*

提出集成TSDPLL对系统节点本地时钟计时频率漂移进行有效补偿的时钟同步方法,大大提高了应用网络时间同步技术（如NTP、PTP等）的同步精度。为确保TSDPLL能在网络出现拥塞的情况下仍然正常工作,通过分析收敛函数基本特征,提出基于收敛函数的容错方案。仿真实验结果表明,该方案算法简单、容错效果明显,是基于DPLL时钟漂移补偿算法不可或缺的关键组成部分。     

基于拟合偏差的时钟同步

该文提出采用拟合偏差方法进行时钟调整的策略,以有效克服网络延迟和抖动对时钟同步的影响。开发NTP时间同步客户端,实现多种时间戳数据的采集和存储。分析本地节点的时间信息和来自于参考时钟服务器的时间戳信息,并构造时钟偏差趋势方程。利用线性拟合方法建立时钟漂移率数学模型和利用该漂移率进行时钟的调整和稳定性分析。实验证明,该策略提高了客户端时钟同步的稳定性和安全性,能够更好地适应网络传输性能较差环境下的时钟同步。