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1.
A Hewlett Packard desktop computer has been connected through a Data Ready Flag with NIM ADCs to produce a data acquisition system which can be used for cosmic ray telescope detector applications. The system has been tested with a two detector telescope irradiated with beams of 20Ne ions accelerated to 230 and 376 MeV.  相似文献   

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All CDF event data are collected in a multilevel FASTBUS network. At the lowest level of this network, MEP/MX and SSP scanners read and buffer data from RABBIT and FASTBUS front end systems. Operation of these front end scanners is coordinated by the Trigger Supervisor module which initiates parallel readout after receiving Level 1 and Level 2 triggers. Dataflow from scanners to consumer processes on host VAX computers is supervised by the Buffer Manager which directs an Event Builder to collect and format data from a set of scanner modules. This system is designed to allow partitioning into semi-independent sections for parallel development and calibration studies.  相似文献   

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T. Kimber 《Strain》1989,25(2):61-62
A method of simple modular data acquisition is described. The approach is currently used by engineers for a wide variety of applications. It is particularly useful for engineers who have a limited knowledge of computer programming.  相似文献   

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The data acquisition system for the SLD detector will make extensive use of parallel processing at the front-end level. Fastbus acquisition modules are being built with powerful processing capabilities for calibration, data reduction and further preprocessing of the large amount of analog data handled by each module. This paper describes the readout electronics chain and data preprocessing system adapted for most of the detector channels, exemplified by the central drift chamber waveform digitization and processing system.  相似文献   

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Towards an ideal data acquisition channel   总被引:1,自引:0,他引:1  
A method is presented for compensating in real time for a nonideal transfer function of a data acquisition channel by means of a digital IIR (infinite impulse response) filter. Real-time compensation of the amplitude and phase characteristics of an acquisition channel so that the long-term error is less than ±0.01 dB and ±0.1°, respectively, has been obtained experimentally. It is shown that stability and linearity are the main requirements for the components of the data acquisition channel. Careful selection of the components and outlining of the antialias filter and the programmable amplifier is no longer necessary  相似文献   

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A fast intelligent multiprocessor data acquisition system is described here. The system based on the MC68010 using the VME bus can acquire data via the CAMAC dataway at transfer rates up to 800 Kbytes/s. The system has a user friendly interface which builds the required assembly code needing only the CAMAC FNAs used in the experiment. In addition the system can be easily modified using the standard MC68010 assembly language to handle most preprocessing requirements. The system design will also allow for future expansion to the 32 bit word and faster instruction time of the MC68020. This expansion will allow for transfer rates well over a Mbyte/s.  相似文献   

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A single board auxiliarycamac crate controller for a Z80-A based personal computer ZX-spectrum to drive thecamac crate housing multipleadc, tdc, dac and 16 I/O ports has been developed. Thecamac crate controller used in this system is of A2 type which supports multiple auxiliary crate controllers. Acamac exerciser/training software for the use ofcamac commands in process control as well as data acquisition has been developed.  相似文献   

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A system is presented with which a computer can be used to provide electronic feedback nulling of a Wheatstone bridge measurement system used for data acquisition. This system provides compensation for drifts away from null resulting from the measurement setup or amplifier drifts with time or temperature. An example of the system in the case of a strain gauge bridge used with a cantilever beam is described  相似文献   

12.
A modular extendable acquisition system for coincidence data is developed, which uses commercially available high-stability high-precision ADCs. The basic functions in the system are incorporated each in a specific type of module, which offers maximum flexibility. The user can define the relevant types of coincidences by making the connections between the different modules. Many tools are provided that make it easy to set up and to monitor the system. Data latching, a fast clear, and the possibility of pileup rejection are implemented. Extension possibilities, included in the concept, are discussed. The maximum throughput of the system is such that the conversion-time of the ADCs and the maximum data-rate of a magnetic-tape unit are the limiting factors.  相似文献   

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针对目前大多数采集系统无法实现多通道高分辨率采样及携带不方便等情况,提出了一种基于USB的多路数据采集系统的设计方法。系统利用ARM+FPGA+AD7656的系统组合实现16路通道同步信号采样,FPGA用于实现对A/D转换的逻辑控制,通过ARM7处理器对A/D转换数据进行处理,再由USB接口与计算机进行数据通信。测试结果表明,基于FPGA与ARM的多通道数据采集系统结构简单、控制方便、设计成本较低,能够准确快速地对16路信号同时进行采集。  相似文献   

14.
A RISC architecture specifically designed for selective storage of high-speed digital words is presented. A specialized instruction set is created to allow programmable control of trigger conditions and storage memory. A RISC architecture is required to execute the instruction set and maintain a 10-MHz sample rate. The utility of the RISC system is illustrated by implementing both analog and digital data acquisitions. A prototype system was designed and fabricated for evaluation. Features of this design are presented  相似文献   

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An inexpensive and flexible microcomputer-based CAMAC data acquisition system is described. Quantitative performance characteristics are given to allow calculation of acquisition speed for an arbitrary configuration.  相似文献   

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A data acquisition system is described which is used to digitize the trajectory information obtained in a time projection chamber. The time projection chamber is part of a spectrometer used to study the momentum spectrum of positrons emitted in muon decay. It has 315 sense wires which induce signals on 5355 pads and creates approximately 402 000 bits of data for each event. Most of the data are zeros which are handled using a hardware-aided compaction scheme. The meaningful data are extracted by a modular system consisting of three basic building blocks. These are flash encoders with associated storage, wire hit memory boards, and bit-slice data preprocessors described herein.  相似文献   

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This paper proposes a novel architecture for a data acquisition system intended to support the next generation of ultrasonic imaging instruments operating at or above 100 MHz. Existing systems have relatively poor signal-to-noise ratios and are limited in terms of their maximum data sampling rate, both of which are improved by a combination of embedded averaging and embedded interleaved sampling. "On-the-fly" pipelined operation minimizes control overheads for signal averaging. A two-clock sampling timing system provides for effective sampling rates that are a factor of 20 or more above the basic sampling rate of the analog-to-digital converter (ADC). The system uses commercial field-programmable gate array devices operated at clock frequencies commensurable with the ADC clock. Implementation is via the Xilinx Xtreme digital signal processing development kit, available at low cost. Sample rates of up to 2160 MHz have been achieved in combination with up to 16384 coherent averages using the above-mentioned off-the-shelf hardware.  相似文献   

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