SOI技术特点及晶圆材料的制备

随着微电子技术发展,要使器件水平进一步提高,除了进一步缩小芯片的特征尺寸外,采用新型材料也是有效的方法。文章介绍了SOI解决方案,阐述了SOI器件与体硅器件相比具有的明显优点。文章重点介绍了SOI晶圆材料的制备方法,目前广泛使用且较有发展前途的SOI的材料制备方法主要有注氧隔离的SIMOX（Seperation by Impolanted Oxygen）方法、硅片键合和反面腐蚀的BESOI（Bonding-Etchback SOI）方法、将键合与注入相结合的Smart Cut SOI方法。指出了SOI很有可能成为今后高性能和高可靠集成电路材料的主流。     

Dual material gate silicon on insulator junctionless MOSFET for low power mixed signal circuits

In this research paper, demonstrates, the logic performance of n and p channel complementary metal oxide semiconductor (CMOS) circuits implemented with dual material gate silicon on insulator junctionless transistor (DMG SOI JLT). The logic performance of a CMOS circuit is evaluated in terms of static power dissipation, voltage transfer characteristic, propagation delay and noise margin. The gate capacitance is less as compared to gate capacitance of DMG SOI transistor in saturation. The power dissipation for CMOS inverter of DMG SOI JLT is improved by 25% as compared to DMG SOI transistor. The DMG SOI JLT common source amplifier has 1.25 times amplification as that of DMG SOI transistor. The noise margin of DMG SOI JLT CMOS inverter is improved by 23% as compared to the DMG SOI transistor CMOS inverter. The NAND gate static power dissipation of DMG SOI JLT is found improved imperically as compared to DMG SOI transistor for various channel length. The improvement obtained is 53% for 20nm, 46% for 30nm and 34% for 40nm respectively. Static power dissipation of DMG SOI JLT inverter is reduced by 3% as compared to junction transistor inverter at channel length of 30nm.     

绝缘体上硅动态阈值nMOSFETs特性研究

基于绝缘体上硅技术,提出并研制动态阈值nMOSFETs结构.阐述了动态阈值nMOSFETs的工作原理.动态阈值nMOSFETs的阈值电压从VBS=0 V时的580 mV动态变化到VBS=0.6 V时的220 mV,但是这种优势并没有以增加漏电流为代价.因此动态阈值nMOSFETs的驱动能力较之浮体nMOSFETs在低压情况下,更具有优势.工作电压为0.6 V时,动态阈值nMOSFETs的驱动能力是浮体的25.5倍,0.7 V时为12倍.而且浮体nMOSFETs中的浮体效应,诸如Kink效应,反常亚阈值斜率和击穿电压降低等,均被动态阈值nMOSFETs结构有效抑制.     

SOI power devices

This paper provides an introduction to silicon-on-insulator (SOI) technology and the operating principles of high-voltage SOI devices, reviews the performance of the available SOI switching devices in comparison with standard silicon devices, discusses the reasoning behind the use of SOI technology in power applications and covers the most advanced novel power SOI devices proposed to date. The impact of SOI technology on power integrated circuits (PICs) and the problems associated with the integration of high-voltage and low-voltage CMOS are also analysed     

State-of-the-art and future of silicon on insulator technologies, materials, and devices

The context of SOI technologies is briefly presented in terms of wafer fabrication, configuration/performance of typical SOI devices, and operation mechanisms in partially and fully depleted MOSFETs. The future of SOI is tentatively explored, by discussing the further scalability of SOI transistors as well as the innovating architectures proposed for the ultimate generations of SOI transistors.     

SOI MOSFET器件的热载流子退化机理

介绍了绝缭体上硅（SOI）材料的制作方法．阐进了SOIMOSFET器件的热载流子注入效应的失效机理。研究表明：前沟和背面缺陷的耦合效应是SOI器件的特有现象．对SOI器件的退化构成潜在的威胁。虽然失效机理比体硅器件复杂,但并不会阻碍高性能、低电压ULSI SOI电路的发展。     

抗辐射SOI器件栅氧可靠性研究

对抗辐射SOI器件栅氧可靠性进行研究,比较了体硅器件、SOI器件、抗总剂量加固SOI器件的栅氧可靠性,发现SOI材料片的制备与抗总剂量加固过程中的离子注入工艺都会对顶层硅膜造成影响,进而影响栅氧可靠性。最后通过恒压应力法表征栅氧介质随时间击穿(TDDB)的可靠性,结果显示抗总剂量辐射加固工艺的12.5 nm栅氧在125℃高温5.5 V工作电压下TDDB寿命达到14.65年,满足SOI抗总剂量辐射加固工艺对栅氧可靠性的需求。     

ESD reliability and protection schemes in SOI CMOS output buffers

The electrostatic discharge (ESD) protection capability of SOI CMOS output buffers has been studied with Human Body Model (HBM) stresses. Experimental results show that the ESD voltage sustained by SOI CMOS buffers is only about half the voltage sustained by the bulk NMOS buffers. ESD discharge current in a SOI CMOS buffer is found to be absorbed by the NMOSFET alone. Also, SOI circuits display more serious reliability problem in handling negative ESD discharge current during bi-directional stresses. Most of the methods developed for bulk technology to improve ESD performance have minimal effects on SOI. A new Through Oxide Buffer ESD protection scheme is proposed as an alternative for SOI ESD protection. In order to improve ESD reliability, ESD protection circuitries can be fabricated on the SOI substrate instead of the top silicon thin film, after selectively etching through the buried oxide. This scheme also allows ESD protection strategies developed for bulk technology to be directly transferred to SOI substrate.<>     

以Si3N4为埋层的SOI结构制备与器件模拟

为了减少经典SOI器件的自加热效应,首次成功地用外延方法制备以Si3N4薄膜为埋层的新结构SOSN,用HRTEM和SRP表征了SOI的新结构.实验结果显示,Si3N4层为非晶状态,新结构的SOSN具有良好的结构和电学性能.对传统SOI和新结构SOI的MOSFETs输出电流的输出特性和温度分布用TCAD仿真软件进行了模拟.模拟结果表明,新结构SOSN的MOSFET器件沟道温度和NDR效益都得到很大的降低,表明SOSN能够有效地克服自加热效应和提高MOSFET漏电流.     

Fabrication and Simulation of Silicon-on-Insulator Structure with Si3N4 as a Buried Insulator

In order to minimize the self-heating effect of the classic SOI devices,SOI structures with Si3N4 film as a buried insulator (SOSN) are successfully formed using epitaxial layer transfer technology for the first time.The new SOI structures are investigated with high-resolution cross-sectional transmission electron microscopy and spreading resistance profile.Experiment results show that the buried Si3N4 layer is amorphous and the new SOI material has good structural and electrical properties.The output current characteristics and temperature distribution are simulated and compared to those of standard SOI MOSFETs.Furthermore,the channel temperature and negative differential resistance are reduced during high-temperature operation,suggesting that SOSN can effectively mitigate the self-heating penalty.The new SOI device has been verified in two-dimensional device simulation and indicated that the new structures can reduce device self-heating and increase drain current of the SOI MOSFET.     

0.6μm SOI NMOS器件ESD性能分析及应用

ESD设计是SOI电路设计技术的主要挑战之一,文章介绍了基于部分耗尽0.6μm SOI工艺所制备的常规SOI NMOS器件的ESD性能,以及采用改进方法后的SOI NMOS器件的优良ESD性能。通过采用100ns脉冲宽度的TLP设备对所设计的SOI NMOS器件的ESD性能进行分析,结果表明：SOI NMOS器件不适合...     

基于SLA的面向服务的基础设施

SOI/IaaS是指以服务的方式来提供基础设施的供给模型,它是云计算服务的重要基础,而SLA协议成为了SOI发展的助推器。介绍了SLA@SOI小组的研究工作,主要是SLA@SOI小组中SLA协议的基本思想和该小组提出的基于SLA的SOI框架,并总结了在该框架下管理基础设施的基本原理和基本过程。最后分析了该领域的未来发展方向。这项研究对云计算有着极为重要的意义。     

SOI LIGBT抗闩锁效应的研究与进展

概述了绝缘层上硅横向绝缘栅双极晶体管(SOI LIGBT)抗闩锁结构的改进历程,介绍了从早期改进的p阱深p+欧姆接触SOI LIGBT结构到后来的中间阴极SOI LIGBT、埋栅SOILIGBT、双沟道SOI LIGBT、槽栅阳极短路射频SOI LIGBT等改进结构;阐述了一些结构在抗闩锁方面的改善情况,总结指出抑制闩锁效应发生的根本出发点是通过降低p基区电阻的阻值或减小流过p基区电阻的电流来削弱或者切断寄生双极晶体管之间的正反馈耦合。     

SOI功率器件的新进展

回顾了应用于 SOI功率集成电路的 SOI功率器件的发展背景 ,论述了 SOI功率器件的开发现状 ,以及作为 SOI功率器件基础的 SOI材料制备技术和耐压结构研究的最新进展。同时指出了在 SOI功率器件研究中需要解决的问题 ,以及今后的研究发展重点     

全耗尽SOI MOSFET及CMOS／SOI电路的研究

采用ＳＩＭＯＸ材料，研制了一种全耗尽ＣＭＯＳ／ＳＯＩ模拟开关电路，研究了全耗尽ＳＯＩ ＭＯＳ场效应晶体管的阈值电压与背栅偏置的依赖关系，对漏源击穿的Ｓｎａｐｂａｃｋ特性进行分析，介绍了薄层ＣＭＯＳ／ＳＩＭＯＸ制作工艺，给出了全耗尽ＣＭＯＳ／ＳＯＩ电路的测试结果。     

Off-leakage and drive current characteristics of sub-100-nm SOI MOSFETs and impact of quantum tunnel current

This paper estimates the off-leakage current (I/sub off/) and drive current (I/sub on/) of various SOI MOSFETs by simulations based on the hydrodynamic-transport model; the band-to-band tunneling (BBT) effect at the drain is taken into consideration. Here, the simulations are done for SOI structures with a thick channel where the distinct quantization of energy is irrelevant to the present results. It is shown that merging hydrodynamic transport with the BBT effect is indispensable if realistic I/sub off/ estimates are to be achieved. It is shown that the symmetric double-gate SOI MOSFET does not always offer better drivability than other SOI MOSFETs, and that a single-gate SOI MOSFET with carefully selected parameters exhibits superior performance to double-gate SOI MOSFETs. It is also demonstrated that the quantum tunnel current is not significant, even in 20-nm channel SOI MOSFETs. The results suggest that we can still employ the conventional semi-classical method to estimate the off-leakage current of sub-100-nm channel low-power SOI MOSFETs.     

Proposal of a partial-ground-plane (PGP) silicon-on-insulator (SOI)MOSFET for deep sub-0.1-μm channel regime

This letter proposes a new device structure which is called the “partial-ground-plane (PGP) silicon-on-insulator (SOI) MOSFET.” The PGP SOI MOSFET minimizes the short-channel effect (SCE) compared to the conventional single-gate (SG) SOI MOSFET because the gate-induced field in the SOI layer is held high by the PGP region. This results in a lower stand-by leakage current. The PGP SOI MOSFET also shows much better switching performance and extremely high analog performance because of its smaller parasitic capacitance compared to the conventional ground-plane (GP) device. Thus, it is shown that the PGP SOI MOSFET is a promising candidate for future deep-sub-0.1-μm mixed-mode LSIs     

Influences of buried-oxide interface on inversion-layer mobility inultra-thin SOI MOSFETs

This paper reports on a study of the inversion-layer mobility in n-channel Si MOSFETs fabricated on a silicon-on-insulator (SOI) substrate. In order to make clear the influences of the buried-oxide interface on the inversion-layer mobility in ultra-thin film SOI transistors, SOI wafers of different quality at the buried-oxide interface were prepared, and the mobility behaviors were compared quantitatively. The transistors with a relatively thick SOI film exhibited the universal relationship between the effective mobility and the effective normal field, regardless of the buried-oxide interface quality. It was found, however, that Coulomb scattering due to charged centers at the backside interface between SOI films and buried oxides has great influence on the effective mobility in the thin SOI thickness region, depending on the buried-oxide interface quality. This means that Coulomb scattering due to charged centers at the buried-oxide interface can degrade the mobility with decreasing SOI thickness, unless the SOI wafer quality at the buried-oxide interface is controlled carefully     

The enhancement of gate-induced-drain-leakage (GIDL) current inshort-channel SOI MOSFET and its application in measuring lateralbipolar current gain β

An off-state leakage current unique for short-channel SOI MOSFETs is reported. This off-state leakage is the amplification of gate-induced-drain-leakage current by the lateral bipolar transistor in an SOI device due to the floating body. The leakage current can be enhanced by as much as 100 times for 1/4 μm SOI devices. This can pose severe constraints in future 0.1 μm SOI device design. A novel technique was developed based on this mechanism to measure the lateral bipolar transistor current gain β of SOI devices without using a body contact     

On the performance of single-gated ultrathin-body SOI Schottky-barrier MOSFETs

The authors study the dependence of the performance of silicon-on-insulator (SOI) Schottky-barrier (SB) MOSFETs on the SOI body thickness and show a performance improvement for decreasing SOI thickness. The inverse subthreshold slopes S extracted from the experiments are compared with simulations and an analytical approximation. Excellent agreement between experiment, simulation, and analytical approximation is found, which shows that S scales approximately as the square root of the gate oxide and the SOI thickness. In addition, the authors study the impact of the SOI thickness on the variation of the threshold voltage V/sub th/ of SOI SB-MOSFETs and find a nonmonotonic behavior of V/sub th/. The results show that to avoid large threshold voltage variations and achieve high-performance devices, the gate oxide thickness should be as small as possible, and the SOI thickness should be /spl sim/ 3 nm.