一种染色问题的数学模型

建立了一种染色问题的数学模型，利用模2意义下的矩阵表示，将原问题归结为线性方程组的求解，从而给出了一个多项式算法。     

基于受限信任关系和概率分解矩阵的推荐

现有的推荐算法很难对没有任何记录的冷启动用户或者历史记录稀疏的用户给出准确的推荐,即用户的冷启动问题.本文提出一种基于受限信任关系和概率分解矩阵的推荐方法,由不信任关系约束信任关系的传播,得到准确且覆盖全面的用户信任关系矩阵,并通过对用户信任关系矩阵和用户商品矩阵的概率分解联合用户信任关系和用户商品矩阵信息,为用户给出推荐.实验表明该方法对冷启动用户和历史记录稀疏的用户的推荐效果有较大幅度的提升,有效地解决了用户的冷启动问题.     

HFEM公钥密码方案的设计与实现

基于BMQ问题的困难性,以及有限域上的矩阵与向量之间的关系,提出了一种新的公钥密码方案,即隐藏域上遍历矩阵的公钥密码.给出了有关矩阵集合的约束条件以及利用遍历矩阵来构造满足条件之矩阵集合的方法.与已有MPKC方案相比,HFEM具有陷门设计新颖、算法简单、不涉及任何乘幂及复杂运算、加/解密算法效率相当、中心映射难以抽象、密钥/明文/密文空间大等特点.     

动态规划算法研究

动态规划算法通常用于求解具有某种最优性质的问题,在这类问题中,可能会有许多可行解,每一个解都对应于一个值,我们希望找到具有最优值的解。本文主要研究动态规划算法的特点、基本思想以及其解决问题的具体步骤,详细分析其用于解决矩阵连乘问题的上的算法设计,并给出算法实现。     

电磁问题中几种减少计算时间的方法和比较性研究

在电磁理论问题的求解中，往往会遇到大系统问题，如何减少大系统问题的计算时间是一个具有共性的重要课题，本文对求解大系统问题的几秒方法进行了介绍和比较性研究，其中包括矩量法，网络分解法，矩阵分块法和空域分解法，文章在简述了这些方法的原理之后，给出了用上述方法以及用普通的矩量法计算同一问题的计算时间和储存量，并且比较了各种方法的特点。     

邻域图像帧存储体的理论及其实现

本文针对高速图像处理的数据流问题,特别是邻域图像数据的并行存取问题,提出了邻域图像帧存储体的体系结构,实现了帧存储体邻域图像数据的并行存取,极大地提高了图像处理的速度。本文描述了邻域图像帧存储体的特征,论述了它独特的存储结构,给出了轮换矩阵,地址标识轮换矩阵定义,揭示了邻域存取规律。本文给出了结构邻域图像帧存储体的具体方法并给出了实例。     

圆阵测向Butler矩阵网络和电路设计

文中给出了宽频带线性相位多模圆阵测向技术中天线馈电网络(Butler矩阵)的网络扩阵设计方法和实际矩阵电路研制中应注意的一些技术细节。提出了单向矩阵扩阵设计方法,使扩阵设计过程简单明了,给出的高阶圆阵测向矩阵所含微波微分移相器数量、种类及相移量较传统方法显著减少,有利于提高实际矩阵的幅相精度,降低矩阵的插入损耗。文中也介绍了提高矩阵部件耦合带状线正交电桥、功分器、微分移相器等微波元器件性能的一些方法以及实际矩阵电路设计装配调试方面应注意的一些问题。     

基于矩阵作用问题的公钥密码体制抗量子攻击安全性分析

半群作用问题作为离散对数问题的推广，在公钥密码的设计中有着重要应用。通过分析基于整数矩阵乘法半群在交换群直积上的作用问题的公钥密码体制，将矩阵看作直积元素的指数，这类矩阵作用具有类似群的指数运算法则。首先证明了若矩阵作用是单射或隐藏子群的生成元个数小于或等于矩阵阶的平方，则这类矩阵作用问题可在多项式时间归约为矩阵加法群直和的隐藏子群问题。其次证明了交换矩阵作用问题一定可在多项式时间归约为矩阵加法群直和的隐藏子群问题。因此基于这类矩阵作用问题的公钥密码体制无法抵抗量子攻击，该结论对抗量子攻击的公钥密码设计有理论指导意义。     

基于矩阵相似度的专家客观权重确定方法

针对区间型多属性群决策中的专家赋权问题,提出了基于矩阵相似度的专家客观权重的确定方法。首先,通过对加权规范化决策矩阵进行两两比较得到相似度矩阵;然后对相似度矩阵每行或每列求和,计算出粗权重,并且给出了区间型理想矩阵的概念;最后,通过计算加权规范化决策矩阵与区间型理想矩阵的投影值得到专家权重。与区间型理想解相比,文中给出的区间型理想矩阵考虑了专家的决策权力,更加准确。算例验证了该方法的有效性。     

边棱元法—一种模拟和分析电磁场的新型计算方法

边棱元法是一种基于有限元网格划分的模拟和分析电磁场的新型计算方法，和传统的有限元（节点元）相比，它具有无虚模干扰、变量少，计算量小等优点。本文给出了基于四面体边棱元的三维电磁问题的计算公式和非均匀填充介质的矩形微波谐振腔的计算结果；首次定量地比较了边棱元和节点元的总体矩阵；讨论了零本征值的根源，首次给出其总数的预测公式。     

A Flexible Architecture for Modular Arithmetic Hardware Accelerators based on RNS

Modular arithmetic is a building block for a variety of applications potentially supported on embedded systems. An approach to turn modular arithmetic more efficient is to identify algorithmic modifications that would enhance the parallelization of the target arithmetic in order to exploit the properties of parallel devices and platforms. The Residue Number System (RNS) introduces data-level parallelism, enabling the parallelization even for algorithms based on modular arithmetic with several data dependencies. However, the mapping of generic algorithms to full RNS-based implementations can be complex and the utilization of suitable hardware architectures that are scalable and adaptable to different demands is required. This paper proposes and discusses an architecture with scalability features for the parallel implementation of algorithms relying on modular arithmetic fully supported by the Residue Number System (RNS). The systematic mapping of a generic modular arithmetic algorithm to the architecture is presented. It can be applied as a high level synthesis step for an Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA) design flow targeting modular arithmetic algorithms. An implementation with the Xilinx Virtex 4 and Altera Stratix II Field Programmable Gate Array (FPGA) technologies of the modular exponentiation and Elliptic Curve (EC) point multiplication, used in the Rivest-Shamir-Adleman (RSA) and (EC) cryptographic algorithms, suggests latency results in the same order of magnitude of the fastest hardware implementations of these operations known to date.     

ASIC techniques for high-performance digital signal processing

We describe a high-level ASIC (application specific integrated circuit) synthesis system aimed at rapid and efficient realisation of integer arithmetic “engines” for signal processing bottleneck computations. Novel software features include bit-level scheduling which allocates numerical resources for computation, and a parameter synthesis system which maximises the use of this resource. Underlying synthesis is a generic digit-serial integer arithmetic processing architecture, with module generation capability across a wide parameter space for a useful set of primitive arithmetic operations. We outline the principal components of the tool, and briefly describe some application examples.     

基于FPGA的Cholesky分解矩阵求逆

针对在空时自适应处理(STAP)中通常采用Cholesky分解矩阵求逆算法求杂波协方差矩阵的逆矩阵,设计了基于FPGA的并行化Cholesky分解矩阵求逆运算模块的实现架构。该模块分成Cholesky分解子模块、三角矩阵求逆子模块和三角矩阵相乘子模块等三部分,流水执行求逆运算。通过实测与仿真,对矩阵阶数、运算并行度、FPGA占用资源、运算时间和运算精度等要素之间的关系进行了详细分析。     

Generic signal processor implementation with VHSIC

This paper illustrates the relationship between clock and data rates for a variety of generic processor architectures. A significant result for signal processing is that if memory and arithmetic chips operate at the same clock rate, processor performance is constrained by the rate at which memory may be accessed. The paper presents a case study of the implementation of a typical generic signal processor, the AOSP Macro Function Signal Processor using Very High Speed Integrated Circuit (VHSIC) technology. It is shown that VHSIC technology, with high speeds and high levels of integration is well suited to the implementation of this generic signal processor.     

嵌入式系统下摄像头数据解码和优化

为了实现摄像头数据的传输速度的提高,节省嵌入式系统的有限资源,我们实现了一套摄像头据解码的优化算法。该算法采用矩阵解码、浮点运算替代,汇编优化等方法,最终实现了图像传输帧率的提高,从而提高了图像的实时性并提升了系统的稳定性能。     

Novel Power-Delay-Area-Efficient Approach to Generic Modular Addition

Modular adders are fundamental arithmetic components typically employed in residue number system (RNS)-based digital signal processing (DSP) systems. They are widely used in modular multipliers and residue-to-binary converters and in implementing other residue arithmetic operations such as scaling. In this paper, a methodology for designing power-delay-area-efficient modular adders based on carry propagate addition is presented. The binary representational characteristics of the modulus are exploited to allow the sharing of hardware in a fast modular adder topology. VLSI implementation results using 0.13- standard-cell technology, together with a theoretical analysis, show that this approach produces adders that offer efficient tradeoffs when compared with the fastest through to the smallest generic modular adders in the literature.     

Generating algorithm for integer DST radixes in video coding

Recently released H.265 is the new generation video coding standard established by ITU and ISO jointly. H.265 is the first to apply discrete sine transform (DST) to transform unit in intra prediction block, with it implemented in an integer transform approach. Given that the integer transform radixes of DST are not unique, it is a key task to seek for them possessing strong de-correlation capability and simple arithmetic calculation as well. This paper presents a generic generating algorithm for integer DST transform radixes through a deep insight into the principle of integer DST transform. Subject to three essential constraints on integer transform matrix, this method establishes a cost function comprising orthogonality metric and accuracy metric with respect to entries of a 4 × 4 matrix, and then seeks transform radixes via a heuristic search strategy. Experimental results show that our method can find out a set of DST radixes after dozens of search steps. The revealed DST radixes not only cover the one used by H.265 but also include a basis superior over H.265’s in terms of orthogonality and precision.     

Fault-tolerant matrix arithmetic and signal processing on highly concurrent computing structures

Hardware for executing matrix arithmetic and signal processing algorithms at high speeds is in great demand in many real-time and scientific applications. With the advent of VLSI technology, large numbers of processing elements which cooperate with each other at high speed have become economically feasible. Since any functional error in a high-performance system may seriously jeopardize the operation of the system and its data integrity, some level of fault tolerance must be incorporated in order to ensure that the results of long computations are valid. Since the major computational requirements for many important real-time signal processing tasks can be reduced to a common set of basic matrix operations, the development of a unified fault-tolerant scheme for matrix operations can solve the problems of both reliable signal processing and reliable matrix operations. Earlier work proposed a low-cost checksum scheme for fault-tolerant matrix operations on multiple processor systems. However, this scheme can only correct errors in matrix multiplication; it can detect, but not correct, errors in matrix-vector multiplication, LU decomposition, matrix inversion, etc. In order to solve these problems with the checksum scheme, a very general matrix encoding scheme is proposed in this paper to achieve fault-tolerant matrix arithmetic and signal processing with linear arrays, which are believed to hold the most promise in VLSI computing structures for their flexibility, low cost, and applicability to most of the interesting algorithms. This proposed technique is, therefore, a very cost-effective encoding technique to achieve fault-tolerant matrix arithmetic and signal processing on highly concurrent VLSI computing structures.     

Simplified matrix inversion for optimization of antenna arrays

A special form of complex matrix called a "phase-difference matrix" that arises in the optimization of antenna arrays is discussed. It is shown that the inverse of such a matrix can be obtained by inverting an associated real matrix without having to perform any arithmetic operations with complex numbers.     

基于IFS分形理论的信源编码技术的研究

本文首次系统地研究了基于ＩＦＳ分形理论的信源压缩编码与传统方法的关系。