Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks

A new logic style called low-swing current mode logic (LSCML) is presented. It features a dynamic and differential structure and a low-swing current mode operation. The LSCML logic style may be used for hardware implementation of secure smart cards against differential power analysis (DPA) attacks but also for implementation of self-timed circuits thanks to its self-timed operation. Electrical simulations of the Khazad S-box have been carried out in 0.13 μm PD (partially depleted) SOI CMOS technology. For comparison purpose, the Khazad S-box was implemented with the LSCML logic and two other dynamic differential logic styles previously reported. Simulation results have shown an improved reduction of the data-dependent power signature when using LSCML circuits. Indeed the LSCML based Khazad S-box has shown a power consumption standard deviation more than two times smaller than the one in DyCML and almost two times smaller than the one in DDCVSL.     

Low‐Power Design of Hardware One‐Time Password Generators for Card‐Type OTPs

Since card‐type one‐time password (OTP) generators became available, power and area consumption has been one of the main issues of hardware OTPs. Because relatively smaller batteries and smaller chip areas are available for this type of OTP compared to existing token‐type OTPs, it is necessary to implement power‐efficient and compact dedicated OTP hardware modules. In this paper, we design and implement a low‐power small‐area hardware OTP generator based on the Advanced Encryption Standard (AES). First, we implement a prototype AES hardware module using a 350 nm process to verify the effectiveness of our optimization techniques for the SubBytes transform and data storage. Next, we apply the optimized AES to a real‐world OTP hardware module which is implemented using a 180 nm process. Our experimental results show the power consumption of our OTP module using the new AES implementation is only 49.4% and 15.0% of those of an HOTP and software‐based OTP, respectively.     

Design and Implementation of Unified Hardware for 128‐Bit Block Ciphers ARIA and AES

ARIA and the Advanced Encryption Standard (AES) are next generation standard block cipher algorithms of Korea and the US, respectively. This letter presents an area‐efficient unified hardware architecture of ARIA and AES. Both algorithms have 128‐bit substitution permutation network (SPN) structures, and their substitution and permutation layers could be efficiently merged. Therefore, we propose a 128‐bit processor architecture with resource sharing, which is capable of processing ARIA and AES. This is the first architecture which supports both algorithms. Furthermore, it requires only 19,056 logic gates and encrypts data at 720 Mbps and 1,047 Mbps for ARIA and AES, respectively.     

Memristive Logic‐in‐Memory Integrated Circuits for Energy‐Efficient Flexible Electronics

A memristive nonvolatile logic‐in‐memory circuit can provide a novel energy‐efficient computing architecture for battery‐powered flexible electronics. However, the cell‐to‐cell interference existing in the memristor crossbar array impedes both the reading process and parallel computing. Here, it is demonstrated that integration of an amorphous In‐Zn‐Sn‐O (a‐IZTO) semiconductor‐based selector (1S) device and a poly(1,3,5‐trivinyl‐1,3,5‐trimethyl cyclotrisiloxane) (pV3D3)‐based memristor (1M) on a flexible substrate can overcome these problems. The developed a‐IZTO‐based selector device, having a Pd/a‐IZTO/Pd structure, exhibits nonlinear current–voltage (I–V) characteristics with outstanding stability against electrical and mechanical stresses. Its underlying conduction mechanism is systematically determined via the temperature‐dependent I–V characteristics. The flexible one‐selector?one‐memristor (1S–1M) array exhibits reliable electrical characteristics and significant leakage current suppression. Furthermore, single‐instruction multiple‐data (SIMD), the foundation of parallel computing, is successfully implemented by performing NOT and NOR gates over multiple rows within the 1S–1M array. The results presented here will pave the way for development of a flexible nonvolatile logic‐in‐memory circuit for energy‐efficient flexible electronics.     

Cooperative amplify‐and‐forward partial relay selection with outdated channel information in spectrum‐sharing systems

Recently, cooperative relaying techniques have been integrated into spectrum‐sharing systems in an effort to yield higher spectral efficiency. Many investigations on such systems have assumed that the channel state information between the secondary transmitter and primary receiver used to calculate the maximum allowable transmit secondary user transmit power to limit the interference is known to be perfect. However, because of feedback delay from the primary receiver or the time‐varying properties of the channel, the channel information may be outdated, which is an important scenario to cognitive radio systems. In this paper, we investigate the impact of outdated channel state information for relay selection on the performance of partial relay selection with amplify and forward in underlay spectrum‐sharing systems. We begin by deriving a closed‐form expression for the outage probability of the secondary network in a Rayleigh fading channel along with peak received interference power constraint and maximum allowable secondary user transmit power. We also provide a closed‐form expression for the average bit‐error rate of the underlying system. Moreover, we present asymptotic expressions for both the outage probability and average bit‐error rate in the high signal‐to‐noise ratio regime that reveal practical insights on the achievable diversity gain. Finally, we confirm our results through comparisons with computer simulations. Copyright © 2016 John Wiley & Sons, Ltd.     

A lightweight authentication scheme based on self‐updating strategy for space information network

The security of space information network (SIN) is getting more and more important now. Because of the special features of SIN (e.g., the dynamic and unstable topology, the highly exposed links, the restricted computation power, the flexible networking methods, and so on), the security protocol for SIN should have a balance between security properties and computation/storage overhead. Although a lot of security protocols have been proposed recently, few can provide overall attacks resistance power with low computation and storage cost. To solve this problem, in this paper we propose a lightweight authentication scheme for space information network. It is mainly based on the self‐updating strategy for user's temporary identity. The scheme consists of two phases, namely, the registration phase and the authentication phase. All the computing operations involved are just hash function (h), the bit‐wise exclusive‐or operation (⊕), and the string concatenation operation (||), which are of low computation cost. The security properties discussion and the attacks–resistance power analysis show that the proposed authentication scheme can defend against various typical attacks, especially denial of service attacks. It is sufficiently secure with the lowest computation and storage costs. Furthermore, the formal security proof in SVO logic also demonstrates that the scheme can satisfy the security goals very well. Copyright © 2016 John Wiley & Sons, Ltd.     

基于状态映射的AES算法硬件混淆设计

代码混淆利用系统自身逻辑来保护内部重要信息和关键算法,常用于软件代码的安全防护,确保开发者和用户的利益。如何在硬件电路上实现混淆、保护硬件IP核的知识产权,也是亟待解决的问题。该文通过对硬件混淆和AES算法的研究,提出一种基于状态映射的AES算法硬件混淆方案。该方案首先利用冗余和黑洞两种状态相结合的状态映射方式,实现有限状态机的混淆;然后,采用比特翻转的方法,实现组合逻辑电路的混淆;最后,在SMIC 65 nm CMOS工艺下设计基于状态映射的AES算法硬件混淆电路,并采用Toggle、数据相关性和代码覆盖率等评价硬件混淆的效率和有效性。实验结果表明,基于状态映射的AES算法硬件混淆电路面积和功耗分别增加9%和16%,代码覆盖率达到93%以上。     

Dynamic inhomogeneous S-Boxes design for efficient AES masking mechanisms

It is an important challenge to implement a lowcost power analysis immune advanced encryption standard （AES） circuit. The previous study proves that substitution boxes （S-Boxes） in AES are prone to being attacked, and hard to mask for its non-linear characteristic. Besides, large amounts of circuit resources in chips and power consumption are spent in protecting S-Boxes against power analysis. Thus, a novel power analysis immune scheme is proposed, which divides the data-path of AES into two parts： inhomogeneous S-Boxes instead of fixed S-Boxes are selected randomly to disturb power and logic delay in the non-linear module; at the same time, the general masking strategy is applied in the linear part of AES. This improved AES circuit was synthesized with united microelectronics corporation （UMC） 0.25 μm 1.8 V complementary metal-oxide-semiconductor （CMOS） standard cell library, and correlation power analysis experiments were executed. The results demonstrate that this secure AES implementation has very low hardware cost and can enhance the AES security effectually against power analysis.     

Optimal power scheduling in 802.11n wireless networks for real‐time services

The growing popularity of mobile devices in our daily life demands higher throughput of wireless networks. The new communication standard 802.11n has significantly improved throughput because of the use of advanced technologies such as the multiple‐input multiple‐output communication technique. Because mobile devices are usually battery‐operated, power efficiency is critical; on the other hand, delay performance can be improved by transmitting at high power. To address the conflicting requirement of power saving and small delay, power scheduling is needed. In the past, many approaches to power scheduling have been proposed for real‐time applications, but few of them have considered complicated modes of channel state information(CSI) in multiple‐input multiple‐output. In this paper, we study this and classify the CSI into four types, namely, constant, slow fading, fast fading, and unknown. For known CSI, we propose an optimal algorithm for power scheduling. For unknown CSI, we propose an approximate algorithm based on some heuristics. To improve resource utilization, a stochastic delay‐bound method is proposed for fast‐fading condition. Simulation results demonstrate that the performance achieved by the optimal and heuristic algorithms agrees well with the analysis. Copyright © 2012 John Wiley & Sons, Ltd.     

Towards the implementation of Multi‐band Multi‐standard Software‐Defined Radio using Dynamic Partial Reconfiguration

The vast evolution of fixed and mobile standards urges upgrading the hardware to be compatible with them. An efficient approach to reduce the required cost and effort is hardware reusability, which in turn can be achieved by a dynamically reconfigurable field programmable gate array (FPGA). This flexible hardware time multiplexing allows more logic to fit within the same area, which means fitting bigger designs into smaller less expensive devices, with more optimization of power consumption. This work shows the advantages of using the dynamic partial reconfiguration (DPR) technique, on a fine‐grained block level, in implementing a baseband physical layer processing module for software‐defined radio (SDR) chain that supports 3G, long‐term evolution (LTE), and WIFI standards. The benefits increase when the reconfiguration is not only dynamic but also takes place in run‐time without the need to switch off the system. A comparison is held on Xilinx Virtex 5 design kit XUPV5‐LX110T between the implementation of the baseband processing module with and without using the DPR technique in the 3G, long‐term evolution, and WIFI standards. The comparison addresses the area, power, memory, and time overhead. Experimental results reveal that the DPR technique improves the area and the power consumption with an acceptable increase in memory and latency. Xilinx ISE 14.7 is used for modules implementation, Xilinx PlanAhead is used in floorplanning for the different designs and applying the DPR technique, and Xilinx Power Analyzer is used to measure the power consumption.     

Noncomplementary BiCMOS logic and CMOS logic for low-voltage,low-power operation-a comparative study

This paper presents results of a comprehensive comparative study of six bipolar complementary metal-oxide-semiconductor (BiCMOS) noncomplementary logic design styles and two CMOS logic styles for low-voltage, low-power operation. These logic styles have been compared for switching power consumption and power efficiency (power-delay product). The examination offers two alternative approaches never used in other comparative studies. First, all BiCMOS-based styles are compared to low-power CMOS styles as opposed to a single conventional static CMOS style. Second, a low-power methodology has been used as opposed to performance methodology referred to in the previous logic comparisons. The styles examined are bootstrapped BiCMOS, bootstrapped full-swing BiCMOS, bootstrapped bipolar CMOS, Seng-Rofail's bootstrapped BiCMOS, modified full-swing BiCMOS, dynamic full-swing BiCMOS, double pass-transistor CMOS, and inverter-based CMOS. These design styles have been compared at various power supply voltages (0.9-3 V), with various output load capacitances (0.1-1 pF) at the frequency 50 MHz and temperature 27°C. The results clearly show which logic style is the most beneficial for which specific conditions     

Techniques for Random Masking in Hardware

A new technique for Boolean random masking of the logic and operation in terms of nand logic gates is proposed and applied for masking the integer addition. The new technique can be used for masking arbitrary cryptographic functions and is more efficient than previously known techniques, recently applied to the Advanced Encryption Standard (AES). New techniques for the conversions from Boolean to arithmetic random masking and vice versa are also developed. They are hardware oriented and do not require additional random bits. Unlike the previous, software-oriented techniques showing a substantial difference in the complexity of the two conversions, they have a comparable complexity being about the same as that of one integer addition only. All the techniques proposed are in theory secure against the first-order differential power analysis on the logic gate level. They can be applied in hardware implementations of various cryptographic functions, including AES, (keyed) SHA-1, IDEA, and RC6     

Efficient Masking Methods Appropriate for the Block Ciphers ARIA and AES

In this paper, we propose efficient masking methods for ARIA and AES. In general, a masked S‐box (MS) block can be constructed in different ways depending on the implementation platform, such as hardware and software. However, the other components of ARIA and AES have less impact on the implementation cost. We first propose an efficient masking structure by minimizing the number of mask corrections under the assumption that we have an MS block. Second, to make a secure and efficient MS block for ARIA and AES, we propose novel methods to solve the table size problem for the MS block in a software implementation and to reduce the cost of a masked inversion which is the main part of the MS block in the hardware implementation.     

Energy consumption optimization for self‐powered IoT networks with non‐orthogonal multiple access

Energy harvesting (EH) has been considered as one of the promising technologies to power Internet of Things (IoT) devices in self‐powered IoT networks. By adopting a typical harvest‐then‐transmit mode, IoT devices with the EH technology first harvest energy by using wireless power transfer (WPT) and then carry out wireless information transmission (WIT), which leads to the coordination between WPT and WIT. In this paper, we consider optimizing energy consumption of periodical data collection in a self‐powered IoT network with non‐orthogonal multiple access (NOMA). Particularly, we take into account time allocation for the WPT and WIT stages, node deployment, and constraints for data transmission. Moreover, to thoroughly explore the impact of different multiple access methods, we theoretically analyse and compare the performance achieved by employing NOMA, frequency division multiple access (FDMA), and time division multiple access (TDMA) in the considered IoT network. To validate the performance of the proposed method, we conduct extensive simulations and show that the NOMA outperforms the FDMA and TDMA in terms of energy consumption and transmission power.     

A Fully Synthesizable Bluetooth Baseband Module for a System‐on‐a‐Chip

Bluetooth is a specification for short‐range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area‐efficient digital baseband module for wireless technology. For area‐efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware‐efficient functions, such as low‐level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB) interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core on system‐on‐a‐chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a 0.25‐µm CMOS technology, the core size of which was only 2.79 mm×2.80 mm.     

Porphyrin‐ and Fullerene‐Based Molecular Photovoltaic Devices

We have developed a novel strategy for the construction of molecular photovoltaic devices where the porphyrins and fullerenes employed as building blocks are organized into nanostructured artificial photosynthetic systems by self‐assembly processes. Highly efficient photosynthetic energy‐ and electron‐transfer processes take place at gold and indium tin oxide (ITO) electrodes modified with self‐assembled monolayers of porphyrin‐ or fullerene linked systems. Porphyrins and fullerenes have also been assembled step by step to make large and uniform clusters on nanostructured semiconductor electrodes, which exhibit a high power‐conversion efficiency of close to 1 %. These results will provide valuable information on the design of donor–acceptor‐type molecular assemblies that can be tailored to construct highly efficient photovoltaic devices.     

The research of DPA attacks against AES implementations

This article examines vulnerabilities to power analysis attacks between software and hardware implementations of cryptographic algorithms. Representative platforms including an Atmel 89S8252 8-bit processor and a 0.25 um 1.8 v standard cell circuit are proposed to implement the advance encryption standard （AES）. A simulation-based experimental environment is built to acquire power data, and single-bit differential power analysis （DPA）, and multi-bit DPA and correlation power analysis （CPA） attacks are conducted on two implementations respectively. The experimental results show that the hardware implementation has less data-dependent power leakages to resist power attacks. Furthermore, an improved DPA approach is proposed. It adopts hamming distance of intermediate results as power model and arranges plaintext inputs to differentiate power traces to the maximal probability. Compared with the original power attacks, our improved DPA performs a successful attack on AES hardware implementations with acceptable power measurements and fewer computations.     

Compressive sensing‐based signal compression and recovery in UWB wireless communication system

In this paper, we propose a new compressive sensing‐based compression and recovery ultra‐wideband (UWB) communication system. Compared with the conventional UWB system, we can jointly estimate the channel and compress the data, which can also simplify the design of hardware. No information about the transmitted signal is required in advance as long as the channel follows autoregressive process. As an application example, real‐world UWB signal is collected and processed to evaluate the performance of our proposed system. The compression procedure is so simple that we just multiply random Gaussian or Bernoulli matrix with the original data to capture all the information we want. Simulation results show that the data could be perfectly recovered if the compression ratio does not exceed 2.5:1 when Bernoulli matrix is chosen as the sensing matrix. Copyright © 2012 John Wiley & Sons, Ltd.     

Power boosting factor determination in impulse postfix‐OFDM‐based positioning system

Based on recently introduced novel impulse postfix‐OFDM scheme, we proposed a joint time‐of‐arrival/angle‐of‐arrival positioning scheme, in which both channel estimation and positioning information can be realized by analyzing the channel impulse response estimated on an access point equipped with a uniform linear antenna array. However, the power boosting factor (PBF) determination of impulse postfix (IP) should be taken as an important issue, because a small PBF will result in imprecise channel estimation and deteriorate the communication quality, as well as positioning accuracy; in contrast, the huge power assignment on IP will lead to insufficient power allocated on date portion, when transmitted power is restricted, which also increases the system BER. In this paper, to obtain the optimal performance of both BER and positioning accuracy, we mathematically analyze the BER and positioning performance with increasing PBFs in the term of signal‐to‐noise ratio and confirm our assumption in the cases of quadrature phase‐shift keying and 16‐quadrature amplitude modulation, with computer simulation. The result applies that, as the PBF is increasing, the system BER is enhanced until PBF reaches 15 and starts deteriorating thereafter. According to the result, the decision criteria for determining PBF of IP should depend on practical preference of BER or positioning. Copyright © 2015 John Wiley & Sons, Ltd.