An all-digital phase-locked loop with 50-cycle lock time suitablefor high-performance microprocessors

A frequency-synthesizing, all-digital phase-locked loop (ADPLL) is fully integrated with a 0.5 μm CMOS microprocessor. The ADPLL has a 50-cycle phase lock, has a gain mechanism independent of process, voltage, and temperature, and is immune to input jitter. A digitally-controlled oscillator (DCO) forms the core of the ADPLL and operates from 50 to 550 MHz, running at 4× the reference clock frequency. The DCO has 16 b of binarily weighted control and achieves LSB resolution under 500 fs     

Low‐Power,All Digital Phase‐Locked Loop with a Wide‐Range,High Resolution TDC

In this paper, we propose a low‐power all‐digital phase‐ locked loop (ADPLL) with a wide input range and a high resolution time‐to‐digital converter (TDC). The resolution of the proposed TDC is improved by using a phase‐interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 mm² using 0.13 µm CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is ‐120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.     

A compact ADPLL based on symmetrical binary frequency searching with the same circuit

A compact all-digital phase-locked loop (C-ADPLL) based on symmetrical binary frequency searching (BFS) with the same circuit is presented in this paper. The minimising relative frequency variation error Δη (MFE) rule is derived as guidance of design and is used to weigh the accuracy of the digitally controlled oscillator (DCO) clock frequency. The symmetrical BFS is used in the coarse-tuning process and the fine-tuning process of DCO clock frequency to achieve the minimum Δη of the locked DCO clock, which simplifies the circuit architecture and saves the die area. The C-ADPLL is implemented in a 0.13 μm one-poly-eight-metal (1P8M) CMOS process and the on-chip area is only 0.043 mm², which is much smaller. The measurement results show that the peak-to-peak (Pk-Pk) jitter and the root-mean-square jitter of the DCO clock frequency are 270 ps at 72.3 MHz and 42 ps at 79.4 MHz, respectively, while the power consumption of the proposed ADPLL is only 2.7 mW (at 115.8 MHz) with a 1.2 V power supply. The measured Δη is not more than 1.14%. Compared with other ADPLLs, the proposed C-ADPLL has simpler architecture, smaller size and lower Pk-Pk jitter.     

Two Efficient Dual-Band and Wide-Band Low-Power DCO Designs Using Current Starving Gates,DCV and Reconfigurable Schmitt Triggers in 180 nm

Digitally controlled oscillators are the main cores in all-digital phase-locked loops (ADPLL), which are important for determining the range of frequency and power consumption in ADPLLs. In the conventional digitally controlled oscillator (DCO) designs, one single band of operation is assigned to the DCO. The following paper presents a new approach in the design of DCOs, which works in dual-band and wide-band modes with a control unit. In dual-band mode, the DCO works in two different ranges of frequencies simultaneously via digital control bits. The wide-band DCO (WBDCO) works in one wider range of frequencies consecutively. It seems that in the wide-band DCO, the gap width for the dual-band DCO (DBDCO) is zero. The previously mentioned designs allow the designer to have standard frequencies with the help of direct or multiplied frequencies. So, we can have a trade-off between power and performance. This means that we can have low power consumption in low-frequency applications and vice versa. The proposed designs are based on using digitally controlled capacitors, current starving gates and Schmitt triggers in critical points of the DCO loop, while preserving coarse and fine tunings. The non-delay linearity factors are clearly investigated and resolved with the use of a new combined control unit. The simulations of the proposed designs are performed in Hspice with a voltage of \(\mathrm{VDD}=1.8\) v in 180 nm CMOS technology for 64- and 128-bit input coarse codes. Our simulation and evaluation results showed that in the dual-band DCO, a 14.8 ps jitter was calculated at 134 MHz with 1.2131 mW power consumption, while in the wide band with overlap mode, a 68.7 ps jitter was measured at 184.61 MHz with 1.604 mW power consumption. Our designs are proper for reconfigurable and multi-standard ADPLL designs.     

600MHz BiCMOS digitally controlled oscillator for clock recovery and frequency synthesis PLLs

A 16-bit digitally controlled BiCMOS ring oscillator (DCO) is described. This BiCMOS DCO design provides improved frequency stability under thermal fluctuations. Simulations of a 5-stage DCO using 1μm BiCMOS process parameters achieved a controllable frequency range of 90-640MHz with a linear/quasi-linear range of around 300MHz. A tiny test chip was fabricated using MOSIS Orbit 2μm low-cost analogue CMOS process technology that provides a lateral NPN bipolar device option. Monotone frequency gain (frequency vs control-word transfer function) with fine stepping (tuning) over several kHz was verified experimentally, thus auguring the prospect of accurate frequency lock in an all-digital phase-locked loop (ADPLL) application. Worstcase jitter due to digital control transitions at pathological control-word boundaries for the BiCMOS DCO was observed to be less than 50 ps. This BiCMOS design would thus provide performance enhancement in PLL applications such as clock recovery and frequency synthesis.     

A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI

An all static CMOS ADPLL fabricated in 65 nm digital CMOS SOI technology has a fully programmable proportional-integral-differential (PID) loop filter and features a third order delta sigma modulator. The DCO is a three stage, static inverter based ring oscillator programmable in 768 frequency steps. The ADPLL lock range is 500 MHz to 8 GHz at 1.3 V and 25degC, and 90 MHz to 1.2 GHz at 0.5 V and 100degC. The IC dissipates 8 mW/GHz at 1.2 V and 1.6 mW/GHz at 0.5 V. The synthesized 4 GHz clock has a period jitter of 0.7 ps rms, and long term jitter of 6 ps rms. The phase noise under nominal operating conditions is 112 dBc/Hz measured at a 10 MHz offset from a 4 GHz center frequency. The total circuit area is 200 mum 150 mum.     

Low power FSK transmitter using all-digital PLL for IEEE 802.15.4g application

This paper presents low power frequency shift keying (FSK) transmitter using all-digital pll (ADPLL) for IEEE 802.15.4g application. In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The resolution of the proposed TDC is improved by using a phase-interpolator, which divides the inverter delay time and the time amplifier, which amplifies the time difference between the reference frequency and the DCO clock. The phase noise of the proposed ADPLL is also improved by using a fine resolution DCO with an active capacitor. To cover the wide tuning range and to operate at a low-power, a two-step coarse tuning scheme with a metal insulator metal capacitor and an active inductor is used. The FSK transmitter is implemented in 0.18 μm 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is 2.2 mm². The power consumption of the ADPLL and transmitter is 12.43 and 22.7 mW when the output power level of the transmitter is ?1.6 dBm at 1.8 V supply voltage, respectively. The frequency resolution of the TDC is 1.25 ps. The effective DCO frequency resolution with the active capacitance and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.83 GHz is ?121.5 dBc/Hz with a 1 MHz offset.     

An Interpolating Digitally Controlled Oscillator for a Wide-Range All-Digital PLL

A digitally controlled oscillator (DCO) for the all-digital phase-locked loop (ADPLL) with both the wide frequency range and the high maximum frequency was proposed by using the interpolation scheme at both the coarse and fine delay blocks of the DCO. The coarse block consists of two ladder-shaped coarse delay chains. The delay of the first one is an odd multiple of an inverter delay and that of the second one is an even multiple. An interpolation operation is performed at the second coarse delay chain, which reduces both the resolution of the coarse delay block and the delay range of the fine block to half. This increases the maximum output frequency of the DCO while it maintains the wide frequency range. The ADPLL with the proposed DCO was fabricated in a 0.18 mum CMOS process with the active area of 0.32 mm² . The measured output frequency of the ADPLL ranges from 33 to 1040 MHz at the supply of 1.8 V. The measured rms and peak-to-peak jitters are 13.8 ps and 86.7 ps, respectively, at the output frequency of 950 MHz. The power consumption is 15.7 mW.     

A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO

An all-digital phase-locked loop (ADPLL) with all components working with time interval or period signals is demonstrated. The ADPLL consists mainly of a free-running ring oscillator (FRO), a time to digital converter (TDC), a digitally controlled oscillator (DCO), a digital divider and a digital loop filter. In the proposed architecture, the TDC and DCO have an equal time resolution from the common FRO. The digital divider keeps the loop gain constant when the frequency multiplication factor changes. As a result, the ADPLL is inherently stable regardless of the variations of the process, supply voltage and temperature (PVT). The ADPLL is fabricated in 0.13 $mu$m CMOS process. Measurement results show that it works well over wide operation conditions, with the input frequencies ranging from 37.5 KHz to 25 MHz, frequency multiplication factors from 10 to 255, output frequencies from 10 MHz to 500 MHz, and supply voltages from 0.6 V to 1.6 V.      

A 400 MHz–1.5 GHz all digital integer-N PLL with a reference spur reduction technique

In this Letter, 400 MHz–1.5 GHz all digital integer-N PLL with a reference spur reduction is proposed. A reference spur is occurred by updating DCO control code at every reference clock period. To reduce a reference spur component, the phase detector which transfers phase error information only when phase error is detected has been designed. The measured clock jitter is 2.528 ps_rms at 1.5 GHz operation, and 3.991 ps_rms at 400 MHz operation. The ADPLL occupies 0.088 mm², and consumes 1.19 mW at 1.5 GHz. This ADPLL is implemented in 65 nm CMOS technology.     

基于65nm工艺的超高速全数字锁相环的设计和实现

论述了UMC 65nm CMOS工艺实现的全定制全数字锁相环.该锁相环用于提供高速嵌入武SRAM内建自测试所需的时钟.分析了全数字锁相环的工作原理和电路架构,并给出了整个锁相环系统的电路和版图实现.编码控制振荡器是全数字锁相环中的核心电路,提出了一种改进的编码控制振荡器,具有高线性度和高精度的特点.在理论上分析了全数字锁相环系统的稳定性,并给出所采用的锁相环架构的稳定性公式.该锁相环达最高输出频率为2GHz,抖动小于1%.     

An all-digital phase-locked loop for high-speed clock generation

An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented. The proposed ADPLL architecture uses both a digital control mechanism and a ring oscillator and, hence, can be implemented with standard cells. The ADPLL implemented in a 0.3-/spl mu/m one-poly-four-metal CMOS process can operate from 45 to 510 MHz and achieve worst case frequency acquisition in 46 reference clock cycles. The power dissipation of the ADPLL is 100 mW (at 500 MHz) with a 3.3-V power supply. From chip measurement results, the P/sub k/-P/sub k/ jitter of the output clock is <70 ps, and the root-mean-square jitter of the output clock is <22 ps. A systematic way to design the ADPLL with the specified standard cell library is also presented. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for system-on-chip applications.     

Design of high-frequency wide-range all digital phase locked loop in 90 nm CMOS

This paper presents a high-frequency wide tuning range all digital phase locked loop (ADPLL) designed using a 90 nm CMOS process with 1.2 V power supply. It operates in the frequency range of 1.9–7.8 GHz. The ADPLL uses a wide frequency range digital controlled oscillator (DCO) and a two stage acquisition process to obtain the fast lock time. The operation of the ADPLL includes both a frequency acquisition state and a phase acquisition state. A novel architecture is implemented which includes a coarse acquisition stage to obtain a monotonically increasing wide frequency range DCO for frequency acquisition and a fine control stage to achieve resolution of 18.75 kHz for phase tracking. Design considerations of the ADPLL circuit components and implementation using Cadence tools are presented. Spectre simulations demonstrate a peak-to-peak jitter value of <15 ps and a root mean square jitter value of 4 ps when locked at 5.12 GHz. The power consumption at 7.8 GHz is 8 mW and the frequency hopping time is 3.5 μs for a 3.2 GHz frequency change. Spectre simulations demonstrate ADPLL convergence to 5.12 GHz for the typical, fast, and slow process corners to support robust performance considering process variations.     

A low-power DCO using inverter interlaced cascaded delay cell

This paper presents a low-power small-area digitally controlled oscillator(DCO) using an inverters interlaced cascaded delay cell(IICDC).It uses a coarse-fine architecture with binary-weighted delay stages for the delay range and resolution.The coarse-tuning stage of the DCO uses IICDC,which is power and area efficient with low phase noise,as compared with conventional delay cells.The ADPLL with a DCO is fabricated in the UMC 180-nm CMOS process with an active area of 0.071 mm2.The output frequency range is 140–600 MHz at the power supply of 1.8 V.The power consumption is 2.34 m W @ a 200 MHz output.     

An all digital PLL with an active inductor DCO for LTE applications in 0.13 μm CMOS

In this paper, we propose a low-power all digital phase-locked loop with a wide input range, and a high resolution TDC that uses phase-interpolator and a time amplifier. The resolution of the proposed TDC is improved by using a phase-interpolator which divides the inverter delay time and the time amplifier which extends the time difference between the reference frequency and the DCO clock. The phase noise of the proposed ADPLL is improved by using a fine resolution DCO with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. To cover the wide tuning range and to operate at a low-power, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally in order to compensate for gain variations. The die area of the ADPLL is 0.8 mm² using 0.13 μm CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is −120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.     

LMS-based calibration of an RF digitally controlled oscillator for mobile phones

We propose a least-mean square based gain calibration technique of an RF digitally controlled oscillator (DCO) in an all-digital phase-locked loop (ADPLL). The DCO gain of about 12-kHz/least significant bit is subject to process, voltage and temperature variations, but is tracked and compensated in real time. Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wide-band frequency modulation that is independent from the ADPLL loop bandwidth. The technique is part of a single-chip fully compliant Global System for Mobile Communications (GSM)/EDGE transceiver in 90-nm digital CMOS.     

A low-power ADPLL using feedback DCO quarterly disabled in time domain

We propose a low-power ADPLL (all-digital phase-locked loop) using a controller which employs a binary frequency searching method in this paper. Glitch hazards and timing violations which occurred very often in the prior ADPLL designs are avoided by the control method and the modified DCO (digital-controlled oscillator) with multiplexers. Besides, the feedback DCO is disabled half a cycle in every two cycles so as to reduce 25% of dynamic power theoretically. The proposed design is implemented by only using the standard cells of a typical CMOS process. The feature of power saving is verified on silicon to be merely 1.53 mW at a 133 MHz output.     

一种应用于图像传感器的全数字锁相环设计

针对图像传感器中传统锁相环(PLL)存在的功耗高、抖动大,以及锁定时长等问题,提出了一种基于计数器架构的低功耗、低噪声、低抖动、快速锁定的分数分频全数字锁相环(ADPLL)设计方法。首先,采用动态调节锁定控制算法来降低回路噪声,缩短锁定时间。其次,设计了一个通用单元来实现数字时间转换器(DTC)和时间数字转换器(TDC)的集成,以降低该部分由于增益不匹配引起的抖动。基于180nm CMOS工艺的仿真结果表明,在1.8V电源电压下,该ADPLL能够实现250MHz~2.8GHz范围的频率输出,锁定时间为1.028μs,当偏移载波频率为1MHz时,相位噪声为-102.249dBc/Hz,均方根抖动为1.7ps。     

A new ADPLL architecture dedicated to program clock references synchronization

This paper presents a totally digital phase locked loop (PLL) used for the recovery of a MPEG-2 decoder clock. The All Digital PLL (ADPLL) is implemented with a frequency synthesizer based on a new technique for phase shifting, avoiding the phase accumulation of ADPLL using a ring oscillator or avoiding the multiphase generation if a delay-locked loop (DLL) is used. The strongest point of the proposed configuration is the possibility of implementing as many ADPLLs as needed in a single circuit, in the limit of the circuit resources, without additional external circuit. The transfer characteristic, frequency resolution and jitter performance are computed and discussed. Then, the ADPLL resources and the ADPLL performances in term of time response and jitter are reported.