Modeling of substrate current in p-MOSFET's

It is shown that the substrate current characterization method and modeling approach used for n-MOSFET's is also applicable to p-MOSFET's. The impact ionization rate extracted for holes is found to be 8 × 10⁶exp (-3.7 × 10⁶/E), where E is the electric field. Based on our measurement and modeling result, roughly twice the channel electric field is required for p-MOSFET's to generate the same amount of substrate current as n-MOSFET's. The hot-carrier-induced breakdown voltage is therefore also about two times larger.     

A physically-based MOS transistor avalanche breakdown model

A physically based breakdown model for MOSFET's is presented to rectify the unexplained experimental breakdown behaviors. The drain avalanche breakdown in the MOS transistor can be caused by either infinite multiplication (MI) or finite multiplication with positive feedback of the substrate current (MF) due to the impact ionization in the pinch-off region. The breakdown voltages of these two modes of breakdown have different dependencies on the biasing conditions and device parameters. For MI mode of breakdown, the breakdown voltage increases slowly with the gate voltage and can be approximated by the drain saturation voltage plus a constant offset. For MF mode of breakdown, the breakdown voltage decreases as the drain saturation current becomes larger. The calculated breakdown characteristics agree well with the measured ones for devices with effective channel length in the range of 0.44~10 μm     

An analysis of the concave MOSFET

The electrical characteristics of the concave MOSFET are analyzed by the two-dimensional numerical method and the theoretical result is in reasonable agreement with the experimental result. Even if the channel length of the concave MOSFET is short, the obtained current-voltage characteristics of the concave MOSFET are quite similar to those of the long-channel normal MOSFET and can be approximated by the normal MOSFET formula. In short-channel concave MOSFET's, the threshold voltage lowering due to the short-channel effect is not observed. It is observed that the threshold voltage of the concave MOSFET depends strongly on the substrate bias voltage as compared with the long-channel normal MOSFET. These observed results are followed by the two-dimensional numerical analysis. The increase of the punch-through breakdown voltage as well as that of the surface induced avalanche breakdown voltage of the concave MOSFET is predicted theoretically. The equivalent circuit model of the concave MOSFET is shown and discussed.     

An analytical breakdown model for short-channel MOSFET's

Avalanche-induced breakdown mechanisms for short-channel MOSFET's are discussed. A simple analytical model that combines the effects due to the ohmic drop caused by the substrate current and the positive feedback effect of the substrate lateral bipolar transistor is proposed. It is shown that two conditions must be satisfied before breakdown will occur. One is the emission of minority carriers into the substrate from the source junction, the other is sufficient avalanche multiplication to cause significant positive feedback. Analytical theory has been developed with the use of a published model for short-channel MOSFET's. The calculated breakdown characteristics agree well with experiments for a wide range of processing parameters and geometries.     

Excess gate current analysis of junction gate FET's by two- dimensional computer simulation

Gate current in a JFET under high drain bias is much higher than expected from the classical theory for reverse-biased p-n junctions. This excess gate current is caused by minority carriers generated by low-level impact ionization in the conducting channel, while the so-called breakdown voltage is determined by high-level avalanche multiplication near the gate edge at the surface. A simple one-dimensional model for the excess gate current is proposed. This model is based on the results of two-dimensional numerical analysis, which neglects the minority carrier motion. The excess gate current and avalanche breakdown voltage are calculated from one-dimensional ionization integrals, which are obtained numerically by utilizing the solution of two-dimensional analysis. The reverberant effect of the generated carriers on the potential distribution is assumed to be negligible. The results of the calculation are in good agreement with experimental results, without any adjustable parameters. Moreover, various impurity doping profiles are analyzed for the purpose of minimizing excess gate current. The present model requires a reasonably short computation time and is useful for designing JFET devices.     

A study of channel avalanche breakdown in scaled n-MOSFET's

The behavior of channel avalanche breakdown in n-MOSFET's miniaturized by isothermal constant field scaling is examined. Both a first-order analytical estimate and a rigorous two-dimensional numerical simulation of electrically wide devices are used to understand the scaling of channel breakdown. A sublinear dependence of snapback and sustaining voltages on channel length is found and explained. In practical terms, this sublinear dependence means that the relative MOS channel breakdown behavior improves for scaled-down devices. The breakdown behavior was verified against experimental data taken on a 1.3-µm n-channel device. In addition, a model is proposed for channel breakdown on unscaled devices that differ only in channel length.     

Two-dimensional analysis of the breakdown mechanism in theetched-groove silicon permeable base transistor

A two-dimensional, two-carrier simulation of a uniformly doped etched-groove permeable-base transistor which includes models for impact ionization and for Auger and Shockley-Read-Hall recombination is reported. It was found that for high current densities the breakdown voltage was reduced by channel avalanche. This mechanism was associated with a strong accumulation of electrons and holes in the source access region. In this region, the gate current remained low but the injection of electrons in the channel was enhanced, resulting in a degradation of the drain conductance and frequency performance     

Hot-carrier drifts in submicrometer p-channel MOSFET's

Hot-carrier-induced shifts in p-channel MOSFET operating characteristics have been observed down to drain voltages of - 6 V. Cases are discussed in which p-MOSFET's show up to two orders of magnitude larger degradation than corresponding n-MOSFET's. The shifts include current and threshold voltage increases. From dependences on stress gate voltage, stress drain voltage, time, and substrate current, the hot-carrier origin of the shifts is specified in detail.     

Substrate current model for submicrometer MOSFETs based on meanfree path analysis

The nonequilibrium effects of hot carriers are investigated to analyze avalanche generation for submicrometer MOSFET devices. A simple analytical expression for the impact ionization utilizing the mean free path concept is developed. It is incorporated into a conventional drift-diffusion equation solver (PISCES) to obtain the substrate current in submicrometer MOSFET devices. The transconductance for high drain bias and breakdown conditions are analyzed based on the proposed impact ionization model     

Channel-width measurements of LOCOS- and trench-isolated MOSFET'sby photoemission

A nondestructive, accurate, and simple method has been developed to measure channel width in processed MOSFET's fabricated with LOCOS or trench isolation. The method is based on spectroscopic analysis of the light emitted from breakdown occurring in the reverse-biased drain region. A high-resolution microscope is used to observe the photoemitted light from CMOS devices with channel widths ranging from 10 to 0.2 μm. The method is applicable to surface-channel n-MOSFET's fabricated with either isolation. For buried-channel p-MOSFET's, the method is not successful because reverse breakdown in the p⁺-drain region does not always occur at the edge, independent of the isolation technology used     

Drain voltage limitations of MOS transistors

A comprehensive investigation has been carried out into the factors which influence the maximum drain voltage of an M.O.S. transistor for normal pentode-like operation. The drain voltage is limited by two principal mechanisms, namely punch-through of the drain depletion region to the source, and breakdown, due to impact ionization in the high field region at the drain edge. A two-dimensional analysis technique for determining the drain voltage at the onset of either punch-through or avalanche breakdown, from a solution of Poisson's equation within the substrate depletion region, is described. The solutions are obtained using finite difference numerical methods which take into account the gate-induced potential profiles at the edge of the source and drain junctions. Boundary conditions of zero effective gate bias and channel current are imposed which simplify the solution of Poisson's equation to an electrostatic one. The punch-through voltage V_PT is defined as the drain-to-source voltage at which the longitudinal field at any point along the edge of the source region inverts in sign to permit the drift of minority carriers from source to drain. Breakdown voltage, V_BD, however, is determined by the drain voltage at which the maximum field in the device reaches the critical value for avalanche multiplication. Good agreement is achieved between theoretical and practical results for both mechanisms on a wide variety of devices. It is shown that V_PT decreases as the channel length and substrate doping concentration decrease and as the oxide thickness and diffusion depth increase. V_BD, however, decreases as the channel length, oxide thickness and diffusion depth decrease.Punch-through and breakdown are discussed for gate bias conditions above and below threshold. The sharp fall in breakdown voltage as the gate bias rises above threshold is explained on the basis of injected charge from the channel into the drain depletion region.     

A general control-volume formulation for modeling impact ionization in semiconductor transport

A method for incorporating impact ionization into a general control-volume formulation of semiconductor transport is described. The methods for electric-field and current-density vector evaluation and generated charge partitioning within a two-dimensional triangular element are given. The techniques employed allow device breakdown to be accurately determined independent of mesh orientation to current flow direction. The avalanche breakdown of a 1-µm n-MOSFET illustrates the approach. Regions where the drain current is a multivalued function of drain voltage are directly and self-consistently calculated for this device.     

Temperature dependence of carrier ionization rates and saturated velocities in silicon

The temperature dependencies of the carrier ionization rates and saturated drift velocities in silicon have been extracted from microwave admittance and breakdown voltage data of avalanche diodes. The avalanche voltage and broadband (2–8 GHz) microwave small-signal admittance were measured for junction temperatures in the range 280 to 590 K. An accurate model of the diode was used to calculate the admittance characteristic and voltage for each junction temperature. Subsequently, the values of ionization coefficients and saturated velocities were determined at each temperature by a numerical minimization routine to obtain the best fit between the calculated values and measured data. The resulting ionization rates are well fitted by the temperature dependent model developed by Crowell and Sze from the Baraff ionization-rate theory. The carrier scattering mean free path lengths, average energy loss per collision, and relative ionization cross section are obtained from the best fit agreement between the scattering model and experimental data. The parameter values determined here relevent for use with the above theory are the following:Parameter Holes Electrons ε_r(eV) 0.063 0.063 ε_i(eV) 1.6 1.6 λ_oo(Å) 81.2 77.4 σ 0.391 0.593 The values and temperature dependence of the saturated carrier velocities determined are in good agreement with other published results. At 300 K the low field (E?10⁴ V/cm) saturated velocity for electrons and holes is 10.4 and 7.4×10₆ cm/sec, respectively. The results obtained in this study are of general use for the modeling of effects related to avalanche breakdown and high-field carrier transport in silicon.     

Breakdowns in Si JFET's

A two-dimensional numerical analysis to clarify the breakdown phenomena in Si n-type JFET is described. In this analysis, the continuity equation for minority carriers is introduced to consider the effect of avalanche multiplication. The heat conduction equation is also taken into account to include the thermal effect on the breakdown voltage. The results obtained are: 1) the mechanisms of excess gate current (EGC), current-mode second breakdown (CSB), and thermal-mode second breakdown (TSB). 2) The effects of how channel impurity concentration Nc, drain current ID, and applied drain voltage VDGaffect EGC, CSB, and TSB are also reported.     

Subthreshold conduction in MOSFET's

The dependence of channel current in subthreshold operation upon drain, gate, and substrate voltages is formulated in terms of a simple model. The basic results are consistent with earlier approaches for long-channel devices. For short-channel devices, the variation of current with drain voltage up to the punch-through voltage is accurately described. The threshold voltage of a short-channel device as a function of applied voltages follows as a natural result of the derivation. Results are presented which confirm the theory over a wide range of drain and gate voltages. With the application of substrate bias it is concluded from the data and the theory that two-dimensional effects can cause dramatic increases in the drain conductance.     

Gate-drain avalanche breakdown in GaAs power MESFET's

The voltage breakdown behavior of a number of different MESFET structures has been investigated using a two-dimensional numerical model. The site of the avalanche is found to be under the drain edge of the gate in recessed devices under all bias conditions, but moves towards the drain contact in planar structures when the channel is not pinched off. The dependence of the breakdown voltage on a variety of geometrical and physical variables has been studied. In particular the surface is shown to play an important part in determining the breakdown voltage.     

Theoretical analysis of the DC avalanche breakdown in GaAs MESFET's

The channel avalanche breakdown in GaAs MESFET's has been investigated using nonstationary electron dynamics and an ionization coefficient taken as a function of average electron energy. Stationary high-field domains of different shapes and peak-field localization are calculated at the breakdown, depending on technological parameters, device geometry or gate bias. Design rules are given to obtain maximum saturated output power and a full-channel current breakdown voltage comparable to the one near pinchoff. In particular, it is found that both a recessed channel geometry and an increased gate-drain distance should yield the best device performances with a doping level not higher than about 1.2-10¹⁷cm^-3and a channel current Idssbetween 275 and 330 mA/mm.     

A new method for extracting the counter-implanted channel profileof enhancement-mode p-MOSFETs

A new methodology is proposed to extract the nonuniform channel doping profile of enhancement mode p-MOSFETs with counter implantation, based on the relationship between device threshold voltage and substrate bias. A selfconsistent mathematical analysis is developed to calculate the threshold voltage and the surface potential of counter-implanted long-channel p-MOSFET at the onset of heavy inversion. Comparisons between analytic calculation and two-dimensional (2-D) numerical analysis have been made and the accuracy of the developed analytic model has been verified. Based on the developed analytic model, an automated extraction technique has been successfully implemented to extract the channel doping profile. With the aid of a 2-D numerical simulator, the subthreshold current can be obtained by the extracted channel doping profile. Good agreements have been found with measured subthreshold characteristics for both long- and short-channel devices. This new extraction methodology can be used for precise process monitoring and device optimization purposes     

An analytical threshold voltage and subthreshold current model forshort-channel MESFETs

Short-channel effects on the subthreshold behavior are modeled in self-aligned gate MESFETs with undoped substrates through an analytical solution of the two-dimensional Poisson equation in the subthreshold region. Based on the resultant potential solution, simple and accurate analytical expressions for short-channel threshold voltage, subthreshold swing, and subthreshold drain current are derived. These are then used to develop an expression for minimum acceptable channel length. A comparative study of the short-channel effects in MESFETs with doped and undoped substrates indicates that channel lengths will be limited to 0.15-0.2 μm by subthreshold conduction. Besides offering insight into the device physics of the short-channel effects in MESFETs, the model provides a useful basis for accurate analysis and simulation of small-geometry GaAs MESFET digital circuits     

SiGe-channel heterojunction p-MOSFET's

The advances in the growth of pseudomorphic silicon-germanium epitaxial layers combined with the strong need for high-speed complementary circuits have led to increased interest in silicon-based heterojunction field-effect transistors. Metal-oxide-semiconductor field-effect transistors (MOSFET's) with SiGe channels are guided by different design rules than state-of-the-art silicon MOSFET's. The selection of the transistor gate material, the optimization of the silicon-germanium channel profile, the method of threshold voltage adjustment, and the silicon-cap and gate-oxide thickness sensitivities are the critical design parameters for the p-channel SiGe MOSFET. Two-dimensional numerical modeling demonstrates that n⁺ polysilicon-gate SiGe p-MOSFET's have acceptable short-channel behavior at 0.20 μm channel lengths and are preferable to p⁺ polysilicon-gate p-MOSFET's for 2.5 V operation. Experimental results of n⁺-gate modulation-doped SiGe p-MOSFET's illustrate the importance of the optimization of the SiGe-channel profile. When a graded SiGe channel is used, hole mobilities as high as 220 cm² /V.s at 300 K and 980 cm²/V.s at 82 K are obtained