Polycrystalline silicon-film™ solar cells: Present and future

Future crystalline silicon solar cells will have increased performance and reduced cost. Increased performance will come from thin silicon with light trapping, provided that it includes back-surface passivation. Cost reduction will come from the growth of this thin silicon light-trapping structure on a low-cost substrate. the silicon will be polycrystalline. Solar cells formed with thin (< 50 μm) silicon active layers can produce higher conversion efficiencies at reduced material requirements than conventional ingot-based silicon devices. This paper presents the essential features of high-performance device design based on thin silicon layers, the design features of the Silicon-Film^−TM technology, the sequence of products that emerge from its development and recent results from the first commercial-scale, large-area (225 cm⁻²) Silicon-Film^−TM solar cell product.     

Estimation of breast tumor thermal properties using infrared images

The major goal of this paper is to help detect breast cancer early based on infrared images. Some procedures, protocols and numerical simulations were developed or performed. Two different issues are presented. The first is the development of a standardized protocol for the acquisition of breast thermal images including the design, construction and installation of mechanical apparatus. The second part is related to the greatest difficulty for the numerical computation of breast temperature profiles that is caused by the uncertainty of the real values of the thermophysical parameters of some tissues. Then, a methodology for estimating thermal properties based on these infrared images is presented. The commercial software FLUENT^TM was used for the numerical simulation. A Sequential Quadratic Programming (SQP) method was used to solve the inverse problem and to estimate the thermal conductivity and blood perfusion of breast tissues. The results showed that it is possible to estimate the thermophysical properties using the thermography. The next stage will be to use the geometry of a real breast for the numerical simulation in conjunction with a linear mapping of the temperatures measured over the breast volume.     

New CMOS process using a thermal-oxide mask for making <Emphasis Type="Italic">n</Emphasis><Superscript>−</Superscript>- and <Emphasis Type="Italic">p</Emphasis><Superscript>−</Superscript>-Wells

A new manufacturing process is proposed and evaluated for CMOS memory circuits that is designed to decrease labor input and to increase yield. It essentially uses thermal silicon dioxide instead of silicon nitride as the material of the mask for n ^?- and p ^?-wells, and employs an improved doping procedure for the wells. The new process is shown to decrease considerably the residual stress and defect density in the wafer. Its advantages over the standard process are supported by a two-dimensional computer simulation with Silvaco’s SSUPREM4.     

Formation of thermal donors in SIMOX material

Thermal oxygen donor generation in SIMOX material formed in Czochralski (CZ) and oxygen free float zone (FZ) silicon was investigated by Hall and photoluminescence techniques. It was determined that residual interstitial oxygen was introduced to silicon by the SIMOX buried oxide formation process thus increasing the possibility of thermal donor creation. Significantly, thermal donor generation was identified and localized to the top silicon region in FZ material. The detected concentration of residual oxygen was on the order of 5 × 10¹³ cm^-3 and is negligible when compared to the intrinsic oxygen concentration of the starting CZ bulk material.     

Characterization of the thermal conductivity of insulating thin films by scanning thermal microscopy

This paper reports on the abilities of a Scanning Thermal Microscopy (SThM) method to characterize the thermal conductivity of insulating materials and thin films used in microelectronics and microsystems. It gives a review of the previous works on the subject and gives new results allowing showing the performance of a new method proposed for reducing the thermal conductivity of meso-porous silicon by swift heavy ion irradiation. Meso-porous silicon samples were prepared by anodisation of silicon wafers and underwent irradiation by 845 MeV ²⁰⁸Pb ions, with fluences of 4×10¹¹ and 7×10¹¹ cm⁻². Thermal measurements show that irradiation reduced thermal conductivity by a factor of up to 2.     

Ultralow Thermal Conductivity of Single‐Crystalline Porous Silicon Nanowires

Porous materials provide a large surface‐to‐volume ratio, thereby providing a knob to alter fundamental properties in unprecedented ways. In thermal transport, porous nanomaterials can reduce thermal conductivity by not only enhancing phonon scattering from the boundaries of the pores and therefore decreasing the phonon mean free path, but also by reducing the phonon group velocity. Herein, a structure–property relationship is established by measuring the porosity and thermal conductivity of individual electrolessly etched single‐crystalline silicon nanowires using a novel electron‐beam heating technique. Such porous silicon nanowires exhibit extremely low diffusive thermal conductivity (as low as 0.33 W m^?1 K^?1 at 300 K for 43% porosity), even lower than that of amorphous silicon. The origin of such ultralow thermal conductivity is understood as a reduction in the phonon group velocity, experimentally verified by measuring the Young's modulus, as well as the smallest structural size ever reported in crystalline silicon (<5 nm). Molecular dynamics simulations support the observation of a drastic reduction in thermal conductivity of silicon nanowires as a function of porosity. Such porous materials provide an intriguing platform to tune phonon transport, which can be useful in the design of functional materials toward electronics and nanoelectromechanical systems.     

Finite element analysis and analytical simulations of Suspended Gate-FET for ultra-low power inverters

This paper proposes, the investigation of the Suspended Gate Field-Effect Transistor (SG-FET) small-slope switch based on a hybrid numerical simulation approach combining ANSYS^TM Multiphysics and ISE-DESSIS^TM in a self-consistent system. The proposed numerical simulations uniquely enable the investigation of the behavior and the physics of complex micro-electro-mechanical/solid-state devices, such as the SG-FET. Abrupt switching as well as the effect of trapped charges in the gate dielectric are demonstrated. The numerical data serve to calibrate an analytical EKV-based SG-FET model, which is then used to design and originally simulate a sub-micron (90 nm) scaled SG-FET complementary inverter. It is shown that, due to abrupt switching in the subthreshold region and electro-mechanical hysteresis, the SG-FET inverter could deliver a significant power saving (1–2 decades reduction of inverter peak current and practically no leakage power) compared to traditional CMOS inverter.     

Electro-thermal characterization and simulation of integrated multi-trenched XtreMOSTM power devices

This paper presents a new methodology to characterize and simulate the electro-thermal aspects of packaged power drivers using multi-trenched XtreMOS^TM devices. Electrical device data is collected by pulsed and DC measurements. Thermal data is collected through on-chip sensors and through a full surface high resolution transient interferometric mapping (TIM). For the first time a data driven segmented electro-thermal transient model is proposed to accurately describe the thermal profile behavior for the mutli-trenched devices. Further investigations of the thermal heating impact on the driver due to the low thermal conductivity of the trenches (SiO₂) have been carried out. The results of the investigations have been discussed for two different gate to source (VGS) bias conditions: VGS below the temperature compensation point (TCP), which is a bias condition that might lead to a thermal runaway, and VGS above TCP.     

Polycrystalline silicon solar cells on metallurgical silicon substrates

The use of a polycrystalline silicon p-n junction structure deposited on low-cost substrates is a promising approach for the fabrication of low-cost solar cells. Metallurgical-grade silicon, with a purity of about 98% and a cost of about $1/kg, was cast into plates in a boron nitride container and used as substrates for the deposition of solar cell structures. The substrates were polycrystalline with millimeter size crystallites. Solar cells of the configurations n>⁺-silicon/p-silicon/metallurgical silicon and n⁺-silicon/p⁺-silicon/metallurgical silicon were prepared by the thermal decomposition of silane and the thermal reduction of trichlorosilane containing appropriate dopants. The AMO efficiencies of n⁺-silicon/p-silicon/metallurgical silicon solar cells were up to 2.8% (with no anti-reflection coatings) and were limited by the grain boundaries in the p-layer. The grain boundary effects were reduced by increasing the dopant concentration in the p-layer, and AMO efficiencies of about 3.5% were obtained from n⁺-silicon/p⁺-silicon/metallurgi silicon solar cells.     

Textured silicon surface passivation by high‐rate expanding thermal plasma deposited SiN and thermal SiO2/SiN stacks for crystalline silicon solar cells

Expanding thermal plasma (ETP) deposited silicon nitride (SiN) with optical properties suited for the use as antireflection coating (ARC) on silicon solar cells has been used as passivation layer on textured monocrystalline silicon wafers. The surface passivation behavior of these high‐rate (>5 nm/s) deposited SiN films has been investigated for single layer passivation schemes and for thermal SiO₂/SiN stack systems before and after a thermal treatment that is normally used for contact‐firing. It is shown that as‐deposited ETP SiN used as a single passivation layer almost matches the performance of a thermal oxide. Furthermore, the SiN passivation behavior improves after a contact‐firing step, while the thermal oxide passivation degrades which makes ETP SiN a better alternative for single passivation layer schemes in combination with a contact‐firing step. Moreover, using the ETP SiN as a part of a thermal SiO₂/SiN stack proves to be the best alternative by realizing very low dark saturation current densities of <20 fA/cm² on textured solar‐grade FZ silicon wafers and this is further improved to <10 fA/cm² after the anneal step. Optical and electrical film characterizations have also been carried out on these SiN layers in order to study the behavior of the SiN before and after the thermal treatment. Copyright © 2008 John Wiley & Sons, Ltd.     

Electron thermal emission rates of nickel centers in silicon

The majority carrier thermal emission rates of nickel levels in the depletion region of reverse biased silicon p⁺ nn⁺ junctions have been investigated using the admittance spectroscopy technique. We have found two levels associated with nickel in n-type silicon. The “thermal activation energies” have values of E_C − 360 ± 10 meV and E_C − 570 ± 10 meV.     

Thermal and mechanical separations of silicon layers from hydrogen pattern-implanted wafers

A silicon layer was successfully transferred from a hydrogen pattern-implanted wafer to another by a thermal or mechanical cleavage process. The first wafer was masked with various patterns of 2.3 micron-thick poly-silicon, and was implanted at a hydrogen dose of 4,5, or 8 10¹⁶ cm⁻² with an energy of 150 keV or 180 KeV. After etching off the implantation mask, the wafer was bonded to a thermally grown oxide wafer face-to-face by low-temperature direct bonding. The bonded pair was then either heated (thermally) or bent (mechanically) until hydrogen-induced silicon layer cleavage occurred, resulting in the silicon layer transfer from the implanted wafer to the other. In this experiment, it was demonstrated that mechanical cleavage can overcome the fractional implantation area limination of thermal cleavage.     

A silicon carbide LOCOS process using enhanced thermal oxidation by argon implantation

A process is described for creating local oxidation of silicon structure (LOCOS) structures in silicon carbide using enhanced thermal oxidation by argon implantation. Thicker oxides were created in selective regions by using multiple energy argon implants at a dose of 1 × 10¹⁵ cm⁻² prior to thermal oxidation. Atomic force microscopy was used to analyze the fabricated LOCOS structure.     

Intentional thermal donor activation in magnetic Czochralski silicon

We have made a quantitative study about the thermal activation of thermal donors in high resistivity magnetic Czochralski silicon. The thermal donor activation has been performed through a thermal treatment at 430 °C up to a total time of 80 min. The space charge density after each annealing step has been extracted from capacitance–voltage measurements. If the starting material is boron-doped p-type high-resistivity Czochralski silicon, the thermal donor generation process can be utilized in order to produce p⁺/n⁻/n⁺ detectors. The last thermal process step, i.e. the sintering of aluminum, is intentionally carried out at the temperature where thermal donors are created. According to our results, we have improved the previously reported model of the thermal donor generation.     

The forward voltage technique to measure junction temperatures of ac operating triacs

The forward voltage drop Vfof an ac operating triac can be employed to indicate its junction temperature. The Vf, for a constant test current, is shown to decrease linearly with increasing temperature over the range of 20 to 125°C with measured slopes between -1.4 to -1.6 mV/°C. A sampling current must be used at the end of an applied power pulse and the cooling of the triac which takes place during the delay in measurement is taken into account by an extrapolation procedure. The indicated temperature using the Vfmethod is in excellent agreement With the maximum temperature measured with an infrared microradiometer at the surface of the active region of the triac. The Vftechnique requires a special power test circuit which is described. This technique provides an accurate indication of the maximum operating temperature and requires calibration of only a few triacs. Triac manufacturers can use the Vftechnique to accurately measure the thermal performance of their triacs and to screen production to eliminate marginal devices.     

Formation and properties of the buried isolating silicon-dioxide layer in double-layer “porous silicon-on-insulator” structures

The oxidation of mesoporous silicon in a double-layer “macroporous silicon–mesoporous silicon” structure is studied. The morphology and dielectric properties of the buried insulating layer are investigated using electron microscopy, ellipsometry, and electrical measurements. Specific defects (so-called spikes) are revealed between the oxidized macropore walls in macroporous silicon and the oxidation crossing fronts in mesoporous silicon. It is found that, at an initial porosity of mesoporous silicon of 60%, three-stage thermal oxidation leads to the formation of buried silicon-dioxide layers with an electric-field breakdown strength of E _br ~ 10⁴–10⁵ V/cm. Multilayered “porous silicon-on-insulator” structures are shown to be promising for integrated chemical micro- and nanosensors.     

高功率多注速调管TM310模圆柱形谐振腔杂模抑制方法

该文针对TM₃₁₀模(主模)圆柱形谐振腔提出了一种新的杂模抑制方法。为抑制与主模相邻的低次杂模TM₀₂₀,采用在谐振腔中放置接收振子天线的方法,并推导了放入接收振子天线后,模式频率变化量的表达式。由此发现：模式频率变化量仅依赖于该模式在接收振子天线处的电场强度,而与其磁场无关;通过适当调整接收振子的位置,可使主模和TM₀₂₀ 模具有不同的频率变化量,从而能增大模式之间的频率间隔,避免TM₀₂₀ 模对主模的干扰。另外,为抑制与主模相邻的杂模TM⁺₃₁₀,采用了在谐振腔中放置短路杆阵的方法。利用CST-MWS软件对X波段此类谐振腔进行了模拟计算,验证了该方法的有效性。     

Assembly-level reliability of flex-substrate BGA, elastomer-on-flex packages and 0.5 mm pitch partial array packages

The assembly-level reliability of the 0.8 mm pitch flex-substrate BGA, 0.65 mm pitch elastomer-on-flex package, and 0.5 mm pitch partial array BGA has been characterized in thermal fatigue, out-of-plane deformation, low frequency repeated bending, and thermal aging. Non-linear finite element models have been used to identify and predict the dominant failure mechanisms and identify the assembly parameters which have a dominant impact on reliability. The model predictions have been verified with accelerated test data. The results have been bench marked against other technologies including 1.5 mm pitch OMPAC^TM and 1 mm pitch, 196 I/O Glob-top BGA.     

Architectured Materials to Improve the Reliability of Power Electronics Modules: Substrate and Lead-Free Solder

Power electronics modules (>100 A, >500 V) are essential components for the development of electrical and hybrid vehicles. These modules are formed from silicon chips (transistors and diodes) assembled on copper substrates by soldering. Owing to the fact that the assembly is heterogeneous, and because of thermal gradients, shear stresses are generated in the solders and cause premature damage to such electronics modules. This work focuses on architectured materials for the substrate and on lead-free solders to reduce the mechanical effects of differential expansion, improve the reliability of the assembly, and achieve a suitable operating temperature (<175°C). These materials are composites whose thermomechanical properties have been optimized by numerical simulation and validated experimentally. The substrates have good thermal conductivity (>280 W m^?1 K^?1) and a macroscopic coefficient of thermal expansion intermediate between those of Cu and Si, as well as limited structural evolution in service conditions. An approach combining design, optimization, and manufacturing of new materials has been followed in this study, leading to improved thermal cycling behavior of the component.     

Applying simulation to network planning and design issues

What is simulation good for and how do you use it? Simulation can be applied to a wide variety of network planning and design issues. This paper describes a number of such issues of interest, suggesting the most relevant simulated performance and the benefits derived from a simulated network performance analysis and then demonstrates the simulation technology through a detailed case study using Plan Net^TM.