First life-test results on planar p-i-n InGaAs/InP photodiodes passivated with SiO2or SiNx+SiO2or SiNxlayers

This letter reports the results obtained with planar p-in photodiodes realized using three different passivating coatings and compares their performances and long-term stability in view of highly reliable component development.     

Silicon-rich SiO2and thermal SiO2dual dielectric for yield improvement and high capacitance

The use of silicon-rich SiO2and thermal SiO2dual dielectric in memory capacitors and FET's is investigated. It is shown that the silicon-rich layer was conductive and introduced only a small decrease in the series capacitance of the dual dielectric. Consequently, the capacitance of the dual dielectric is close to that of the thermal oxide only. The response time of the silicon-rich layer is measured by using FET response time and is shown to be in the nanosecond range. With this fast response time, it is possible to use the dual dielectric in memory and logic circuits. Another advantage of the dual dielectric is the very high yield due to the field screening of the silicon-rich layer to any nonuniformities in the thermal oxide or at the SiO2-contact interface. This dual dielectric has the promise of high yield and high capacitance for future VLSI circuits.     

A damage-free perfect planarization method using bias-sputtered SiO2

A novel bias-sputtered SiO2deposition process, which is suitable for depositing an interlevel insulator of an Al multilevel interconnection of submicrometer feature size, has been achieved. This process consists of damage-free technology and a perfect planarization method. It was found that during the bias-sputter deposition, damage was introduced into the gate oxides of MOS devices due to secondary X-rays generated by electrons coming from the sputter target, but that the presence of a grid electrode to absorb these electrons was quite effective to reduce damage introduction to an acceptable degree for practical use. Also, using a two-step bias-sputter deposition and an etch-back technique, a perfect planarization of bias-sputtered SiO2films was achieved.     

Buckling of thermally-grown SiO2thin films

The difference in thermal expansion causes compression in SiO2thermally grown on Si wafers. Unsupported windows of SiO2buckle if the oxide thickness/window width ratio (t/w) is too small. This correspondence presents the experimentally determined t/w ratio for stable films.     

Observations on phosphorus stabilized SiO2films

Two experiments were performed with phosphorus stabilized and untreated silicon dioxide films on silicon substrates. In the first, the interaction of phosphorus and boron was studied; it was found that diffusion of boron over a phosphorus stabilized film destroyed its stabilization against ion drift effects at 400°C, but that diffusion of phosphorus over a boron diffused film resulted in a stabilized oxide. In the second experiment, a slowly varying voltage was applied at 600°C to a silicon-silicon dioxide-gold structure and the current through the oxide film was recorded. Both phosphorus stabilized and untreated silicon dioxide films show rectifying characteristics, the more highly conducting direction being that with the silicon negative. In the case of the untreated film, a large peak of current is superimposed on this characteristic at -2.5 volts. This peak is absent in phosphorus stabilized films. Discharge currents equivalent to the charging currents are not observed on removing voltage from the specimen, as they are at 400°C. Five distinguishable types of charge transfer in silicon dioxide films are tabulated, and compared with those described in the literature as occurring in crystal quartz.     

Characteristics of MOSFET prepared on Si/MgO.Al2O3/SiO2/Si structure

A new silicon on insulator (SOI) wafer with epitaxial-Si/ epitaxial-MgO.Al2O3(0.1 µm)/SiO2(0.5 µm)/     

A planarized SiO2interlayer dielectric with bias-CVD

A Bias-CVD^TMprocess has been developed for depositing planarized silicon dioxide films. The process uses, in addition to PECVD deposition, an argon ion etch for planarization. A distinguishing feature of this process is the use of a unique sequence of depositions and etching to control contour and topography, eliminate keyholing, and reduce pinhole density. By varying this Sequence, the film topography can range from conformal to fully planarized. A cold-wall low-pressure CVD system with an eight-wafer batch and 13.56-MHz RF capability was used in this study. Because of the chamber geometry, a dc bias is induced in the wafer support during the RF plasma processing. This bias, typically a few hundred volts, provides the accelerating field for the ion etching of the film. It is the anisotropy of this etch that makes planarization possible. The film has the density and index of refraction of thermally grown oxide. The Si to O ratio is 1 to 1.9 with 8-percent nitrogen and 0.1-percent argon, by RBS. SIMS analysis shows no trace of heavy metals. The effect of process parameters has been characterized. Dynamic RAM's deposited with the sloped film show normal yield and electrical properties; there is no evidence of radiation damage.     

Hot-electron trapping in thin LPCVD SiO2dielectrics

The electron-trapping and surface-state generation characteristics of thin LPCVD SiO2dielectrics have been studied using avalanche hot-electron injection. Layered structures of thermal and LPCVD oxide have been examined as a function of anneal time and temperature. After a 1000°C anneal, bulk trapping in the LPCVD oxide was reduced to levels comparable to those in a high-quality dry thermal oxide. Sensitivity to remaining traps was reduced by the presence of a thermal oxide layer on the semiconductor surface. After a post-deposition anneal (PDA), these layered surfaces demonstrated hot-electron performance equal to that of thermal oxide within measurable limits. Also, layered structures generally demonstrated better resistance to surface-state generation than thermal oxides alone. Since less chlorine is incorporated into the layered structures during fabrication, this result is consistent with a recent model identifying broken chlorine bonds as the origin of surface states.     

Proton and sodium transport in SiO2films

The results of an investigation into the relative roles of sodium and proton transport in silicon-dioxide films are presented. Tritium oxide (³H2O), tritiated ethanol, neutron activation, and sodium 22 tracer analyses are used to identify the mobile ions directly, and the results of these analyses are then directly correlated with the observed electrical behavior.     

Tapered windows in SiO2by ion implantation

The enhanced etch rate of ion damaged SiO2has been used to controllably taper steps in thermally grown SiO2. A 50-keV Ar⁺implantation with a dose of 3 × 10¹³/cm²produces a uniform taper of 35-45° with no vertical step at the top edge of the window. These results are observed by viewing the sample on edge with a scanning electron microscope (SEM). The taper angle of the oxide varies from near vertical (90°) at a dose of 4 × 10¹²/cm²to very small angles at large dosages.     

Dielectric relaxation in thermally grown SiO2films

An extensive investigation of the dielectric properties of thermally grown silicon dioxide films was performed in the temperature range from 400°C to 525°C. Principally, the variation of dissipation factor with frequency was observed at various applied peak fields and oxide thicknesses. In the temperature and frequency domain investigated, a large peak in the dissipation factor occurred. This peak corresponded to a massive capacitance dispersion with accompanying peaking of the loss factor at low frequencies. The phenomenon was apparently an ionic space-charge polarization. Theoretical developments based on this model were verified by experiment. The activation energy for the relaxation time was 10.1 ± 0.4 kcal/mole. Examination of the oxide thickness dependence indicated that the carriers were not uniformly distributed initially, but a fixed number was present at a particular temperature and this number was independent of thickness. Further investigation led to the conclusion that a reaction between the metal electrode and the SiO2produced positively charged oxygen vacancies which migrated through the oxide under the influence of an electric field. A mechanism for the production and migration of these vacancies is proposed which complies with the low activation energy as well as the observed temperature and electrode dependence.     

Low-loss optical waveguides with pure fused SiO2cores

Optical waveguide fibers have been produced by a chemical-vapor-deposition technique with optical attenuations as low as 1.1 dB/km at 1.02 µm. The application of this technique to the fabrication of graded index fibers with losses below 2 dB/km is also reported.     

Tapered windows in phosphorus-doped SiO2by ion implantation

Phosphorus-doped SiO2is frequently used as a dielectric coating in silicon integrated circuits. It is important that windows in this dielectric have sufficiently tapered walls so that the subsequent metallization has good step coverage. It is shown here that tapered windows can be made in both Nitrox-deposited ∼ 1-percent phosphorus-doped SiO2and Silox-deposited ∼ 7-percent phosphorus-doped SiO2as well as undoped SiO2by an ion implantation which produces a thin damaged layer at the top of the oxide. The damaged layer etches at a faster rate than the undamaged oxide. This fast-etching layer undercuts the photoresist which serves as the etching mask and results in window walls having slopes in the range of 30-40° with respect to the wafer surface. Tapering windows by ion implantation is a dependable process that gives reproducible results without having to rely on the art of photoresist liftoff methods.     

A new MOS integrated circuit fabrication using Si3N4film self-alignment liftoff techniques

A new MOS integrated circuits fabrication process that realizes self-aligned source and drain contact hole formation is described. This process utilizes a Si3N4film self-alignment liftoff technique for selective oxidation (SALTS). Devices are fabricated using SALTS. It is shown that device packing density and speed show a 30-percent or more improvement over the conventional method at the same minimum lithographic feature size. It is also shown that Si3N4film deposited using the sputtering method does not cause any degradation in device characteristics.     

Thermal nitridation of Si and SiO2for VLSI

This paper presents an extensive review of our work on thermal nitridation of Si and SiO2. High-quality ultrathin films of silicon nitride and nitrided-oxide (nitroxide) have been thermally grown in ammonia atmosphere in a cold-wall RF-heated reactor and in a lamp-heated system. The growth kinetics and their dependence on processing time and temperature have been studied from very short to long nitridation times. The kinetics of thermal nitridation of SiO2in ammonia ambient have also been studied. In nitroxide, nitrogen-rich layers are formed at the surface and interface at a very early stage of the nitridation. Then the nitridation reaction mainly goes on in the bulk region with the surface and near interface nitrogen content remaining fairly constant. Our results also indicate the formation of an oxygen-rich layer at the interface underneath the nitrogen-rich layer whose thickness increases slowly with nitridation time. The nitride and nitroxide films were analyzed using Auger electron spectroscopy, grazing angle Rutherford backscattering, and etch rate measurements. MIS devices were fabricated using these films as gate insulators and were electrically characterized usingI - V, C - V, time-dependent breakdown, trapping, and dielectric breakdown techniques. Breakdown, conduction, andC-Vmeasurements on metal-insulator semiconductor (MIS) structures fabricated with these films show that very thin thermal silicon nitride and nitroxide films can be used as gate dielectrics for future highly scaled-down VLSI devices. The electrical characterization results also indicate extremely low trapping in the nitride films. The reliability of ultrathin nitride was observed to be far superior to SiO2and nitroxide due to its much less trapping. Studies show that the interface transition from nitride to silicon is almost abrupt and the morphology and roughness of the interface are comparable to the SiO2-Si interfaces.     

Hole trapping and breakdown in thin SiO2

The field dependence of the hole generation rate, also known as the impact ionization coefficient α, in thin SiO2(< 20 nm) was characterized by measuring the negative flat-band shift due to hole trapping. In thicker oxides,alpha = alpha_{0}e^{-H/E}where H = 78 MV/cm for electric fields ranging from 7 to 14 MV/cm, which covers the field range from the onset of significant Fowler-Nordheim current to instant breakdown. The similar field dependences of α and charge-to-breakdown supports the model that hole generation and trapping leads to oxide wearout. Because of the fact that positive charge generation is observed for oxide voltage well below the SiO2bandgap, we propose that the generated holes arise from transition between band tails in the amorphous SiO2. It is also observed that α decreases rapidly when the applied oxide voltage is very low; thus α is a function of both oxide field and voltage in general. This suggests that ultra-thin oxide with low operating voltages might be a good candidate for high endurance E²PROM devices at very low oxide field.     

Laser-induced breakdown in crystalline and amorphous SiO2

The 1.06 μm breakdown thresholds of crystalline and amorphous SiO2were compared. These materials showed dependences of the breakdown threshold on the focal volume which are consistent with a multiphoton-assisted electron avalanche damage mechanism.     

Accelerated testing of time-dependent breakdown of SiO2

Electric-field acceleration factor β is the slope of thelog (t_{BD})versus Eoxcurve, where tBDis the time to breakdown at oxide field Eox. We report that β is not a constant but proportional toEmin{ox}max{-2}. This is the main cause of the wide divergence of β values reported in the literature. The reported oxide thickness dependence of β is believed to be a result of the higher electron trap densities in thicker oxides. Oxide lifetime extrapolation usinglog (t_{BD}), or better,log (Q_{BD})against1/E_{ox}plots is more accurate and has a theoretical basis. Highly accelerated oxide testing appears to be feasible especially for very thin oxides.     

Unusual phenomena in CVD SiO2under sustained electron bombardment

SEM observations of passivating oxide after roughly 100 h of exposure to 10-12-keV, 1-10-mA/cm²electrons disclosed several unexpected phenomena, including smoothing and removal of the surface, perforation of the layer, and the growth of filaments at the edges of the illuminated regions. Possible explanations for the above are discussed.     

Effect of thermally nitrided SiO2thickness on MIS characteristics

The flatband voltage of metal-insulator-semiconductor (MIS) structures with thermally nitrided SiO2(nitroxide) insulators has been studied as a function of the nitroxide thickness in the range of 10-60 nm, for different nitridation conditions. The most striking result is that 10-nm nitroxide films are far less susceptible than thicker ones to the degradation of the electrical properties of the starting SiO2films induced by nitridation, as revealed by a negative shift of the flatband voltage. For nitridation cycles at relatively low temperatures (900° 120 min or 1000°C 60 min) the shift in the 10-nm films is practically negligible.