Trapped-electron and generated interface-trap effects in hot-electron-induced MOSFET degradation

A new experimental method is proposed to distinguish the electron-trapping effect in the gate oxide from the interface-trap generation effect in hot-electron-induced nMOSFET degradation. In this method, by selecting the appropriate bias conditions, hot electrons and/ or hot holes are intentionally injected into the oxide region above the channel outside the drain layer, which affects MOSFET characteristics such as threshold voltage and transconductance. The negative charges of electrons trapped in the oxide during hot-electron injection are completely compensated for by the positive charges of subsequently injected and trapped holes, and the trapped electron effect in the degradation is eliminated. Using this method, the causes for hot-electron-induced transconductance degradation (Δgm/gm) are analyzed. As the degradation increases, the trapped-electron effect decreases, and the generated interface-trap effect increases. The relationship of (Δgm/gm)_{it}, =A(Δgm/gm) --Bis obtained, where (Δgm/gm)_{it} is gmdegradation due to generated interface-traps, andAandBare fixed numbers. Furthermore φ_{it}/λ (the ratio of the critical value in hot-electron energy for interface-trap generation to the mean free path of hot electrons in Si) is experimentally obtained to be 5.7 × 10⁶eV/cm. Using λ = 9.2 nm [1], a value of φ_{it} = 5.2 eV is derived.     

Theoretical characterization and high-speed performance evaluation of GaAs IGFET's

Fundamental characterization of GaAs IGFET's is carried out utilizing two-dimensional numerical analysis, and high-speed operation performances are evaluated. Two-dimensional analysis shows that the operational mechanism of GaAs IGFET's is very similar to that of MESFET's, i.e., channel depletion-type operation due to control of the gate depletion layer. But normally-off-type current-voltage characteristics can be easily realized because of positive VFBfor GaAs dioxide films. Electrical characteristics are strongly dependent on the oxide film. Although the transconductance gmdeteriorates compared to MESFET's due to the potential drop through the oxide layer, the deterioration in gmis found to be small for oxide films with large dielectric constant εOX. Furthermore, it is clarified that cutoff frequency fTfor IGFET's is greater than for MESFET's because the input capacitance Cgsin depletion-type device operation is found to be much smaller than for MESFET's. In additional, a high-voltage swing is applicable in device operation because of the IG structure, and higher gm, is achieved by supplying high gate biases. These features give GaAs IGFET's wide application fields as high-performance devices and make them superior to MESFET's, especially in digital circuits.     

Device characterization of p-channel AlGaAs/GaAs MIS-like heterostructure FET's

p-channel AlGaAs/GaAs MIS-like heterostructure FET's (p-MIS HFET's) are characterized concerning their gate-source leakage current. Device performance is confirmed to improve approximately inversely to layer thickness dtbetween the channel and metal gate, at low gate voltages. A high transconductance gmof 110 ms. mm-1is obtained at 77 K by reducing dtto 20 nm. Maximum transconductance is limited by gate-source leakage current Igs. Igsis governed mainly by the leakage current through the ion-implanted gate edge and is reduced by decreasing the dose level of ion-implantation at the gate edge to 2 × 10¹³cm^-2. The contact resistance is reduced to about 0.1 ω. mm by ion implantation into the ohmic contact region to a dose of 2 × 10¹⁴cm^-2. Calculations indicate that, by reducing Igsand the gate-source resistance to 1 ω. mm with the lightly doped drain (LDD) structure, gmaround 200 mS. mm^-1at 300 K and 300 mS. mm^-1at 77 k are achievable with a 1-µm gate structure.     

A GaAs 1-kbit static RAM with a shallow recessed-gate structure FET

A novel GaAs FET structure, the shallow recessed-gate structure, has been proposed and applied to a 1-kbit static RAM. In order to decrease the source resistance Rsand gate capacitance Cg, the shallow n⁺implanted layer was formed between the gate and source/drain region; then the gate region was slightly recessed. This FET has a high transconductance gm, low source resistance Rs, small gate capacitance Cg, and small deviation of threshold voltagepart V_{th}, and thus is suitable for high-speed GaAs LSI's. A 1-kbit static RAM has been designed and fabricated applying this FET structure and an access time of 3.8 ns with 38- mW power dissipation has been obtained.     

MOS transistors with anodically formed metal oxides as gate insulators

A new type of MOS field effect transistor has been fabricated utilizing anodically formed valve metal oxide films (AMOS). These anodic oxide films such as hafnium dioxide (HfMOS) offer the advantage of producing high dielectric constant insulators in the channel in order to improve the transconductance (gm) and voltage gain (µA= Cin/Cfb) of the device.     

High-transconductance p-channel modulation-doped AlGaAs/GaAs heterostructure FET's

p-channel modulation-doped AlGaAs-GaAs heterostructure FET's (p-HFET's) employing two-dimensional hole gas (2DHG) were fabricated under various geometrical device parameter conditions. The p-HFET characteristics were measured at 300 and 77 K for the following three device-parameter ranges: the gate length Lg(1-320 µm), the gate-source distance Lgs(0.5-5 µm), and the layer thickness dt(35-58 nm) of AlGaAs beneath the gate. Based on the obtained results, a high-performance enhancement-mode p-HFET was fabricated with the following parameters:L_{g} = 1µm,L_{gs} = 0.5µm, andd_{t} = 35nm. The achieved extrinsic transconductance gmwas 75 mS . mm^-1at 77 K. This experimental result indicates that a gmgreater than 200 mS . mm^-1at 77 K Can be obtained in 1-µm gate p-HFET devices.     

Double heterostructure Ga0.47In0.53As MESFETs with submicron gates

MESFETs with GA0.47In0.53As active channel grown by MBE on InP substrates were successfully fabricated. Thin layers of MBE grown Al0.48In0.52As seperated both the single crystal aluminum gate from the active channel and the active channel from the InP substrate so raising the Schottky barrier height of the gate and confining the electrons to the channel. The MESFETs with 0.6µm long gates and gate-to-source separations of 0.8 um exhibited an average gmof 135 mS mm^-1of gate width for Vds= 2V and Vg= 0. This is higher than that reported for GaAs MESFETs with a similar geometry in spite of the intermediate layer between the gate metal and the active layer.     

Gold-germanium-based ohmic contacts to the two-dimensional electron gas at selectively doped semiconductor heterointerfaces

Results of a study of ohmic contacts to the two-dimensional electron gas (2DEG) at N⁺-n III-V semiconductor heterointerfaces are presented. In a comparison of alloyed metallizations based on the Au-27at. %Ge eutectic system, the addition of Ni and the method of deposition were found to have the largest effects in lowering the contact resistance. The Ni-Ge-Au Ohmic contact reproducibly gives a (width-normalized) contact resistance of less than 0.2 Ω . mm, which is adequate for MESFET applications using these structures. MESFET's fabricated with (Al,Ga) As and (Al,In,Ga) As heterojunction 2DEG channels and Ni-Ge-Au contacts have source-drain resistances (Rsd), which decrease dramatically at low temperature as a result of the mobility enhancement in the 2DEG channel and the small contribution of contact resistances. The transconductance (gm) of the device thus more nearly approaches its high intrinsic value. At 77 K, the best (Al,Ga) As FET's had Rsd= 0.69 Ω . mm and gm= 309 mS/mm with gate lengths of 1.5 µm and a source-drain spacing of 9 µm. A microwave gain of 11 dB at 6.4 GHz has been obtained at room temperature for these devices.     

A dc and microwave comparison of GaAs MESFET's on GaAs and Si substrates

In order to assess GaAs on Si technology, we have made a performance comparison of GaAs MESFET's grown and fabricated on Si and GaAs substrates under identical conditions and report the first microwave results. The GaAs MESFET's on Si with 1.2-µm gate length (290-µm width) exhibited transconductances (gm) of 180 mS/mm with good saturation and pinchoff whereas their counterparts on GaAs substrates exhibited gmof 170 mS/mm. A current gain cut-off frequency of 13.5 GHz was obtained, which compares with 12.9 GHz observed in similar-geometry GaAs MESFET's on GaAs substrates. The other circuit parameters determined from S-parameter measurements up to 18 GHz showed that whether the substrate is Si or GaAs does not seem to make a difference. Additionally, the microwave performance of these devices was about the same as that obtained in devices with identical geometry fabricated at Tektronix on GaAs substrates. The side-gating effect has also been measured in both types of devices with less than 10-percent decrease in drain current when 5 V is applied to a pad situated 5 µm away from the source. The magnitude of the sidegating effect was identical to within experimental determination for all side-gate biases in the studied range of 0 to -5 V. The light sensitivity of this effect was also very small with a change in drain current of less that 1 percent between dark and light conditions for a side gate bias of -5 V and a spacing of 5 µm. Carrier saturation velocity depth profiles showed that for both MESFET's on GaAs and Si substrates, the velocity was constant at 1.5 × 10⁷cm/s to within 100-150 Å of the active layer-buffer layer interface.     

Vertical FET's in GaAs

Vertical FET's in GaAlAs material systems have been fabricated. The present structure makes possible extremely short (less than 1000-Å) channel devices which are beyond the reach of optical lithographic processes. Devices with transconductance gmas high as 280 mS/mm have been obtained.     

Noise in high-gain transistors and its application to the measurement of certain transistor parameters

Noise performance of a high-gain transistor is presented. It is shown that both burst noise and flicker noise in high-gain transistors are not as important as those in low-gain units. At very small biases, less than 10 µA for the given transistor, the limiting noise of the transistor is dominated by the shot noise. In the higher bias region the thermal noise of the base resistance is the dominant noise of the transistor. It is also demonstrated that from noise measurement the base resistance rb'b, the transconductance gm, and the small signal common emitter-current gain β can be accurately determined.     

Wide-band amplifiers for television

The maximum uniform amplification that can be secured over a wide frequency band by means of a single vacuum tube is much greater than that of the usual simple circuits. It can be secured by either of two arrangements, one using an individual filter coupling each tube to the next, and the other using degenerative feedback in each stage to make the stage behave as a section of a confluent filter. In either case, the shunt capacitance on each side of each tube is included in an individual full-shunt arm of a band-pass or low-pass filter. One end of each interstage filter, or of each filter including one or more feedback stages, is extended to a dead-end termination with resistance approximately matching the image impedance. The other end is terminated at one of the tubes in a full-shunt arm, where the filter presents the maximum uniform impedance that can be built up across the tube capacitance. These concepts in terms of wave filters lead to practical wide-band circuits adapted to meet any given requirements. The following general formula is shown to express the maximum uniform amplification that can be secured in one tube: A = gm/πfw√CgCpin which A is the voltage ratio between input and output circuits of equal impedance, gmis the transconductance of the tube, Cgand Cpare the grid and plate capacitance of the tube, and fwis the width of the frequency band.     

Trigger sensitivity of transferred electron logic devices

An analysis of the Schottky-barrier gate transferred electron logic devices (TELD's) is developed which gives the trigger sensitivity in terms of the channel pinchoff voltage, normalized channel depletion width under the gate, device subthreshold transconductance, and the value of the external load resistor. The results presented show that the trigger sensitivity increases with increase in doping density, decrease in channel pinchoff voltage, and decrease in gate reverse bias. Furthermore, for the same material parameters (doping density, channel thickness, etc.) device subthreshold transconductance (gm) improves the trigger sensitivity by a factor (1 + gmRL). Device designs based on this analysis should result in improved device performance.     

A complementary DMOS-VMOS IC structure

A new complementary MOS structure has been fabricated consisting of a p-channel DMOS transistor and an n-channel double-diffused VMOS transistor. The transconductance of each transistor was between 0.85-0.98 of the theoretical gm. The threshold voltages have been adjusted by either ion implantation or by adjusting the diffusion profiles. The inverter operation is similar to that of standard CMOS.     

A high aspect ratio design approach to millimeter-wave HEMT structures

In MESFET and HEMT structures as the gate length is reduced below 0.5 µm in an attempt to achieve amplification at highest possible frequencies, it is essential that the depletion depth under the gate be also reduced in order to preserve a high aspect ratio that ensures a high device voltage gain factor (gm/g0) and a reasonable value of stable power gain at high frequencies. Results based on this design approach indicate that an n-A1GaAs/GaAs HEMT structure with 0.25-µm gate length could provide stable power gain in excess of 6 dB at the unity current gain frequency of 92.4 GHz, and for an aspect ratio of ten it is difficult to reduce the gate length below 0.25 µm.     

Electron-beam fabrication of GaAs low-noise MESFET's using a new trilayer resist technique

A LO/HI/LO resist system has been developed to produce sub-half-micrometer T-shaped cross section metal lines using e-beam lithography. The system provides T-shaped resist cavities with undercut profiles. T-shaped metal lines as narrow as 0.15 µm have been produced. GaAs MESFET's with 0.25-µm T-shaped Ti/Pt/Au gates have also been fabricated on MBE wafers using this resist technique. Measured end-to, end 0.25-µm gate resistance was 80 ω/mm, dc transconductance gmas high as 300 mS/mm was observed. At 18 GHz, a noise figure as low as 1.4 dB with an associated gain of 7.9 dB has also been measured. This is the lowest noise figure ever reported for conventional GaAs MESFET's at this frequency. These superior results are mainly attributed to the high-quality MBE material and the advanced T-gate fabrication technique employing e-beam lithography.     

Improved MODFET performance through ion implantation in the gate region

AlxGa1-xAs/GaAs modulation-doped FET's (MODFET's) are reported which utilize for the first time a shallow low-dose p-type implantation under the gate region to improve the source-drain breakdown voltage, and the gate-channel forward turn-on and reverse breakdown voltages. Extremely low output conductances of less than 0.2 mS/mm are also obtained and the open-circuit dc voltage gains gm/gdexceed 250. Such improvements are important for achieving high RF power in microwave device applications, and have similarly significant implications for digital circuitry.     

Performance of a quarter-micrometer-gate ballistic electron HEMT

The electrical properties of a quarter-micrometer-gate HEMT have been studied by simulation and experiment. An IDSof 11 mA/50 µm, a gmof 500 mS/mm, and an fTof 110 GHz have been predicted by two-dimensional Monte Carlo simulation for certain conditions. The reasons underlying the high performance are discussed in terms of the electron dynamics in the device. A record room-temperature propagation delay time of 9.2 ps/gate at a power dissipation of 4.2 mW/ gate with the maximum transconductance of 400 mS/mm was obtained experimentally for a 0.28-µm-gate HEMT. Only a negligible short-channel effect was observed for reducing the gate length from 1.4 to 0.28 µm.     

Dependence of normally-off GaAs JFET performance on device structure

The relation between the performance of normally-off JFET's and the Si ion-implantation conditions used to form the channel layer was studied. Static and switching characteristics were investigated for JFET's with three kinds of channel layers; Si implanted at 130 keV to doses of 2,4, and 6 × 10¹²ions/cm². While higher doses gave better static characteristics [Ids, gm, and Ron], higher capacitance degraded the switching characteristics. The optimum parameters were determined for the high-speed switching JFET. With 2-µm gate length, the highest switching speed was 80 ps and the lowest power-delay product was 0.9 fJ. An improved structure satisfying a high-conductance and low-capacitance requirement was successfully fabricated and showed excellent performance for high-speed and low-power logic circuits; the minimum propagation delay was 45 ps and the minimum power-delay product was 3.8 fJ with a delay time of 83 ps.