Synergies of Electrochemical Metallization and Valance Change in All‐Inorganic Perovskite Quantum Dots for Resistive Switching

The in‐depth understanding of ions' generation and movement inside all‐inorganic perovskite quantum dots (CsPbBr₃ QDs), which may lead to a paradigm to break through the conventional von Neumann bottleneck, is strictly limited. Here, it is shown that formation and annihilation of metal conductive filaments and Br^? ion vacancy filaments driven by an external electric field and light irradiation can lead to pronounced resistive‐switching effects. Verified by field‐emission scanning electron microscopy as well as energy‐dispersive X‐ray spectroscopy analysis, the resistive switching behavior of CsPbBr₃ QD‐based photonic resistive random‐access memory (RRAM) is initiated by the electrochemical metallization and valance change. By coupling CsPbBr₃ QD‐based RRAM with a p‐channel transistor, the novel application of an RRAM–gate field‐effect transistor presenting analogous functions of flash memory is further demonstrated. These results may accelerate the technological deployment of all‐inorganic perovskite QD‐based photonic resistive memory for successful logic application.     

Towards the Development of Flexible Non‐Volatile Memories

Flexible non‐volatile memories have attracted tremendous attentions for data storage for future electronics application. From device perspective, the advantages of flexible memory devices include thin, lightweight, printable, foldable and stretchable. The flash memories, resistive random access memories (RRAM) and ferroelectric random access memory/ferroelectric field‐effect transistor memories (FeRAM/FeFET) are considered as promising candidates for next generation non‐volatile memory device. Here, we review the general background knowledge on device structure, working principle, materials, challenges and recent progress with the emphasis on the flexibility of above three categories of non‐volatile memories.     

Interface Engineering with MoS2–Pd Nanoparticles Hybrid Structure for a Low Voltage Resistive Switching Memory

Metal oxide‐based resistive random access memory (RRAM) has attracted a lot of attention for its scalability, temperature robustness, and potential to achieve machine learning. However, a thick oxide layer results in relatively high program voltage while a thin one causes large leakage current and a small window. Owing to these fundamental limitations, by optimizing the oxide layer itself a novel interface engineering idea is proposed to reduce the programming voltage, increase the uniformity and on/off ratio. According to this idea, a molybdenum disulfide (MoS₂)–palladium nanoparticles hybrid structure is used to engineer the oxide/electrode interface of hafnium oxide (HfO_x)‐based RRAM. Through its interface engineering, the set voltage can be greatly lowered (from ?3.5 to ?0.8 V) with better uniformity under a relatively thick HfO_x layer (≈15 nm), and a 30 times improvement of the memory window can be obtained. Moreover, due to the atomic thickness of MoS₂ film and high transmittance of ITO, the proposed RRAM exhibits high transparency in visible light. As the proposed interface‐engineering RRAM exhibits good transparency, low SET voltage, and a large resistive switching window, it has huge potential in data storage in transparent circuits and wearable electronics with relatively low supply voltage.     

Flexible Nonvolatile Transistor Memory with Solution‐Processed Transition Metal Dichalcogenides

Nonvolatile field‐effect transistor (FET) memories containing transition metal dichalcogenide (TMD) nanosheets have been recently developed with great interest by utilizing some of the intriguing photoelectronic properties of TMDs. The TMD nanosheets are, however, employed as semiconducting channels in most of the memories, and only a few works address their function as floating gates. Here, a floating‐gate organic‐FET memory with an all‐in‐one floating‐gate/tunneling layer of the solution‐processed TMD nanosheets is demonstrated. Molybdenum disulfide (MoS₂) is efficiently liquid‐exfoliated by amine‐terminated polystyrene with a controlled amount of MoS₂ nanosheets in an all‐in‐one floating‐gate/tunneling layer, allowing for systematic investigation of concentration‐dependent charge‐trapping and detrapping properties of MoS₂ nanosheets. At an optimized condition, the nonvolatile memory exhibits memory performances with an ON/OFF ratio greater than 10⁴, a program/erase endurance cycle over 400 times, and data retention longer than 7 × 10³ s. All‐in‐one floating‐gate/tunneling layers containing molybdenum diselenide and tungsten disulfide are also developed. Furthermore, a mechanically‐flexible TMD memory on a plastic substrate shows a performance comparable with that on a hard substrate, and the memory properties are rarely altered after outer‐bending events over 500 times at the bending radius of 4.0 mm.     

Analysis of the Bipolar Resistive Switching Behavior of a Biocompatible Glucose Film for Resistive Random Access Memory

Resistive random access memory (RRAM) devices are fabricated through a simple solution process using glucose, which is a natural biomaterial for the switching layer of RRAM. The fabricated glucose‐based RRAM device shows nonvolatile bipolar resistive switching behavior, with a switching window of 10³. In addition, the endurance and data retention capability of glucose‐based RRAM exhibit stable characteristics up to 100 consecutive cycles and 10⁴ s under constant voltage stress at 0.3 V. The interface between the top electrode and the glucose film is carefully investigated to demonstrate the bipolar switching mechanism of the glucose‐based RRAM device. The glucose based‐RRAM is also evaluated on a polyimide film to verify the possibility of a flexible platform. Additionally, a cross‐bar array structure with a magnesium electrode is prepared on various substrates to assess the degradability and biocompatibility for the implantable bioelectronic devices, which are harmless and nontoxic to the human body. It is expected that this research can provide meaningful insights for developing the future bioelectronic devices.     

Pseudohalide‐Induced 2D (CH3NH3)2PbI2(SCN)2 Perovskite for Ternary Resistive Memory with High Performance

Recently, organic–inorganic hybrid perovskites (OIHP) are studied in memory devices, but ternary resistive memory with three states based on OIHP is not achieved yet. In this work, ternary resistive memory based on hybrid perovskite is achieved with a high device yield (75%), much higher than most organic ternary resistive memories. The pseudohalide‐induced 2D (CH₃NH₃)₂PbI₂(SCN)₂ perovskite thin film is prepared by using a one‐step solution method and fabricated into Al/perovskite film/indium–tin oxide (glass substrate as well as flexible polyethylene terephthalate substrate) random resistive access memory (RRAM) devices. The three states have a conductivity ratio of 1:10³:10⁷, long retention over 10 000 s, and good endurance properties. The electrode area variation, impedance test, and current–voltage plotting show that the two resistance switches are attributable to the charge trap filling due to the effect of unscreened defect in 2D nanosheets and the formation of conductive filaments, respectively. This work paves way for stable perovskite multilevel RRAMs in ambient atmosphere.     

Tunable Tribotronic Dual‐Gate Logic Devices Based on 2D MoS2 and Black Phosphorus

With the Moore's law hitting the bottleneck of scaling‐down in size (below 10 nm), personalized and multifunctional electronics with an integration of 2D materials and self‐powering technology emerge as a new direction of scientific research. Here, a tunable tribotronic dual‐gate logic device based on a MoS₂ field‐effect transistor (FET), a black phosphorus FET and a sliding mode triboelectric nanogenerator (TENG) is reported. The triboelectric potential produced from the TENG can efficiently drive the transistors and logic devices without applying gate voltages. High performance tribotronic transistors are achieved with on/off ratio exceeding 106 and cutoff current below 1 pA μm^–1. Tunable electrical behaviors of the logic device are also realized, including tunable gains (improved to ≈13.8) and power consumptions (≈1 nW). This work offers an active, low‐power‐consuming, and universal approach to modulate semiconductor devices and logic circuits based on 2D materials with TENG, which can be used in microelectromechanical systems, human–machine interfacing, data processing and transmission.     

Magnetic‐Induced‐Piezopotential Gated MoS2 Field‐Effect Transistor at Room Temperature

Utilizing magnetic field directly modulating/turning the charge carrier transport behavior of field‐effect transistor (FET) at ambient conditions is an enormous challenge in the field of micro–nanoelectronics. Here, a new type of magnetic‐induced‐piezopotential gated field‐effect‐transistor (MIPG‐FET) base on laminate composites is proposed, which consists of Terfenol‐D, a ferroelectric single crystal (PMNPT), and MoS₂ flake. When applying an external magnetic field to the MIPG‐FET, the piezopotential of PMNPT triggered by magnetostriction of the Terfenol‐D can serve as the gate voltage to effectively modulate/control the carrier transport process and the corresponding drain current at room temperature. Considering the two polarization states of PMNPT, the drain current is diminished from 9.56 to 2.9 µA in the P_up state under a magnetic field of 33 mT, and increases from 1.41 to 4.93 µA in the P_down state under a magnetic field of 42 mT and at a drain voltage of 3 V. The current on/off ratios in these states are 330% and 432%, respectively. This work provides a novel noncontact coupling method among magnetism, piezoelectricity, and semiconductor properties, which may have extremely important applications in magnetic sensors, memory and logic devices, micro‐electromechanical systems, and human–machine interfacing.     

Graphene–Graphene Oxide Floating Gate Transistor Memory

A novel transparent, flexible, graphene channel floating‐gate transistor memory (FGTM) device is fabricated using a graphene oxide (GO) charge trapping layer on a plastic substrate. The GO layer, which bears ammonium groups (NH₃⁺), is prepared at the interface between the crosslinked PVP (cPVP) tunneling dielectric and the Al₂O₃ blocking dielectric layers. Important design rules are proposed for a high‐performance graphene memory device: i) precise doping of the graphene channel, and ii) chemical functionalization of the GO charge trapping layer. How to control memory characteristics by graphene doping is systematically explained, and the optimal conditions for the best performance of the memory devices are found. Note that precise control over the doping of the graphene channel maximizes the conductance difference at a zero gate voltage, which reduces the device power consumption. The proposed optimization via graphene doping can be applied to any graphene channel transistor‐type memory device. Additionally, the positively charged GO (GO–NH₃⁺) interacts electrostatically with hydroxyl groups of both UV‐treated Al₂O₃ and PVP layers, which enhances the interfacial adhesion, and thus the mechanical stability of the device during bending. The resulting graphene–graphene oxide FGTMs exhibit excellent memory characteristics, including a large memory window (11.7 V), fast switching speed (1 μs), cyclic endurance (200 cycles), stable retention (10⁵ s), and good mechanical stability (1000 cycles).     

A flexible nickel phthalocyanine resistive random access memory with multi-level data storage capability

Metal phthalocyanine is considered one of the most promising candidates for the design and fabrication of flexible resistive random access memory(RRAM)devices due to its intrinsic flexibility and excel-lent functionality.However,performance degradation and the lack of multi-level capability,which can directly expand the storage capacity in one memory cell without sacrificing additional layout area,are the primary obstacles to the use of metal phthalocyanine RRAMs in information storage.Here,a flex-ible RRAM with pristine nickel phthalocyanine(NiPc)as the resistive layer is reported for multi-level data storage.Due to its high trap-concentration,the charge transport behavior of the device agrees well with classical space charge limited conduction controlled by traps,leading to an excellent performance,including a high on-off current ratio of 107,a long-term retention of 106 s,a reproducible endurance over 6000 cycles,long-term flexibility at a bending strain of 0.6％,a write speed of 50 ns under sequential bias pulses and the capability of multi-level data storage with reliable retention and uniformity.     

Using post-breakdown conduction study in a MIS structure to better understand the resistive switching mechanism in an MIM stack

We apply our understanding of the physics of failure in the post-breakdown regime of high-κ dielectric-based conventional logic transistors having a metal-insulator-semiconductor (MIS) structure to interpret the mechanism of resistive switching in resistive random-access memory (RRAM) technology metal-insulator-metal (MIM) stacks. Oxygen vacancies, gate metal migration and metal filament formation in the gate dielectric which constitute the chemistry of breakdown in the post-breakdown stage of logic gate stacks are attributed to be the mechanisms responsible for the SET process in RRAM technology. In this paper, we draw an analogy between the breakdown study in logic devices and filamentation physics in resistive non-volatile memory.     

Flexible memristive memory array on plastic substrates

The demand for flexible electronic systems such as wearable computers, E-paper, and flexible displays has recently increased due to their advantages over present rigid electronic systems. Flexible memory is an essential part of electronic systems for data processing, storage, and communication and thus a key element to realize such flexible electronic systems. Although several emerging memory technologies, including resistive switching memory, have been proposed, the cell-to-cell interference issue has to be overcome for flexible and high performance nonvolatile memory applications. This paper describes the development of NOR type flexible resistive random access memory (RRAM) with a one transistor-one memristor structure (1T-1M). By integration of a high-performance single crystal silicon transistor with a titanium oxide based memristor, random access to memory cells on flexible substrates was achieved without any electrical interference from adjacent cells. The work presented here can provide a new approach to high-performance nonvolatile memory for flexible electronic applications.     

Forming-free flexible memristor with multilevel storage for neuromorphic computing by full PVD technique

Flexible resistive random access memory(RRAM) has shown great potential in wearable electronics.With tunable multilevel resistance states,flexible memristors could be used to mimic the bio-synapses for constructing high-efficient wearable neuromorphic computing system.However,the flexible substrate has intrinsic disadvantages including low-tempe rature tolerance and poor complementary metal-oxidesemiconductor(CMOS) compatibility,which limit the development of flexible electronics.The physical vapor deposition(PVD) fabrication process could prepare RRAM without requirement of further treatment,which greatly simplified preparation steps and reduced the production costs.On the other hand,forming process,as a common pre-programing operation in RRAM,increases the energy consumption and limits the application scenarios of RRAM.Here,a NiO-based forming-free RRAM with low set voltage was fabricated via full PVD technique.The flexible device exhibited reliable re sistive switching characteristics under flat state even compre s sive and tensile states(R=10 mm).The tunable multilevel resistance states(5 levels) could be obtained by controlling the compliance current.Besides,synaptic plasticities also were verified in this device.The flexible NiO-based RRAM shows great potential in wearable forming-free multibit memo ry and neuromorphic computing electronics.     

Retention characteristics of Schottky barrier tunneling transistor-nano floating gate memory with various side walls

At present, the nano floating gate memory (NFGM) device has shown a great promise as a ultra-dense, high-endurance memory device for low-power applications. As the size of the NFGM reduced, the short channel effect became one of the critical issues in the base Field Effect Transistor (FET). Schottky barrier tunneling transistor (SBTT) can improve the controllability of the short channel effect. In this work, we studied nano floating gate memory based on the SBTT. Erbium silicide was employed instead of the conventional heavily doped S/D. The NFGM device based on the SBTT used Si nanocrystals as charge storages. The subthreshold slope and the threshold voltage of the SBTT-NFGM were 90 mV/dec. and 0.2 V, respectively. The memory window appeared about 4 V after the applied write/erase bias at +/- 11 V for 500 ms. The write/erase speeds of the memory device were 50 ms and 200 ms at +/- 13 V, respectively. We also analyzed the retention characteristics of the Schottky barrier tunneling transistor nonvolatile floating gate memory according to the various side walls.     

Tubular 3D Resistive Random Access Memory Based on Rolled‐Up h‐BN Tube

Due to their advantages compared with planar structures, rolled‐up tubes have been applied in many fields, such as field‐effect transistors, compact capacitors, inductors, and integrative sensors. On the other hand, because of its perfect insulating nature, ultrahigh mechanical strength and atomic thickness property, 2D hexagonal boron nitride (h‐BN) is a very suitable material for rolled‐up memory applications. In this work, a tubular 3D resistive random access memory (RRAM) device based on rolled‐up h‐BN tube is realized, which is achieved by self‐rolled‐up technology. The tubular RRAM device exhibits bipolar resistive switching behavior, nonvolatile data storage ability, and satisfactorily low programming current compared with other 2D material‐based RRAM devices. Moreover, by releasing from the substrate, the footprint area of the tubular device is reduced by six times. This tubular RRAM device has great potential for increasing the data storage density, lowering the power consumption, and may be applied in the fields of rolled‐up systems and sensing‐storage integration.     

Structural Phase Transition Effect on Resistive Switching Behavior of MoS2‐Polyvinylpyrrolidone Nanocomposites Films for Flexible Memory Devices

The 2H phase and 1T phase coexisting in the same molybdenum disulfide (MoS₂) nanosheets can influence the electronic properties of the materials. The 1T phase of MoS₂ is introduced into the 2H‐MoS₂ nanosheets by two‐step hydrothermal synthetic methods. Two types of nonvolatile memory effects, namely write‐once read‐many times memory and rewritable memory effect, are observed in the flexible memory devices with the configuration of Al/1T@2H‐MoS₂‐polyvinylpyrrolidone (PVP)/indium tin oxide (ITO)/polyethylene terephthalate (PET) and Al/2H‐MoS₂‐PVP/ITO/PET, respectively. It is observed that structural phase transition in MoS₂ nanosheets plays an important role on the resistive switching behaviors of the MoS₂‐based device. It is hoped that our results can offer a general route for the preparation of various promising nanocomposites based on 2D nanosheets of layered transition metal dichalcogenides for fabricating the high performance and flexible nonvolatile memory devices through regulating the phase structure in the 2D nanosheets.     

Preparation of MoS2‐Polyvinylpyrrolidone Nanocomposites for Flexible Nonvolatile Rewritable Memory Devices with Reduced Graphene Oxide Electrodes

A facile method for exfoliation and dispersion of molybdenum disulfide (MoS₂) with the aid of polyvinylpyrrolidone (PVP) is proposed. The resultant PVP‐coated MoS₂ nanosheets, i.e., MoS₂‐PVP nanocomposites, are well dispersed in the low‐boiling ethanol solvent, facilitating their thin film preparation and the device fabrication by solution processing technique. As a proof of concept, a flexible memory diode with the configuration of reduced graphene oxide (rGO)/MoS₂‐PVP/Al exhibited a typical bistable electrical switching and nonvolatile rewritable memory effect with the function of flash. These experimental results prove that the electrical transition is due to the charge trapping and detrapping behavior of MoS₂ in the PVP dielectric material. This study paves a way of employing two‐dimensional nanomaterials as both functional materials and conducting electrodes for the future flexible data storage.     

Organic Field‐Effect Transistor Memory Devices Using Discrete Ferritin Nanoparticle‐Based Gate Dielectrics

Organic field‐effect transistor (OFET) memory devices made using highly stable iron‐storage protein nanoparticle (NP) multilayers and pentacene semiconductor materials are introduced. These transistor memory devices have nonvolatile memory properties that cause reversible shifts in the threshold voltage (V_th) as a result of charge trapping and detrapping in the protein NP (i.e., the ferritin NP with a ferrihydrite phosphate core) gate dielectric layers rather than the metallic NP layers employed in conventional OFET memory devices. The protein NP‐based OFET memory devices exhibit good programmable memory properties, namely, large memory window ΔV_th (greater than 20 V), a fast switching speed (10 μs), high ON/OFF current ratio (above 10⁴), and good electrical reliability. The memory performance of the devices is significantly enhanced by molecular‐level manipulation of the protein NP layers, and various biomaterials with heme Fe^III/Fe^II redox couples similar to a ferrihydrite phosphate core are also employed as charge storage dielectrics. Furthermore, when these protein NP multilayers are deposited onto poly(ethylene naphthalate) substrates coated with an indium tin oxide gate electrode and a 50‐nm‐thick high‐k Al₂O₃ gate dielectric layer, the approach is effectively extended to flexible protein transistor memory devices that have good electrical performance within a range of low operating voltages (<10 V) and reliable mechanical bending stability.     

A High‐Performance Top‐Gated Graphene Field‐Effect Transistor with Excellent Flexibility Enabled by an iCVD Copolymer Gate Dielectric

A high‐performance top‐gated graphene field‐effect transistor (FET) with excellent mechanical flexibility is demonstrated by implementing a surface‐energy‐engineered copolymer gate dielectric via a solvent‐free process called initiated chemical vapor deposition. The ultrathin, flexible copolymer dielectric is synthesized from two monomers composed of 1,3,5‐trimethyl‐1,3,5‐trivinyl cyclotrisiloxane and 1‐vinylimidazole (VIDZ). The copolymer dielectric enables the graphene device to exhibit excellent dielectric performance and substantially enhanced mechanical flexibility. The p‐doping level of the graphene can be tuned by varying the polar VIDZ fraction in the copolymer dielectric, and the Dirac voltage (V_Dirac) of the graphene FET can thus be systematically controlled. In particular, the V_Dirac approaches neutrality with higher VIDZ concentrations in the copolymer dielectric, which minimizes the carrier scattering and thereby improves the charge transport of the graphene device. As a result, the graphene FET with 20 nm thick copolymer dielectrics exhibits field‐effect hole and electron mobility values of over 7200 and 3800 cm² V^?1 s^?1, respectively, at room temperature. These electrical characteristics remain unchanged even at the 1 mm bending radius, corresponding to a tensile strain of 1.28%. The formed gate stack with the copolymer gate dielectric is further investigated for high‐frequency flexible device applications.     

Two‐Terminal Multibit Optical Memory via van der Waals Heterostructure

2D van der Waals (vdWs) heterostructures exhibit intriguing optoelectronic properties in photodetectors, solar cells, and light‐emitting diodes. In addition, these materials have the potential to be further extended to optical memories with promising broadband applications for image sensing, logic gates, and synaptic devices for neuromorphic computing. In particular, high programming voltage, high off‐power consumption, and circuital complexity in integration are primary concerns in the development of three‐terminal optical memory devices. This study describes a multilevel nonvolatile optical memory device with a two‐terminal floating‐gate field‐effect transistor with a MoS₂/hexagonal boron nitride/graphene heterostructure. The device exhibits an extremely low off‐current of ≈10^?14 A and high optical switching on/off current ratio of over ≈10⁶, allowing 18 distinct current levels corresponding to more than four‐bit information storage. Furthermore, it demonstrates an extended endurance of over ≈10⁴ program–erase cycles and a long retention time exceeding 3.6 × 10⁴ s with a low programming voltage of ?10 V. This device paves the way for miniaturization and high‐density integration of future optical memories with vdWs heterostructures.