A 16×16 crosspoint switch for ternary encoded signals

A crosspoint-switching chip that can switch bipolar, alternate mark inversion encoded (AMI) signals directly, is described. AMI encoding is a form of ternary, return-to-zero (RZ) coding where a binary zero is represented by an absence of a pulse and ones are represented with an alternating sequence of positive and negative pulses. Bipolar signals are used widely in interoffice telecommunications such as the T1, T1C, T2, and T3 digital transmission systems. The switching chip has 16 input and 16 output channels. Control of the chip allows any input to be connected to any output or outputs, providing a nonblocking connection. The architecture allows for expansion of the crosspoint array by paralleling several chips. The chip, fabricated using a standard 3-μm CMOS technology, is capable of handling data rates up to 15 Mb/s per channel, has about 17000 transistors, and has an area of about 32.5 mm²     

A 2 Gb/s expandable space-division switching LSI and networkarchitecture for gigabit-rate broad-band circuit switching

An expandable space-division (SD) switch architecture and a bipolar circuit design for gigabit-per-second crosspoint-switch LSIs are described. An expandable 2-Gb/s 16×16 crosspoint switch LSI which employs a novel switch structure, a novel circuit design, and a super self-aligned process (SST-1A) is developed. A switching module and partial 1:n nonblock, full 1:1 nonblock switching network architecture are also presented. Using the LSI and the switching network architecture, an experimental 620-Mb/s network system is demonstrated     

2 Gbit/s, 16*16 expandable high-speed space-division-switch LSI using SST

A Si bipolar 2 Gbit/s 16*16 high-speed space-division-switch LSI is described. High-speed operation of 2 Gbit/s and low-power dissipation of 2.8 W are achieved by adopting a new expandable structure, a very low voltage swing-differential bipolar circuit design and a super self-aligned process technology (SST-1A). This LSI is applicable to future B-ISDN HDTV switching systems.<>     

A high-speed CMOS circuit for 1.2-Gb/s 16*16 ATM switching

The authors describe a 0.7- mu m CMOS asynchronous transfer mode (ATM) switch circuit of 350 K transistors, the kernel of a fully autonomous 16*16 ATM switching matrix devoted to telecommunications. This matrix is able to switch ATM multiplexes with a throughput of up to 1.2 Gb/s per access line, and was implemented using 16 receiver/transmitter circuits and a control circuit. The architecture of the ATM switch circuit is based on a large embedded and shared dual-access memory. Each chip processes 4-b slices of each incoming multiplex. Seven such chips working in parallel are enough to achieve standard ATM cell switching. Up-to-date test features, such as boundary scan, built-in self-test, and redundancy were implemented in the circuit.<>     

A low-power transmission-gate-based 16-bit multiplier for digital hearing aids

The most widespread 16-bit multiplier architectures are compared in terms of area occupation, dissipated energy, and EDP (Energy-Delay Product) in view of low-power low-voltage signal processing for digital hearing aids and similar applications. Transistor-level simulations including back-annotated wire parasitics confirm that the propagation of glitches along uneven and re-convergent paths results in large unproductive node activity. Because of their shorter full-adder chains, Wallace-tree multipliers indeed dissipate less energy than the carry-save (CSM) and other traditional array multipliers (6.0 µW/MHz versus 10.9 µW/MHz and more for 0.25 µm CMOS technology at 0.75 V). By combining the Wallace-tree architecture with transmission gates (TGs), a new approach is proposed to improve the energy efficiency further (3.1 µW/MHz), beyond recently published low-power architectures. Besides the reduction of the overall capacitance, minimum-sized transmission gate full-adders act as RC-low-pass filters that attenuate undesired switching. Finally, minimum size TGs increase the V _dd to ground resistance, hence decreasing leakage dissipation (0.55 nW versus 0.84 nW in CSM and 0.94 nW in Wallace).     

Implementation of a 16 to 16 switching element for ATM exchanges

The authors describe the implementation of an asynchronous transfer mode (ATM) switching element with 16 inlets and 16 outlets at 600 Mb/s each. The single board switching element is used as a basic switching block in a connection-oriented ATM switching network. The design of the switching element was carried out by using advanced BiCMOS technologies. It is shown how the functional scheme is translated into a feasible chip partitioning and which design options were taken. In particular, the design of the cell switching facility and the queueing memory is treated in detail. A comparison between memory pooling or individual output queues is presented. By making the choice of the latter solution, the development schedule could be kept very tight. Second, the testability of the chips remains good despite the high gate complexity     

16-Mb synchronous DRAM with 125-Mbyte/s data rate

In order to keep up with the growing need for memory bandwidth at low cost, a new synchronous DRAM (SDRAM) architecture is proposed. The SDRAM has programmable latency, burst length, and burst type for wide variety of applications. The experimental 16M SDRAM (2M×8) achieves a 125-Mbyte/s data rate using 0.5-μm twin well CMOS technology     

Distributed Microprocessors Control Architecture for Versatile Business Communications

This paper describes the NEAX®2400 Information Management System (IMS), which is no longer a conventional telephone switching system, but is instead a switching hub for various office automation equipment. The NEAX2400 IMS not only provides various circuit-switching functions such as conventional voice communication (telephone) switching, low-speed and high-speed data switching, but also provides stored and forward capabilities for voice (voice mail) and data (text mail, facsimile mail, etc.). This paper especially emphasizes the basic EPBX features and functions of the NEAX2400 IMS. The standard 64 kbit/s PCM technique is used for digitalization of voice signals, and switched through a nonblocking architecture time-division digital network. All digital data signals are transmitted through the same time-division digital network at the 64 kbit/s rate intermixed with digital voice signals. The controls of the switching functions, station service features, and maintenance service are performed by functionally divided distributed microprocessers. The most outstanding attribute of the NEAX2400 IMS is the unique building-block architecture of the equipment configuration. Modules are stacked above the basic module as the number of line and trunk ports, or additional stored and forward features are required. Up to four additional modules can be stacked up as a single module group. This unique arrangement permits the NEAX2400 IMS to be very flexible in its system applications and expandability. Practically, the NEAX2400 IMS will economically service as few as 184 ports (mixture of voice/data, line/trunk) and can be continuously expanded to as many as 23 184 ports.     

A 70-Mbit/s (RZ) 16×16 crosspoint switch for ternary-encodedsignals

An experimental 16×16 crosspoint switch that can switch ternary signals and handle data rates of up to 70 Mb/s return-to-zero (RZ) (equivalent to 140-Mb/s nonreturn-to-zero (NRZ)) per channel is described. Ternary signals, in particular, alternate mark inversion (AMI) encoded signals, are widely used in telephone interoffice digital-transmission systems. This chip could be used in an asynchronous cross-connection system at the DS3 (44.736-Mb/s) signal level. This crosspoint chip has 16 input and 16 output channels. Any input can be connected to any output or outputs without blocking. The architecture allows for paralleling many chips to increase the size of the crosspoint array and also for cascading them to provide multistage switching capability. The switch can be addressed in the same way as a memory chip, and the cross-connection map can be written to and read back from the device. The chip is fabricated using a standard 2-μm CMOS technology, and the die size is 20.16 mm² (177.2×176.4 mil), containing about 11000 transistors     

LSB split capacitor SAR ADC with 99.2% switching energy reduction

A highly energy efficient capacitor switching technique in a successive approximation register (SAR) analog to digital converter (ADC) for biomedical applications is presented. The proposed scheme based on new switching method, which combine the LSB split capacitive technique and monotonic method can reduce the average switching energy by 99.2% compared to the conventional SAR architecture. Besides reducing energy in each comparison cycle, the suggested method also achieves an 8× reduction in total capacitance used in the digital to analog converter over the conventional one with the same resolution. The proposed ADC can find application in biomedical engineering systems and other fields which low power consumption is needed.     

APC-AB codec modules operating at 16 and 8 kbit/s

High-quality speech codec modules operating at 16 and 8 kb/s have been developed using an adaptive predictive coding with adaptive bit allocation (APC-AB) scheme. An optimized APC-AB algorithm is studied that reduces processing complexity while maintaining speech quality. The coding algorithm is implemented in two digital signal processors (DSPs). The DSP chips, a framing LSI circuit, a PCM codec, and some peripheral ICs are integrated in each of two compact packages, i.e. codec modules, operating at 16 or 8 kb/s. The codec module size is as small as 80 mm×50 mm×12 mm, and its typical power consumption is 500 mW using 2-μm CMOS LSI technology. At 16 kb/s this APC-AB codec achieves high speech quality, close to that of a 7-bit μ-law PCM. The codec modules are expected to be used for various applications such as customer premises multiplexers for digital leased lines, digital mobile radio, and stored-and-forward-message systems (voice-mail systems)     

An expandable column fft architecture using circuit switching networks

The Fast Fourier Transform (FFT) is widely used in various digital signal processing applications. The performance requirements for FFT in modern real-time applications has increased dramatically due to the high demand on capacity and performance of modern telecommunication systems, where FFT plays a major role. Software implementations of FFT running on a general purpose computer can no longer meet current speed requirements. However, recent advances in VLSI technology have made it possible to implement the entire FFT system on a single silicon substrate. This article presents a column FFT design suitable for ULSI (Ultra Large Scale Integration) implementations. The basic building block is a 64-point column FFT. FFTs with longer transform lengths can be easily realized using the 64-point column FFT building block. The butterfly processors in the column FFT are connected using circuit switching networks. The circuit switching networks not only provide dynamically recon-figurable interconnections among the butterfly processors, but also provide a fault-tolerant capability. Bit-serial arithmetic is used in the architecture. Assuming the data word length is 16 bits, the 1024-point column FFT engine proposed in this article is capable of processing 1024 complex data samples in 533 clock cycles. If the clock frequency is 40 MHz, it will take 13.3 µs to complete a 1024-point FFT.     

An expandable time-division circuit switching LSI and networkarchitecture for broadband ISDN

A broadband network architecture is proposed that integrates multimedia services, such as data, video, and telephony information, using 52-Mb/s based STM-paths at the user network interface (UNI). The user can access any new service via the STM-based access network via either synchronous transfer mode (STM) switching or asynchronous transfer mode (ATM) switching. STM circuit switching supports long duration, constant bandwidth data transfer services such as video and high-definition television (HDTV) distribution and will also be used for the crossconnect system. Circuit switching can provide transparent transmission during long connection periods. This paper also proposes an expandable time-division switch architecture, an expandable time-division switching LSI, and an expandable switching module for small to large size system applications. The proposed time-division switching LSI, module, and system handle 52-Mb/s bearer signals and have throughputs of 2.4 Gb/s, 10 Gb/s, and 40 Gb/s, respectively. The time-division switch realizes video distribution with 1:n connections. Finally, a local switching node that features an expandable 52-Mb/s time-division circuit switching network is shown for multimedia access networking     

16 Kb/s high quality voice encoding for satellite communication networks

This paper describes applications of adaptive predictive coding (APC) with maximum likelihood quantization (MLQ) which can cover a wide range of coding rates from 4.8 to 16 kb/s for low C/N satellite communication systems, such as maritime, aeronautical mobile and thin-route satellite communication systems, and also for speech and data integration, including digital circuit multiplication equipment (DCME) in business communication systems, such as INTELSAT business services (IBS). A 16 kb/s APC–MLQ hardware codec has been implemented by NEC–7720 DSP chips and the performance has been confirmed in subjective quality of speech through conversational tests. The objective performance has also been evaluated for non-voice signals, such as single and multi-frequency tones, and 1200 and 2400 b/s voiceband data signals. The APC-MLQ codec can transmit the voice-band data at 1200 b/s over two asynchronous tandem links and at 2400 b/s over one link. It was noted that the APC-MLQ codec is superior in speech performance at 16 kb/s to a narrow-band companded FM and meets requirements for low C/N satellite communication systems. For voice and data integration into 16 kb/s for 64 kb/s links, we propose a multi-media multiplexing for low C/N digital satellite communication systems and also a small-scale circuit multiplication system for business use. In these systems, a variable rate coding of APC-MLQ from 4.8 to 16 kb/s can be effectively introduced for voice and data integration.     

A 10-bit 50-MS/s redundant SAR ADC with split capacitive-array DAC

A new architecture for successive-approximation register analog-to-digital converters (SAR ADC) using generalized non-binary search algorithm is proposed to reduce the complexity and power consumption of the digital circuitry. The proposed architecture is based on the split capacitive-array DAC with a simple switching logic as compared to the conventional non-binary SAR ADC architecture. A 10-bit 50-MS/s SAR ADC is designed based on the proposed architecture in a 0.18 μm CMOS technology. Simulation results show that at a supply voltage of 1.2 V, the SAR ADC achieves a peak signal-to-noise-and-distortion ratio of 59.5 dB, and a power consumption of 1.3 mW, resulting in a figure of merit of 33 fJ/conversion-step.     

BZ-FAD: A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture

In this paper, a low-power structure called bypass zero, feed A directly (BZ-FAD) for shift-and-add multipliers is proposed. The architecture considerably lowers the switching activity of conventional multipliers. The modifications to the multiplier which multiplies A by B include the removal of the shifting the B register, direct feeding of A to the adder, bypassing the adder whenever possible, using a ring counter instead of a binary counter and removal of the partial product shift. The architecture makes use of a low-power ring counter proposed in this work. Simulation results for 32-bit radix-2 multipliers show that the BZ-FAD architecture lowers the total switching activity up to 76% and power consumption up to 30% when compared to the conventional architecture. The proposed multiplier can be used for low-power applications where the speed is not a primary design parameter.     

A 2-V, 1.8-GHz BJT phase-locked loop

This paper describes the design of a bipolar junction transistor phase-locked loop (PLL) for ΣΔ fractional-N frequency-synthesis applications. Implemented in a 0.8-μm BiCMOS technology, the PLL can operate up to 1.8 GHz while consuming 225 mW of power from a single -2-V supply. The entire LC-tuned negative-resistance variable-frequency oscillator is integrated on the same chip. A differential low-voltage current-mode logic circuit configuration is used in most of the PLL's functional blocks to minimize phase jitter and achieve low-voltage operation. The multimodulus frequency divider is designed to support multibit digital modulation. The new phase and frequency detector and loop filter contain only npn transistors and resistors and thus achieve excellent resolution in phase comparison. When phase locked to a 53.4-MHz reference clock, the measured phase noise of the 16-GHz output is -91 dBc/Hz at 10-kHz offset. The frequency switching time from 1.677 to 1.797 GHz is 150 μs. Die size is 4300×4000 μm², including the passive loop filter     

SIGMA: a VLSI systolic array implementation of a Galois field GF(2m) based multiplication and division algorithm

Finite or Galois fields are used in numerous applications like error correcting codes, digital signal processing and cryptography. The design of efficient methods for Galois field arithmetic such as multiplication and division is critical for these applications. A new algorithm based on a pattern matching technique for computing multiplication and division in GF(2^m) is presented. An efficient systolic architecture is described for implementing the algorithm which can produce a new result every clock cycle and the multiplication and division operations can be interleaved. The architecture has been implemented using 2-μm CMOS technology. The chip yields a computational rate of 33.3 million multiplications/divisions per second     

An efficient threshold voltage generation for SAR ADCs

In this paper, a new architecture for successive-approximation register (SAR) analog-to-digital converters (ADCs) is presented. In the proposed scheme, the threshold voltage for each comparison is divided into two parts. This results in appreciably less switching energy and less total capacitance without a substantial increase in digital complexity compared to the conventional SAR ADC. Analytical calculations and circuit level simulation results in the context of a 10-bit 100 kS/s ADC are provided to verify the usefulness of the proposed SAR ADC scheme revealing 87 % less switching power and 40 % less total capacitance in comparison with the conventional SAR ADC.     

A digital quadrature modulator with on-chip D/A converter

The first analog IF mixer stage of a transmitter can be replaced with this digital quadrature modulator. The modulator interpolates orthogonal input carriers by 16 and performs digital quadrature modulation at carrier frequencies f/sub s//4, -f/sub s//4,f/sub s//2 (f/sub s/ is the sampling frequency). A 12-b digital-to-analog (D/A) converter is integrated with the digital quadrature modulator. A segmented current source architecture is combined with a proper switching technique to reduce spurious components and to enhance dynamic performance. The digital quadrature modulator is designed to fulfill the spectral, phase, and EVM specifications of GSM, EDGE, and WCDMA base stations. The die area of the chip is 27.09 mm/sup 2/ (0.35-/spl mu/m CMOS technology) and the total power consumption is 1.02 W with 2.8 V at 500-MHz output sampling rate (0.78-W digital modulator, 0.24-W D/A converter).