一种具有高K栅介质与低k侧壁介质的PNPN型隧穿晶体管研究

本文提出了一种具有高K栅介质及低K侧壁介质的PNPN型隧穿场效应晶体管,并通过二维仿真研究了栅电场和侧壁电场对隧穿场效应晶体管性能的影响。结果表明高K栅介质可以增强栅对沟道的控制能力,同时低K侧墙介质有助于增大带带隧穿的几率。具有这种结构的隧穿场效应晶体管器件具有很好的开关特性、大的开态电流以及良好的工艺容差。该器件可以应用于低功耗领域,并有可能作为下一代CMOS技术的替代者之一。     

Drain current model for double-gate tunnel field-effect transistor with hetero-gate-dielectric and source-pocket

In this paper, the application of hetero-gate-dielectric (HGD) and source-pocket (SP) in a double-gate tunnel field-effect transistor (TFET) is proposed for the first time to simultaneously boost the on-current and suppress the ambipolar current. Quasi-two-dimensional (2D) potential and electric field analytical models for the HGD-SP TFET are developed by solving 2D Poisson's equation with matching boundary conditions. Based on the Kane's formula, analytical expression for the band-to-band generation is derived and then used to calculate the drain current. Device Performance for HGD–SP TFET is studied and compared with corresponding HGD TFET and SP TFET. It is demonstrated that the proposed device architecture outperforms the other two devices in terms of on current and ambipolar current. Moreover, the models exactly depict the influence of pocket doping, pocket width, and gate dielectric constant on the surface potential, electric field, and drain current of a HGD–SP TFET. The good accordance between the modeled results and numerical simulation results verifies the accuracy of the proposed models.     

高k栅介质MOSFET的栅电流模型

提出了包括有限势垒高度下反型层量子化效应以及多晶硅耗尽效应在内的直接隧穿电流模型.在该模型的基础上,研究了采用不同高介电常数栅介质材料时MOSFET的栅电流与介质材料的介电常数、禁带宽度及和Si导带不连续等参数之间的关系.所获得的结果能够为新型栅介质材料的选取提供依据.     

高k栅介质MOSFET的栅电流模型

提出了包括有限势垒高度下反型层量子化效应以及多晶硅耗尽效应在内的直接隧穿电流模型.在该模型的基础上,研究了采用不同高介电常数栅介质材料时MOSFET的栅电流与介质材料的介电常数、禁带宽度及和Si导带不连续等参数之间的关系.所获得的结果能够为新型栅介质材料的选取提供依据.     

A 2-D Semi-Analytical Model of Double-Gate Tunnel Field-Effect Transistor Xu Huifang (许会芳), Dai Yuehua*(代月花), Li Ning(李宁), Xu JianBin(徐建斌)

文中提出了一种双栅隧穿场效应晶体管(DG TFET)的二维半解析模型。通过在栅绝缘层和沟道区引入两个矩形源,运用半解析法和特征函数展开法求解二维泊松方程,得到电势的二维半解析解。解的结果是一个特殊函数,为无穷级数表达式。基于电势模型,求出最短隧穿长度( )和平均电场( ),运用Kane模型得到漏极电流。新模型考虑了移动电荷对电势的影响以及漏源电压对隧穿参数 和 的影响。文中计算了不同漏源电压,不同硅膜厚度,栅介质层厚度和栅介质层常数下的表面势和漏极电流。结果表明,新模型与仿真结果吻合。这将有助于DG TFET的优化设计,同时,也加深了DG TFET器件对电路结构设计的规划。     

The effect of high-K gate dielectrics on deep submicrometer CMOSdevice and circuit performance

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K_gate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K_gate for different target subthreshold leakage currents has been identified     

HfTiO氮化退火对MOS器件电特性的影响

采用磁控溅射方法,在Si衬底上淀积HfTiO高k介质,研究了NO、N2O、NH3和N2不同气体退火对MOS电特性的影响。结果表明,由于NO氮化退火能形成类SiO2/Si界面特性的HfTiSiON层,所制备的MOS器件表现出优良的电特性,即低的界面态密度、低的栅极漏电和高的可靠性。根据MOS器件栅介质(HfTiON/HfTiSiON)物理厚度变化(ΔTox)和电容等效厚度变化(ΔCET)与介质(HfTiON)介电常数的关系,求出在NO气氛中进行淀积后退火处理的HfTiON的介电常数达到28。     

高k栅极电介质材料与Si纳米晶体管

Si MOS晶体管进入nm尺度后,原来通用的栅极介电材料SiO2已不能适应纳米晶体管继续小型化的需要,必须用高k栅极电介质材料取而代之。对Si纳米晶体管为什么要采用高k栅极电介质材料、此类材料的物理性能和电学性能、与Si之间的相容性以及材料中缺陷对其性能和器件的影响等一系列问题进行了论述,并且讨论了高k栅极电介质材料的进一步发展。     

长沟道圆柱围栅高K栅栈结构MOSFETs器件的直接隧穿电流解析模型

An analytical direct tunneling gate current model for cylindrical surrounding gate（CSG） MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the gate＇s oxide thickness, but that it is less affected by the change in channel radius. It is also revealed that when the thickness of the equivalent oxide is constant, the thinner the first layer, the smaller the direct tunneling gate current.Moreover, it can be seen that the dielectric with a higher dielectric constant shows a lower tunneling current than expected. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.     

Polyimide/polyvinyl alcohol bilayer gate insulator for low-voltage organic thin-film transistors

In this paper, we report the fabrication of a polyimide/polyvinyl alcohol (PVA) bilayer gate insulator for low-voltage organic thin-film transistors (TFTs). The introduction of a PVA layer to form a bilayer structure improves the dielectric and insulating properties of the gate insulator. Organic TFTs with 150 nm-thick polyimide and PVA gate insulators were inactive at low operation voltages below 5 V. Conversely, organic TFTs with 150 nm-thick polyimide/PVA bilayer gate insulators exhibited excellent device performances. Our results suggest that the introduction of a PVA layer with a high dielectric constant could be a simple and efficient way to improve the device performance of low-voltage organic TFTs.     

A physical model on electron mobility in InGaAs nMOSFETs with stacked gate dielectric

An inversion-channel electron mobility model for InGaAs n-channel metal–oxide-semiconductor field-effect transistors (nMOSFETs) with stacked gate dielectric is established by considering scattering mechanisms of bulk scattering, Coulomb scattering of interface charges, interface-roughness scattering, especially remote Coulomb scattering and remote interface-roughness scattering. The simulation results are in good agreement with the experimental data. The effects of device parameters on degradation of electron mobility, e.g. interface roughness, dielectric constant and thickness of high-k layer/interlayer, and the doping concentration in the channel, are discussed. It is revealed that a tradeoff among the device parameters has to be performed to get high electron mobility with keeping good other electrical properties of devices.     

Polymer Dielectrics and Orthogonal Solvent Effects for High‐Performance Inkjet‐Printed Top‐Gated P‐Channel Polymer Field‐Effect Transistors

We investigated the effects of a gate dielectric and its solvent on the characteristics of top‐gated organic field‐effect transistors (OFETs). Despite the rough top surface of the inkjet‐printed active features, the charge transport in an OFET is still favorable, with no significant degradation in performance. Moreover, the characteristics of the OFETs showed a strong dependency on the gate dielectrics used and its orthogonal solvents. Poly(3‐hexylthiophene) OFETs with a poly(methyl methacrylate) dielectric showed typical p‐type OFET characteristics. The selection of gate dielectric and solvent is very important to achieve high‐performance organic electronic circuits.     

A novel hetero-junction Tunnel-FET using Semiconducting silicide–Silicon contact and its scalability

A new type of silicon-based Tunneling FET (TFET) using semiconducting silicide Mg₂Si/Si hetero-junction as source-channel structure is proposed and the device simulation has been presented. With narrow bandgap of silicide and the conduction and valence band discontinuous at the hetero-junction, larger drain current and smaller subthreshold swing than those of Si homo-junction TFET can be obtained. Structural optimization study reveals that low Si channel impurity concentration and the alignment of the gate electrode edge to the hetero-junction lead to better performance of the TFET. Scaling of the gate length increases the off-state leakage current, however, the drain voltage (V_d) reduction in accordance with the gate scaling suppresses the phenomenon, keeping its high drivability.     

有机场效应晶体管最新实验研究进展

介绍了近两年新报道的有机半导体材料,列举了其场效应性能参数;综述了有机场效应晶体管(OFET)在器件结构上的改进,重点阐述了基于常见有机功能层材料富勒烯及其衍生物、并五苯、聚3-己基噻吩的OFET对栅介质层及有机功能层与电极的界面的改进,讨论了器件结构改进对OFET阈值电压、开关比、载流子迁移率的影响;介绍了衬底温度、退火处理对OF-ET性能的影响。最后,针对有机场效应晶体管研究现状,指出未来研究中应注重开发高迁移率、高薄膜稳定性的有机功能材料和高介电常数、高成膜质量的有机栅介质材料,继续优化器件结构,改进制备工艺以提高器件性能。     

具有栅介质电场屏蔽作用的新型GaN纵向槽栅MOSFET器件设计

基于氮化镓(GaN)等宽禁带(WBG)半导体的金氧半场效应晶体管(MOSFET)器件在关态耐压下,栅介质中存在与宽禁带半导体临界击穿电场相当的大电场,致使栅介质在长期可靠性方面受到挑战。为了避免在GaN器件中使用尚不成熟的p型离子注入技术,提出了一种基于选择区域外延技术制备的新型GaN纵向槽栅MOSFET,可通过降低关态栅介质电场来提高栅介质可靠性。提出了关态下的耗尽区结电容空间电荷竞争模型,定性解释了栅介质电场p型屏蔽结构的结构参数对栅介质电场的影响规律及机理,并通过权衡器件性能与可靠性的关系,得到击穿电压为1 200 V、栅介质电场仅0.8 MV/cm的具有栅介质长期可靠性的新型GaN纵向槽栅MOSFET。     

氧化镉掺杂对钛酸钡基陶瓷材料改性

对ＢａＴｉＯ３－ＺｎＮｂ２Ｏ６－ＣｄＯ系陶瓷介质材料的介电性质进行了研究，并对ＢａＴｉＯ３，ＢａＴｉＯ３－ＺｎＮｂ２Ｏ６，ＢａＴｉＯ３－ＺｎＮｂ２Ｏ６－ＣｄＯ三种材料介电常数，温度稳定性，介电损耗，显微结构进行了比较，得出结论是ＢａＴｉＯ３－ＺｎＮｂ２Ｏ６－ＣｄＯ系陶瓷材料，介电常数高，损耗小，介电常数随温度变化小，是较理想的电容器陶瓷介质材料     

Impact of parameter fluctuations on RF stability performance of DG Tunnel FET

This paper presents the impact of parameter fluctuation due to process variation on radio frequency (RF) stability performance of double gate tunnel FET (DG TFET). The influence of parameter fluctuation due to process variation leads to DG TFET performance degradation. The RF figures of merit (FoM) such as cut-off frequency (f_t), maximum oscillation frequency (f_max) along with stability factor for different silicon body thickness, gate oxide thickness and gate contact alignment are obtained from extracted device parameters through numerical simulation. The impact of parameter fluctuation of silicon body thickness, gate oxide thickness and gate contact alignment was found significant and the result provides design guidelines of DG TFET for RF applications.     

Submicron-meter tunneling field-effect poly-Si thin-film transistors with a thinned channel layer

Submicron-meter poly-Si tunneling-effect thin-film transistor (TFT) devices with a thinned channel layer have been investigated. With reducing the gate length to be shorter than 1 μm, the poly-Si TFT device with conventional MOSFET structure is considerably degraded. The tunneling field-effect transistor (TFET) structure can be employed to alleviate the short channel effect, thus largely suppressing the off-state leakage. However, for a poly-Si channel layer of 100 nm thickness, the TFET structure causes a small on-state current, which may not provide well sufficient driving current. By reducing the channel layer thickness to be 20 nm, the on-state current for the TFET structure can be largely increased, due to the enhanced bending of energy band for a thinned channel layer. As a result, for the TFET poly-Si TFTs at a gate bias of 5 V and a drain bias of 3 V, a 20-nm channel layer leads to an on-state current of about 1 order larger than that by a 100-nm channel layer, while still keeping an off-state leakage smaller than 0.1 pA/μm. Accordingly, the submicron-meter TFET poly-Si TFT devices with a thinned channel layer would show good feasibility for implementing high packing density of poly-Si TFT devices.     

Acrylate-based nanocomposite zirconium-dispersed polymer dielectric for flexible oxide thin-film transistors with a curvature radius of 2 mm

Novel hybrid dielectric film is synthesized at a low temperature of 150 °C using a solution process. Zirconium acrylate (ZrA) and poly(methyl methacrylate) (PMMA) comprise the inorganic and organic components, respectively. The acrylate-based molecular structure of both ingredients allows the facile formation of hybrid ZrA/PMMA dielectric film with neither additional coupling agent nor ultraviolet photon irradiation. The high quality of the hybrid ZrA/PMMA dielectric film is confirmed by its high dielectric constant of 5.5 and low leakage current density of 1.7 × 10⁻⁸ A/cm² at the electric field of 1 MV/cm. The indium gallium tin oxide (IGTO) transistors with the optimal ZrA/PMMA gate insulator layer are fabricated on the polyimide substrate at the maximum high temperature of 150 °C. They exhibit hysteresis-free high performance with high carrier mobility of 24.3 cm²V⁻¹s⁻¹, gate swing of 0.61 V/decade and I_ON/OFF ratio of 4 × 10⁶. Owing to the intrinsic deformability of hybrid dielectric film, these transistors maintained electrical performance after 100 cycles of mechanical bending to the extremely small radius of curvature of 2 mm.     

Low voltage copper phthalocyanine organic thin film transistors with a polymer layer as the gate insulator

Low voltage organic thin film transistors(OTFTs) were created using polymethyl-methacrylate-co g-lyciclyl-methacrylate(PMMA-GMA) as the gate dielectric.The OTFTs performed acceptably at supply voltages of about 10 V.From a densely packed copolymer brush,a leakage current as low as 2×10~(-8) A/cm~2 was obtained.From the measured capacitance-insulator frequency characteristics,a dielectric constant in the range 3.9-5.0 was obtained. By controlling the thickness of the gate dielectric,the threshold voltage ...