一种应用于GPS接收机的高线性度SiGe HBT低噪声放大器

A high linearity 1.575 GHz SiGe：HBT low noise amplifier （LNA） for global positioning system applications is described. The bipolar cascoded with an MOSFET LNA was fabricated in a commercial 0.18 μm SiGe BiCMOS process, A resistor bias feed circuit with a feedback resistor was designed for the LNA input transistor to improve its intermodulation and compression performance. The packaged chip tested on board has displayed a noise figure of 1. I 1 dB, a power gain of 18 dB, an output 1 dB compression point of ＋7.8 dBm and an input third-order intercept point of ＋1.8 dBm. The chip occupies a 500 × 560μm^2 area and consumes 3.6 mA from a 2.85 V power supply.     

A 0.18μm CMOS low noise amplifier using a current reuse technique for 3.1-10.6 GHz UWB receivers

A new,low complexity,ultra-wideband 3.1-10.6 GHz low noise amplifier(LNA),designed in a chartered 0.18μm RFCMOS technology,is presented.The ultra-wideband LNA consists of only two simple amplifiers with an inter-stage inductor connected.The first stage utilizing a resistive current reuse and dual inductive degeneration technique is used to attain a wideband input matching and low noise figure.A common source amplifier with an inductive peaking technique as the second stage achieves high flat gain and wide -3 dB bandwidth of the overall amplifier simultaneously.The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB,and a high reverse isolation of—45 dB,and good input/output return losses are better than -10 dB in the frequency range of 3.1-10.6 GHz.An excellent noise figure(NF) of 2.8-4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V.An input-referred third-order intercept point(IIP3) is -7.1 dBm at 6 GHz.The chip area,including testing pads,is only 0.8×0.9 mm2.     

Design of a fully differential CMOS LNA for 3.1-10.6 GHz UWB communication systems

A fully differential complementary metal oxide semiconductor （CMOS） low noise amplifier （LNA） for 3.1-10.6 GHz ultra-wideband （UWB） communication systems is presented. The LNA adopts capacitive cross-coupling common-gate （CG） topology to achieve wideband input matching and low noise figure （NF）. Inductive series-peaking is used for the LNA to obtain broadband flat gain in the whole 3.1-10.6 GHz band. Designed in 0.18 um CMOS technology, the LNA achieves an NF of 3.1-4.7 dB, an Sll of less than -10 dB, an S21 of 10.3 dB with ±0.4 dB fluctuation, and an input 3rd interception point （IIP3） of -5.1 dBm, while the current consumption is only 4.8 mA from a 1.8 V power supply. The chip area of the LNA is 1×0.94 mm^2.     

S-band low noise amplifier using 1μm InGaAs/InAlAs/InP pHEMT

正This paper discusses the design of a wideband low noise amplifier(LNA) in which specific architecture decisions were made in consideration of system-on-chip implementation for radio-astronomy applications.The LNA design is based on a novel ultra-low noise InGaAs/InAlAs/InP pHEMT.Linear and non-linear modelling of this pHEMT has been used to design an LNA operating from 2 to 4 GHz.A common-drain in cascade with a common source inductive degeneration,broadband LNA topology is proposed for wideband applications.The proposed configuration achieved a maximum gain of 27 dB and a noise figure of 0.3 dB with a good input and output return loss(S_(11)—10 dB,S_(22)—11 dB).This LNA exhibits an input 1-dB compression point of-18 dBm,a third order input intercept point of 0 dBm and consumes 85 mW of power from a 1.8 V supply.     

A 50 MHz-1 GHz high linearity CATV amplifier with a 0.15μm InGaAs PHEMT process

A 50 MHz-1 GHz low noise and high linearity amplifier monolithic-microwave integrated-circuit (MMIC) for cable TV is presented.A shunt AC voltage negative feedback combined with source current negative feedback is adopted to extend the bandwidth and linearity.A novel DC bias feedback is introduced to stabilize the operation point,which improved the linearity further.The circuit was fabricated with a 0.15μm InGaAs PHEMT (pseudomorphic high electron mobility transistor) process.The test was carried out in 75Ωsystems from 50 MHz to 1 GHz.The measurement results showed that it gave a small signal gain of 16.5 dB with little gain ripples of less than±1dB.An excellent noise figure of 1.7-2.9 dB is obtained in the designed band.The IIP3 is 16 dBm, which shows very good linearity.The CSO and CTB are high up to 68 dBc and 77 dBc,respectively.The chip area is 0.56 mm~2 and the power dissipation is 110 mA with a 5 V supply.It is ideally suited to cable TV systems.     

一种低于1dB噪声系数的单片集成GNSS低噪声放大器

A monolithic integrated low noise amplifier(LNA) based on a SiGe HBT process for a global navigation satellite system(GNSS) is presented. An optimizing strategy of taking parasitic capacities at the input node into consideration is adopted and a method and design equations of monolithically designing the LC load and the output impedance matching circuit are introduced. The LNA simultaneously reaches excellent noise and input/output impedance matching. The measurement results show that the LNA gives an ultra-low noise figure of 0.97 dB, a power gain of 18.6 dB and a three-order input intermodulation point of..6 dBm at the frequency of 1.575 GHz. The chip consumes 5.4 mW from a 1.8 V source and occupies 600×650 μm2 die area.     

High Power SiGe X-Band (8～10GHz) Heterojunction Bipolar Transistors and Amplifiers

Limited by increased parasitics and thermal effects as device size increases,current commercial SiGe power HBTs are difficult to operate at X-band (8～12GHz) frequencies with adequate power added efficiencies at high power levels.We find that,by changing the heterostructure and doping profile of SiGe HBTs,their power gain can be significantly improved without resorting to substantial lateral scaling.Furthermore,employing a common-base configuration with a proper doping profile instead of a common-emitter configuration improves the power gain characteristics of SiGe HBTs,thus permitting these devices to be efficiently operated at X-band frequencies.In this paper,we report the results of SiGe power HBTs and MMIC power amplifiers operating at 8～10GHz.At 10GHz,a 22.5dBm (178mW) RF output power with a concurrent gain of 7.32dB is measured at the peak power-added efficiency of 20.0%,and a maximum RF output power of 24.0dBm (250mW) is achieved from a 20 emitter finger SiGe power HBT.The demonstration of a single-stage X-band medium-power linear MMIC power amplifier is also realized at 8GHz.Employing a 10-emitter finger SiGe HBT and on-chip input and output matching passive components,a linear gain of 9.7dB,a maximum output power of 23.4dBm,and peak power added efficiency of 16% are achieved from the power amplifier.The MMIC exhibits very low distortion with 3rd order intermodulation (IM) suppression C/I of -13dBc at an output power of 21.2dBm and over 20dBm 3rd order output intercept point (OIP3).     

A 2.4GHz CMOS Monolithic Transceiver Front-End for IEEE 802.11b Wireless LAN Applications

A 2.4GHz CMOS monolithic transceiver front-end for IEEE 802.11b wireless LAN applications is presented.The receiver and transmitter are both of superheterodyne structure for good system performance.The front-end consists of five blocks:low noise amplifier,down-converter,up-converter, pre-amplifier,and LO buffer.Their input/output impedance are all on-chip matched to 50Ω except the down-converter which has open-drain outputs.The transceiver RF front-end has been implemented in a 0.18μm CMOS process.When the LNA and the down-converter are directly connected,the measured noise figure is 5.2dB,the measured available power gain 12.5dB,the input 1dB compression point -18dBm,and the third-order input intercept point -7dBm.The receiver front-end draws 13.6mA currents from the 1.8V power supply.When the up-converter and pre-amplifier are directly connected,the measured noise figure is 12.4dB,the power gain is 23.8dB,the output 1dB compression point is 15dBm,and the third-order output intercept point is 16dBm.The transmitter consumes 276mA current from the 1.8V power supply.     

A 2.1-6 GHz SiGe BiCMOS low-noise amplifier design for a multi-mode wideband receiver

正A wideband low-noise amplifier(LNA) with ESD protection for a multi-mode receiver is presented.The LNA is fabricated in a 0.18-μm SiGe BiCMOS process,covering the 2.1 to 6 GHz frequency band.After optimized noise modeling and circuit design,the measured results show that the LNA has a 12 dB gain over the entire bandwidth, the input third intercept point(IIP3) is -8 dBm at 6 GHz,and the noise figure is from 2.3 to 3.8 dB in the operating band.The overall power consumption is 8 mW at 2.5 V voltage supply.     

A novel power amplifier structure for RFID tag applications

A novel matching method between the power amplifier(PA) and antenna of an active or semi-active RFID tag is presented.A PCB dipole antenna is used as the resonance inductor of a differential power amplifier. The total PA chip area is reduced greatly to only 240×70μm~2 in a 0.18μm CMOS process due to saving two on-chip integrated inductors.Operating in class AB with a 1.8 V supply voltage and 2.45 GHz input signal,the PA shows a measured output power of 8 dBm at the 1 dB compression point.     

Design of 20-44 GHz broadband doubler MMIC

This paper presents the design and performance of a broadband millimeter-wave frequency doubler MMIC using active 0.15μm GaAs PHEMT and operating at output frequencies from 20 to 44 GHz.This chip is composed of a single ended-into differential-out active Balun,balanced FETs in push-push configuration,and a distributed amplifier. The MMIC doubler exhibits more than 4 dB conversion gain with 12 dBm of output power,and the fundamental frequency suppression is typically -20 dBc up to 44 GHz.The MMIC works at...     

A 77-100 GHz power amplifier using 0.1-μm GaAs PHEMT technology

A wideband MMIC power amplifier at W-band is reported in this letter. The four-stage MMIC, developed using 0.1 μm GaAs pseudomorphic HEMT (PHEMT) technology, demonstrated a flat small signal gain of 12.4±2 dB with a minimum saturated output power (Psat) of 14.2 dBm from 77 to 100 GHz. The typical Psat is better by 16.3 dBm with a flatness of 0.4 dB and the maximum power added efficiency is 6% between 77 and 92 GHz. This result shows that the amplifier delivers output power density of about 470 mW/mm with a total gate output periphery of 100 μm. As far as we know, it is nearly the best power density performance ever published from a single ended GaAs-based PHEMT MMIC at this frequency band.     

A 5 GHz 7.2 dB NF low power direct conversion receiver front-end with balun LNA

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted,and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor.To obtain low l/f noise and high linearity,a current mode passive mixer is preferred and realized.A current mode switching scheme can switch between high and low gain modes,and meanwhile it can not only perform good linearity but save power consumption at low gain mode.The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm~2.It achieves 35 dB conversion gain across 4.9-5.1 GHz,a noise figure of 7.2 dB and an IIP3 of -16.8 dBm,while consuming 28.4 mA from a 1.2 V power supply at high gain mode.Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.     

An RF front-end with an automatic gain control technique for a U/V band CMMB receiver

This paper presents a fully integrated RF front-end with an automatic gain control(AGC) scheme and a digitally controlled radio frequency varied gain amplifier(RFVGA) for a U/V band China Mobile Multimedia Broadcasting(CMMB) direct conversion receiver.The RFVGA provides a gain range of 50 dB with a 1.6 dB step. The adopted AGC strategy could improve immunity to adjacent channel signal,which is of importance for CMMB application.The front-end,composed of a low noise amplifier(LNA),an RFVGA,a mixer and AGC,achieves an input referred 3rd order intercept point(IIP3) of 4.9 dBm with the LNA in low gain mode and the RFVGA in medium gain mode,and a less than 4 dB double side band noise figure with both the LNA and the RFVGA in high gain mode.The proposed RF front-end is fabricated in a 0.35μm SiGe BiCMOS technology and consumes 25.6 mA from a 3.0 V power supply.     

A digitally controlled power amplifier with neutralization capacitors for Zigbee~(TM) applications

正This paper presents a single chip CMOS power amplifier with neutralization capacitors for Zigbee~(TM) system according to IEEE 802.15.4.A novel structure with digital interface is adopted,which allows the output power of a PA to be controlled by baseband signal directly,so there is no need for DAC.The neutralization capacitors will increase reverse isolation.The chip is implemented in SMIC 0.18μm CMOS technology.Measurement shows that the proposed power amplifier has a 13.5 dB power gain,3.48 dBm output power and 35.1%PAE at P_(1dB) point. The core area is 0.73×0.55 mm~2.     

输出功率-3dBm的射频发射前端在802.11g中的应用

A 2.4 GHz,direct-conversion RF transmitter front-end with an up converter and PA driver is fabricated in a 0.13μm CMOS process for the reliable transmission of 54 Mb/s OFDM signals.The front-end output power is -3 dBm while the corresponding EVM is -27 dB which is necessary for the 802.1 1g standard of EVM at-25 dB. With the adopted gain control strategy the output power changes from -14.3 to -3.7 dBm with every step 0.8 dB (20%) which covers the gain variation due to working temperature and process.A power detector indicates the output power and delivers a voltage to the baseband to control the output power.     

一种针对中国超宽带标准的CMOS PA

A 6–9 GHz ultra-wideband CMOS power amplifier (PA) for the high frequency band of China's UWB standard is proposed. Compared with the conventional band-pass filter wideband input matching methodology, the number of inductors is saved by the resistive feedback complementary amplifying topology presented. The output impendence matching network utilized is very simple but efficient at the cost of only one inductor. The measured S₂₂ far exceeds that of similar work. The PA is designed and fabricated with TSMC 0.18 μ m 1P6M RF CMOS technology. The implemented PA achieves a power gain of 10 dB with a ripple of 0.6 dB, and S₁₁ < –10 dB over 6–9 GHz, S₂₂ < –35 dB over 4–10 GHz. The measured output power at the 1 dB compression point is over 3.5 dBm from 6 to 9 GHz. The PA dissipates a total power of 21 mW from a 1.8 V power supply. The chip size is 1.1 × 0.8 mm².     

功率为16.9 dBm增益大于20 dB的InP DHBT W波段功率放大器

A two-stage MMIC power amplifier has been realized by use of a l-μm InP double heterojunction bipolar transistor(DHBT).The cascode structure,low-loss matching networks,and low-parasite cell units enhance the power gain.The optimum load impedance is determined from load-pull simulation.A coplanar waveguide transmission line is adopted for its ease of fabrication.The chip size is 1.5×1.7 mm~2 with the emitter area of 16×1μm×15μm in the output stage.Measurements show that small signal gain is more than 20 dB over 75.5-84.5 GHz and the saturated power is 16.9 dBm @ 79 GHz with gain of 15.2 dB.The high power gain makes it very suitable for medium power amplification.     

一种应用于IEEE 802.11 a_n的高线性度InGaP/GaAs功率放大器

A three-stage 4.8-6 GHz monolithic power amplifier(PA) compatible with IEEE 802.11a/n designed based on an advanced 2μm InGaP/GaAs hetero-junction bipolar transistor(HBT) process is presented.The PA integrates input matching and closed-loop power control circuits on chip.Under 3.3 V DC bias,the amplifier achieves a ~31 dB small signal gain,excellent wide band input and output matching among overall 1.2 GHz bandwidth,and up to 24.5 dBm linear output power below EVM 3%with IEEE 802.11a 64QAM OFDM input signal.     

A 4th-order reconfigurable analog baseband filter for software-defined radio applications

This paper presents a 4th-order reconfigurable analog baseband filter for software-defined radios.The design exploits an active-RC low pass filter（LPF） structure with digital assistant,which is flexible for tunability of filter characteristics,such as cut-off frequency,selectivity,type,noise,gain and power.A novel reconfigurable operational amplifier is proposed to realize the optimization of noise and scalability of power dissipation.The chip was fabricated in an SMIC 0.13μm CMOS process.The main filter and frequency calibration circuit occupy 1.8×0.8 mm² and 0.48×0.25 mm² areas,respectively.The measurement results indicate that the filter provides Butterworth and Chebyshev responses with a wide frequency tuning range from 280 kHz to 15 MHz and a gain range from 0 to 18 dB.An IIP3 of 29 dBm is achieved under a 1.2 V power supply.The input inferred noise density varies from 41 to 133 nV/（Hz）^1/2 according to a given standard,and the power consumptions are 5.46 mW for low band（from 280 kHz to 3 MHz） and 8.74 mW for high band（from 3 to 15 MHz） mode.