共查询到19条相似文献,搜索用时 296 毫秒
1.
2.
文中从通信系统的信号完整性设计和电磁兼容性设计的概念讲起,重点描述了某高速通信系统的EMC设计方法。该系统基于CPU、FPGA和DDR的核心架构,有信号频率高、交换容量大、板卡EMI指标严格的设计难点。文中在系统的EMC设计过程中重点考虑了高速信号完整性和电源完整性,有效的突破了该高速PCB设计的关键技术,并搭建了测试平台对板卡的信号完整性、电磁辐射进行了全面测试。经实验证明,文中设计的系统信号完整性与电磁兼容性性能优良,充分满足了设计要求,工作稳定可靠。 相似文献
3.
4.
5.
6.
简要阐述了DDS技术的基本原理,介绍了一种由TMS320VC5509A DSP控制器为核心的任意波形发生器.详细叙述了该波形发生器的硬件设计原理及软件设计方法.本设计具有结构简单、性能稳定、生成波形精度高及可扩展性好等优点. 相似文献
7.
8.
文章采用ZigBee协议标准组织无线传感网,将CC2530作为ZigBee模块的硬件核心,用高精度数字式温度传感器DHT11进行温度采集,选用ARM芯片Intel Xscale pxa270作为上位机核心处理器,设计了实时、高效的小型无线温度监测系统。该系统结构完整,可扩展性强,与同类产品相比,性能更加稳定,使用更加灵活。 相似文献
9.
10.
11.
基于VOQ缓存策略的信元调度算法是提升交换系统性能的关键因素。介绍了3种富有代表性的调度算法iSLIP算法、iLQF算法和DPA算法。iSLIP算法易于硬件实现,不大于log2N次迭代即可实现收敛,但对于突发通信效率不高,适用于中小规模的高速交换结构;iLQF算法调度效率高,但硬件实现较为困难,且时延较大,目前应用较少;DPA算法可以用简单的组合逻辑实现,时延小,但效率不高,适用于重载大规模的高速交换结构。 相似文献
12.
iRGRR(iterative Request-Grant-based Round-Robin)算法是一种输入排队crossbar调度算法,具有硬件易实现、可扩展性强、性能优良等优点。在此基础上,该文提出一种新的高速crossbar分组调度策略iRGRR/PM(iRGRR with Packet Mode),可以更好地支持IP分组的调度,能够被应用于高速、大容量的路由器中。与iRGRR算法相比,iRGRR/PM简化了分组输出重组模块的设计,并且提高了crossbar的带宽资源利用率。文中简单分析了两种算法间的分组时延关系,并进行了详尽的仿真研究。结果表明:在相同条件下,iRGRR/PM算法具有更高的吞吐量,尤其在非均匀业务流下能获得接近100%的吞吐量;调度长分组时,iRGRR/PM算法具有更好的时延性能。 相似文献
13.
14.
针对航天控制系统灵活性、复用性、可扩展性较差等问题,采用部分动态可重配置和软硬件协同设计等技术,设计了一种基于Microblaze软核的高带宽软件无线电(Software-defined Radio,SDR)通用一体化测试平台。该硬件平台由Kintex7 FPGA与集成式射频(Radio Frequency,RF)收发器AD9371组成,采用Microblaze软核进行功能开发,实现任务调度、功能配置和数据交互;通过Vivado实现测试平台逻辑功能开发,并将功能代码封装成FPGA IP(Intellectual Property)核;最终通过AD9371 RF收发器实现射频数据收发。测试结果表明,该通用一体化测试平台可进行高速率、高带宽数据传输。该平台具有通用性强、互联性强、易操作、易移植等特点,可广泛应用于工业、通信、军事、医疗、汽车、无人机、航天等领域。 相似文献
15.
现有的关于Clos交换结构的调度算法在关注调度性能的同时,逐渐忽略了其在硬件实现上的复杂度。该文根据一款星载交换芯片的设计实现,提出了一种改进型的Clos结构,且在此基础上设计了一种硬件实现简单且能实现极大匹配的调度算法。 相似文献
16.
目前基于单级交换结构(single-stage switch)集中式调度的路由器已经不能满足Internet网络流量、网络规模和上层应用的快速发展.近年来,旨在提高路由器可扩展性、吞吐率、QoS能力的高性能交换技术,成为路由器技术研究中的一大热点.文章从体系结构、调度策略、QoS特性三个方面对高性能交换结构研究进展进行了综述,以可扩展性、实现复杂度、延迟和吞吐率保证、负载均衡及报文乱序为主要衡量指标分析比较了每一类交换结构调度算法的性能,最后提出下一步的研究课题和思路. 相似文献
17.
This paper proposes two almost all-optical packet switch architectures, called the “packing switch” and the “scheduling switch” architecture, which when combined with appropriate wait-for-reservation or tell-and-go connection and how control protocols provide lossless communication for traffic that satisfies certain smoothness properties. Both switch architectures preserve the order of packets that use a given input-output pair, and are consistent with virtual circuit switching, The scheduling switch requires 2klogT+k2 two-state elementary switches (or 2klogT+2klogk elementary switches, if a different version is used) where k is the number of inputs and T is a parameter that measures the allowed burstiness of the traffic. The packing switch requires very little processing of the packet header, and uses k2logT+klogk two-state switches. We also examine the suitability of the proposed architectures for the design of circuit switched networks. We find that the scheduling switch combines low hardware cost with little processing requirements at the nodes, and is an attractive architecture for both packet-switched and circuit-switched high-speed networks 相似文献
18.
Providing quality-of-service guarantees in both cell- and packet-based networks requires the use of a scheduling algorithm in the switches and network interfaces. These algorithms need to be implemented in hardware in a high-speed switch. The authors present a number of approaches to implement scheduling algorithms in hardware. They begin by presenting a general methodology for the design of timestamp-based fair queuing algorithms that provide the same bounds on end-to-end delay and fairness as those of weighted fair queuing, yet have efficient hardware implementations. Based on this general methodology, the authors describe two specific algorithms, frame-based fair queuing and starting potential-based fair queuing, and discuss illustrative implementations in hardware. These algorithms may be used in both cell switches and packet switches with variable-size packets. A methodology for combining a traffic shaper with this class of fair queuing schedulers is also presented for use in network interface devices, such as an ATM segmentation and reassembly device 相似文献
19.
We introduce a new approach to ATM switching. We propose an ATM switch architecture which uses only a single shift-register-type buffering element to store and queue cells, and within the same (physical) queue, switches the cells by organizing them in logical queues destined for different output lines. The buffer is also a sequencer which allows flexible ordering of the cells in each logical queue to achieve any appropriate scheduling algorithm. This switch is proposed for use as the building block of large-stale multistage ATM switches because of low hardware complexity and flexibility in providing (per-VC) scheduling among the cells. The switch can also be used as scheduler/controller for RAM-based switches. The single-queue switch implements output queueing and performs full buffer sharing. The hardware complexity is low. The number of input and output lines can vary independently without affecting the switch core. The size of the buffering space can be increased simply by cascading the buffering elements 相似文献