光纤Bragg光栅液氦环境下温度传感特性的研究

进行了液氦温度(4.2 K)到室温(298 K)温区内光纤Bragg光栅(FBG)温度传感性能的实验研究.重点分析了液氦温度(4.2 K)到液氮温度(77 K)FBG的温度传感特性.实验表明:FBG传感特性与温度相关.在50 K以下,温度响应基本没有变化;50 K-77 K,波长偏移量随温度上升变化不规律;150 K-298 K传感特性近似成线性.对比裸光栅与涂敷光栅,涂敷光栅的温度灵敏度远大于裸光栅的温度灵敏度.选用外加热膨胀系数大的聚合物封装,可以显著提高FBG的温敏系数和线性度.     

A low-power charge-recycling ROM architecture

This paper describes a newly proposed low-power charge-recycling read-only memory (CR-ROM) architecture. The CR-ROM reduces the power consumption in bit lines, word lines, and precharge lines by recycling the previously used charge. In the proposed CR-ROM, bit-line swing voltage is lowered by the charge recycling between bit lines. When N bit lines recycle their charges, the swing voltage and the power of the bit lines become 1/N and 1/N/sup 2/ compared to the conventional ROMs, respectively. As the number of N increases, the power saving in bit lines becomes salient. Also, power consumption in word lines and precharge lines can be reduced theoretically to half by the proposed charge-recycling techniques. The simulation results show that the CR-ROM consumes 60%/spl sim/85% of the conventional low-power ROMs with 1 K /spl times/ 32 b. A CR-ROM with 32 Kb was implemented in a 0.35-/spl mu/m CMOS process. The power dissipation is 6.60 mW at 100 MHz with 3.3 V and the maximum operating clock frequency is 150 MHz.     

A 32 K ASIC synchronous RAM using a two-transistor basic cell

A 32 K synchronous RAM using a two-transistor basic cell has been developed for use with a 100 K compact gate array. The basic cell consists of only two transfer gates and a storage capacitor and thus results in a very dense memory array. The RAM operates as a static RAM during system operations and provides both serial and parallel data ports. It can be reconfigured into 1 K×32, 2 K×16, 4 K×8, etc. depending on the system needs. An access time of 40 ns was achieved for a test chip at an operating power of 175 mW     

Highly reliable and high-yield 1300-nm InGaAlAs directly modulated ridge fabry-Perot lasers, operating at 10-gb/s, up to 110/spl deg/C, with constant current swing

Transceivers for 300-m multimode links, based on a serial 10-Gb/s laser source and incorporating a receiver based on electronic dispersion compensation (EDC), are creating the first high-volume application for a 10-Gb Fabry-Perot (FP). A highly reliable and high-yield uncooled ridge FP laser is presented. The device shows excellent power characteristics in the 25/spl divide/150/spl deg/C temperature range with very high T/sub 0/ (95 K in the temperature range 0/spl divide/85/spl deg/C and still 78 K at 150/spl deg/C). Outstanding dynamic performances are also shown: 6 dB of extinction ratio can be achieved up to 110/spl deg/C by using a constant current swing of 50 mA. Because of their enhanced performances, these devices have enabled single temperature setting of the optical module, leading to a significant test cost reduction.     

A 288K CMOS EPROM with redundancy

A 150 ns 288K CMOS EPROM with a nine-block cell array and a standby current of less than 1 /spl mu/A has been developed. This device can be used as an 8 or 9-bit EPROM. The ninth block can be used as a redundant block by electrically programmable polysilicon fuses. A redundant row decoder is also included. Improvements in the lithography and process technologies have reduced the cell size to 9 /spl times/ 6 /spl mu/m and the chip size to 7.44 /spl times/ 4.65 mm.     

A bipolar 18K-gate variable size cell masterslice

An emitter-coupled logic (ECL) 100K compatible 18K-gate masterslice has been developed. A variable-size-cell (VSC) approach is proposed to reduce nonutilized elements in the ECL gate array. The concept of the VSC is to implement logic circuitry not by the usual macrocells but by newly developed cellular units. The unit is constructed using three transistors and four polysilicon resistors. By utilizing 1.2-/spl mu/m salicide base contact technology, the intrinsic gate delay is 150 ps at a power consumption of 2.4 mW. A 32-bit multiplier has been implemented as an application. Compared with conventional cell structures, a 20% higher effective gate density is achieved.     

Wafer-scale 3D integration of InGaAs photodiode arrays with Si readout circuits by oxide bonding and through-oxide vias

A new wafer-scale three dimensional (3D) integration technique, originally developed for Si, is applied to hybridize InP-based photodiode arrays with Si readout circuits. The infrared (IR) photodiodes consisted of an InGaAs absorption layer grown on the InP substrate and were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits to allow 3D integration in the Si fabrication facility. The finished 150-mm-diameter InP wafer was directly bonded to the SOI wafer and interconnected to the Si readout circuits by through-oxide vias (TOV). A 32 × 32 array with 6-μm pixel size was demonstrated. The 3D integration of InP with Si wafers achieved the smallest pixel size, which is less than a half of that can be achieved using conventional flip-chip bump bonding technique.     

A fault-tolerant 64K dynamic random-access memory

A 64K dynamic MOS RAM with features and performance fully compatible with current 16K RAM's has been designed and characterized. The memory cell is a one-transistor-one-capacitor structure, standard except for a polysilicon bit line. A dual-32K architecture, along with partial selection and stepped recovery, holds power and peak current values below those of 16K parts. Spare rows and columns, which can be substituted for defective elements by the laser opening of polysilicon links, enhance yield. Worst case column enable access time of the memory is 100 ns, row enable access time is 170 ns, and only 128 cycles within 4 ms are needed to refresh the device.     

机械制冷机冷却的透射式光学系统支撑结构

低温光学能够降低红外光学系统自身热噪声,有效提高探测灵敏度。支撑结构是实现光学系统在低温下正常工作的关键部件。设计的透射式低温光学系统工作温度为150 K,采用脉冲管制冷机这种新型机械式低温制冷机做冷源。因制冷机冷指直径较小,直接冷却光学透镜会在透镜内部产生较大温差,影响成像质量,为此设计了一种新型支撑结构,一方面设计了新型的轴向支撑和径向支撑用来减少透镜在低温下的形变,另一方面建立了透镜与脉冲管制冷机之间的传热模型,来指导支撑结构热设计,减小透镜内部温差。最后,对透镜支撑的低温性能进行了测试,实验结果表明,经过3 h,透镜温度由300 K降至150 K,支撑结构很好地保护了透镜并且在降温过程中透镜内部温差小于1 K。当温度从300 K降低到150 K时,光学表面的最大变形小于1（1=632.8 nm）。支撑结构从机械和热学性能上满足了低温光学系统的需要,为机械式制冷机冷却光学系统的光机结构设计提供了一种新选择。     

An 80 ns 32K EEPROM using the FETMOS cell

A 32K bit EEPROM using the FETMOS (floating-gate electron tunneling MOS) cell has achieved a typical access time of 80 ns and a die size of 20.6 mm/SUP 2/ using approximately 3 /spl mu/m feature sizes. The device has many built-in ease of use and ease of test features, including multimode erase (word, page, and bulk), bulk `O' program, latched inputs for program and erase operation, nonlocked high voltage supply, and margin test capability for both programmed and erased states. A unique TPP (transparent-partial programming) yield enhancement technique, using polysilicon fuse programming, can convert partially good 32K dice into totally good 16K and 8K devices.     

Palladium-silicide Schottky-barrier IR-CCD for SWIR applications at intermediate temperatures

A new 32 × 63 element palladium-silicide Schottky-barrier IR-CCD device is described. The device can be operated from 40 to 140K and is sensitive in the 1.0 to 3.5 µm SWIR spectral range. A typical value of the quantum efficiency coefficient is 19.1%/eV. The photoelectric barrier height is 0.34 eV.     

Parallel and pipelined VLSI implementation of a staged decoder for BCM signals

This paper is devoted to VLSI implementation of a staged decoder for Block-Coded Modulation (BCM). We first review a general parallel and pipelined implementation of the decoder and we identify the parameters to be considered for optimization. A particular BCM scheme, based on the 8-PSK signal set, is chosen for a case study. Several ideas are described leading to a code-optimized design, and hardware implementation is shown. Next, we evaluate the performance of our design. In particular it is shown that, by exploiting regularity, a simple structure which achieves a throughput rate of 10 Mbps can be implemented by using 23 K transistors and 2 standard cells CMOS technology. Further optimization and simple stacking of ten processors on a single chip in a block-processing structure allows us to achieve a throughput rate of 100 Mbps with about 150 K transistors (38 K gates).     

一种用于音频DAC的可重构∑-△调制器的设计

设计了一种适于嵌入式FPGA应用的可重构Σ-Δ调制器,并采用高效的流水线结构实现,它能够被设置为3阶或5阶,可支持不同字长（16-/18-/20-/24-位）PCM数据的满幅输入。通过Matlab仿真,针对16位、44.1 kHz、过采样率为128的输入信号,工作在三阶情况下的调制器可以获得超过100 dB的信噪比（SNR）;而在输入为24位1、92 kHz、过采样率为32时,工作在5阶情况下的调制器的信噪比（SNR）超过了150 dB,很好地抑制了通带内的噪声。     

A 350GHz Radial-Probe SIS Mixer for Astronomical Imaging Arrays

We have developed a 330-370GHz SIS mixer for small-format, heterodyne, astronomical imaging arrays. Fixed-tuned broadband operation is achieved by means of a superconducting radial waveguide probe. A horn-reflector antenna provides high-efficiency optical coupling. Using a variable-temperature cryogenic noise source, we measured a DSB system noise temperature of 32±1K. The mixer contributes 3±3K, supporting the theoretically-predicted result that the noise temperature of a DSB mixer can be less than hω/2κ (8.6K)     

Charge transport in superlattices with low-strength barriers and the problem of a terahertz bloch oscillator

Charge-transport properties of superlattices with low-strength barriers and the possibility of designing a Bloch oscillator based on these superlattices are discussed. A terahertz Bloch oscillator based on n-GaAs-GaAlAs structures with low-strength barriers is suggested. Because of interminiband tunneling, the current is an increasing function of electric-field strength, so that domains cannot be formed. At the same time, tunneling and Bloch oscillations give rise to dynamic negative electrical conductivity in the terahertz region. Monte Carlo simulations show that dynamic negative conductivity exists in the frequency range of 1–7 THz for superlattices with moderate charge-carrier mobility at 77 K. A Bloch oscillator should include a superlattice with 350–700 periods of 150-Å, with this superlattice being sandwiched between contact regions, which are in fact strip-line sections (the oscillator cavity). Presumably, such an oscillator can operate at 77 K in the continuous-wave mode.     

Type-II interband cascade lasers in the 4.3-4.7-/spl mu/m wavelength region

Operation of type-II interband cascade lasers in the 4.3-4.7-/spl mu/m wavelength region has been demonstrated at temperatures up to 240 K in pulsed mode. These lasers fabricated with 150-/spl mu/m-wide mesa stripes operated in continuous-wave (CW) mode up to a maximum temperature of 110 K, with an output power exceeding 30 mW/f and a threshold current density of about 41 A/cm/sup 2/ at 90 K. The maximum CW operation temperature of 110 K is largely limited by the high specific thermal resistance of the 150-/spl mu/m-wide broad area lasers. A 20-/spl mu/m-wide mesa stripe laser was able to operate in CW mode at higher temperatures up to 125 K as a result of the reduced specific thermal resistance of a smaller device.     

Determination of a nonlinear parameter for acoustic-surface-wave convolution in LiNbO3

A 1-dimensional, single-parameter model is used to calculate the voltage induced by two acoustic surface waves propagating in opposite directions in a nonlinear material. A value of the single parameter for LiNbO3 is found to be K = 8±3 C/m2 from experiment at 150 MHz.     

Characterization and modeling of quantum cascade lasers based on aphoton-assisted tunneling transition

A detailed characterization and modeling of long-wavelength (λ~10 μm) quantum cascade (QC) lasers based on a photon-assisted tunneling transition are presented. In particular, the influence of the finite lifetime of the lower state of the laser transition on the current-voltage and threshold current versus temperature characteristics have been studied both theoretically and experimentally. It is shown that, for our structure, the value of the lower state lifetime can be extracted from the voltage-current curve; the value we found was 2.6 ps. In addition, this model allows to understand the abrupt degradation of the performance of the device for T>150 K. Low temperature (T=10 K) threshold current densities of 1.1 kA/cm² and a tuning range of 85 cm^-1 in pulsed mode are reported. In continuous-wave mode, the emission linewidth of a free-running laser was determined to be 3.9 MHz     

一种透射式低温光学系统的设计与验证

由于能够减小系统自身的热噪声和提高系统信噪比,低温光学是实现高灵敏度红外探测的必要手段。提出了一种将脉冲管制冷机用作冷源的透射式低温光学系统。这种新型低温光学系统可用于体积和重量受限而又需要进行高灵敏度红外探测的场合。从光学设计、光机结构设计和内部热噪声分析等方面说明了透射式低温光学系统的设计过程。搭建了用于对脉冲管制冷机冷却光学系统的可行性进行验证的试验系统,并从系统内部热噪声的角度对低温光学的有效性进行了验证。实验结果表明,经过3 h,透镜温度由300 K降至设计温度150 K,继续降温则可达到最低温度105 K。测试过程中,透镜保持完好,验证了将脉冲管制冷机用作冷源的可行性。用黑体和320×256元碲镉汞探测器对光学系统自身的热噪声进行了测试。结果表明,当光学系统的温度从300 K降至215 K时,其自身热辐射减少了75%。这与理论分析结果一致,验证了低温光学降噪的有效性。     

Analysis of read speed latency in 6T-SRAM cell using multi-layered graphene nanoribbon and cu based nano-interconnects for high performance memory circuit design

In this study, we designed a 6T-SRAM cell using 16-nm CMOS process and analyzed the performance in terms of read-speed latency. The temperature-dependent Cu and multilayered graphene nanoribbon (MLGNR)-based nano-interconnect materials is used throughout the circuit (primarily bit/bit-bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano-interconnects with different interconnect lengths (from 10 μm to 100 μm), for reading-0 and reading-1 operations. To execute the reading operation, the CMOS technology, that is, the16-nm PTM-HPC model, and the16-nm interconnect technology, that is, ITRS-13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high-speed memories using different nano-interconnect materials.