Hole confinement and low-frequency noise in SiGe pFETs onsilicon-on-sapphire

We present the dc, ac, and low-frequency noise characteristics of SiGe channel pFETs on silicon-on-sapphire (SOS). The SiGe pFETs show higher mobility, transconductance, and cutoff frequency compared to the Si control devices. A significant reduction in low-frequency (1/f) noise is observed in the SiGe pFETs, and understood to be the result of a lower border trap density sampled at the Fermi-level due to the valence band offset. The linear g_m of the SiGe pFET's at 85 K shows a secondary peak which is attributed to the turn-on of the surface channel     

High performance 0.1 μm gate-length p-type SiGe MODFET's andMOS-MODFET's

High performance p-type modulation-doped field-effect transistors (MODFET's) and metal-oxide-semiconductor MODFET (MOS-MODFET) with 0.1 μm gate-length have been fabricated on a high hole mobility SiGe-Si heterojunction grown by ultrahigh vacuum chemical vapor deposition. The MODFET devices exhibited an extrinsic transconductance (g_m) of 142 mS/mm, a unity current gain cut-off frequency (f_T) of 45 GHz and a maximum oscillation frequency (f_MAX) of 81 GHz, 5 nm-thick high quality jet-vapor-deposited (JVD) SiO₂ was utilized as gate dielectric for the MOS-MODFET's. The devices exhibited a lower gate leakage current (1 nA/μm at V_gs=6 V) and a wider gate operating voltage swing in comparison to the MODFET's. However, due to the larger gate-to-channel distance and the existence of a parasitic surface channel, MOS-MODFET's demonstrated a smaller peak g _m of 90 mS/mm, f_T of 38 GHz, and f_max of 64 GHz. The threshold voltage shifted from 0.45 V for MODFET's to 1.33 V for MOS-MODFET's. A minimum noise figure (NF_min) of 1.29 dB and an associated power gain (G_a) of 12.8 dB were measured at 2 GHz for MODFET's, while the MOS-MODFET's exhibited a NF _min of 0.92 dB and a G_a of 12 dB at 2 GHz. These DC, RF, and high frequency noise characteristics make SiGe/Si MODFET's and MOS-MODFET's excellent candidates for wireless communications     

High speed p-type SiGe modulation-doped field-effect transistors

We report on the fabrication and characterization of high-speed p-type modulation-doped field-effect transistors (MODFETs) with 0.7-μm and 1-μm gate-lengths having unity current-gain cut-off frequencies (f_T) of 9.5 GHz and 5.3 GHz, respectively. The devices were fabricated on a high hole mobility SiGe heterostructure grown by ultra-high-vacuum chemical vapor deposition (UHV-CVD). The dc maximum extrinsic transconductance (g_m) is 105 mS/mm (205 mS/mm) at room temperature (77 K) for the 0.7-μm gate length devices. The fabricated devices show good pinch-off characteristics and have a very low gate leakage current of a few μA/mm at room temperature and a few nA/mm at 77 K     

Threshold voltage roll-up/roll-off characteristic control insub-0.2-μm single workfunction gate CMOS for high-performance DRAMapplications

Threshold voltage (V_t) roll-off/roll-up control is a key issue to achieve high-performance sub-0.2-μm single workfunction gate CMOS devices for high-speed DRAM applications. It is experimentally confirmed that a combination of well RTA and N₂ implant prior to gate oxidation is important to reduce V_t roll-up characteristics both in nFET and pFET. Optimization of RTA conditions after source/drain (S/D) implant is also discussed as a means of improving V_t roll-off characteristics. Finally, the impact of halo implant on V_t variation in sub-0.2-μm buried channel pFETs is discussed. It is found that halo profile control is necessary for tight V_t variation in sub-0.2-μm single workfunction gate pFET     

Evaluation of NBTI in HfO/sub 2/ gate-dielectric stacks with tungsten gates

Negative-bias temperature instability (NBTI) of the threshold voltage in ultrathin HfO/sub 2/ p-type field-effect transistors (pFET) with tungsten gates is reported. The dependence of threshold voltage, transconductance peak, and interface trap density on stress time is investigated for various negative stress voltages and temperatures. The measurements show that the threshold voltage shifts with a concomitant decrease in transconductance peak and increase in interface trap density as assessed by subthreshold slope and dc current-voltage (DCIV) method. The threshold voltage shift data are fitted with a stretched exponential equation and the fits are used for estimating lifetime. The measurements show that NBTI-related degradation in HfO/sub 2/ stacks is comparable to that observed in SiO/sub 2//poly Si pFETs.     

Fabrication and mobility characteristics of SiGe surface channel pMOSFETs with a HfO/sub 2//TiN gate stack

This paper describes an extensive experimental study of TiN/HfO/sub 2//SiGe and TiN/HfO/sub 2//Si cap/SiGe gate stacked-transistors. Through a careful analysis of the interface quality (interface states and roughness), we demonstrate that an ultrathin silicon cap is mandatory to obtain high hole mobility enhancement. Based on quantum mechanical simulations and capacitance-voltage characterization, we show that this silicon cap is not contributing any silicon parasitic channel conduction and degrades by only 1 /spl Aring/ the electrical oxide thickness in inversion. Due to this interface optimization, Si/sub 0.72/Ge/sub 0.28/ pMOSFETs exhibit a 58% higher mobility at high effective field (1 MV/cm) than the universal SiO/sub 2//Si reference and a 90% higher mobility than the HfO/sub 2//Si reference. This represents one of the best hole mobility results at 1 MV/cm ever reported with a high-/spl kappa//metal gate stack. We thus validate a possible solution to drastically improve the hole mobility in Si MOSFETs with high-/spl kappa/ gate dielectrics.     

Impact ionization suppression by quantum confinement: Effects onthe DC and microwave performance of narrow-gap channel InAs/AlSb HFET's

InAs/AlSb heterostructure field-effect transistors (HFET's) are subject to impact ionization induced short-channel effects because of the narrow InAs channel energy gap. In principle, the effective energy gap to overcome for impact ionization can be increased by quantum confinement (channel quantization) to alleviate impact ionization related nonidealities such as the kink effect and a high gate leakage current. We have studied the effects of quantum well thickness on the dc and microwave performance of narrow-gap InAs/AlSb HFET's fabricated on nominally identical epitaxial layers which differ only by their quantum well thickness. We show that a thinner quantum well postpones the onset of impact ionization and suppresses short-channel effects. As expected, the output conductance g_DS and the gate leakage current are reduced. The f_MAX/f_T ratio is also significantly improved when the InAs well thickness is reduced from 100 to 50 Å. The use of the thinner well reduces the cutoff frequency f_T, the transconductance g_m, and the current drive because of the reduced low-field mobility due to interface roughness scattering in thin InAs/AlSb channel layers: the low-field mobility was μ=21 000 and 9000 cm²/Vs for the 100- and 50-Å quantum wells, respectively. To our knowledge, the present work is the first study of the link between channel quantization, in-plane impact ionization, and device performance in narrow-gap channel HFET's     

RF and Logic Performance Improvement of $ hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}/hbox{InAs}/hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ Composite-Channel HEMT Using Gate-Sinking Technology

Eighty-nanometer-gate In_0.7Ga_0.3As/InAs/In_0.7Ga_0.3As composite-channel high-electron mobility transistors (HEMTs), which are fabricated using platinum buried gate as the Schottky contact metal, were evaluated for RF and logic application. After gate sinking at 250degC for 3 min, the device exhibited a high g_m value of 1590 mS/mm at V_d = 0.5 V, the current-gain cutoff frequency f_T was increased from 390 to 494 GHz, and the gate-delay time was decreased from 0.83 to 0.78 ps at supply voltage of 0.6 V. This is the highest f_T achieved for 80-nm-gate-length HEMT devices. These superior performances are attributed to the reduction of distance between gate and channel and the reduction of parasitic gate capacitances during the gate-sinking process. Moreover, such superior performances were achieved through a very simple and straightforward fabrication process with optimal epistructure of the device.     

Optimization of gate-to-drain separation in submicron gate-lengthmodulation doped FET's for maximum power gain performance

This paper analyzes the effects of the separation between the gate and the drain electrodes on the high-frequency performance limitations of heterostructure MODFET's. Based on the effective gate-length and carrier velocity saturation concepts first the key small-signal equivalent network model parameters of the MODFET are calculated. The concept of open-circuit voltage gain, defined as the transconductance to output conductance ratio (g_m/g_o), has been exploited to determine the output conductance with a knowledge of the static electric field and potential at the edge of the gate on the drain side. By treating the c_oμ_n product as a function of the gate voltage, the drain current-voltage and transconductance characteristics have been effectively modeled for practical devices. By combining the effects of the intrinsic and parasitic equivalent network parameters this paper has determined the dependence of the g_m/g_o ratio, the gate capacitance to the feedback capacitance ratio, the unity current gain frequency (f_r) and the maximum frequency of oscillations (f _max) on the gate-to-drain separation (L_gd). MODFET's based on InAlAs/InGaAs heterostructures lattice-matched to InP substrate with gate-length values of 0.25 μm, 0.15 μm and 0.1 μm are considered for analyses. The optimum values of L_gd calculated are 600 Å, 420 Å, and 340 Å for the corresponding maximum f_max-values of 250, 370, and 480 GHz, respectively     

A novel InGaAs/InAlAs insulated gate pseudomorphic HEMT with asilicon interface control layer showing high DC- and RF-performance

A novel InGaAs/InAlAs insulated gate pseudomorphic HEMT (IG-PHEMT) utilizing a silicon interface control layer (Si ICL) was successfully fabricated and its DC and RF performances were characterized. The device showed high transconductance of 177 mS/mm even for a gate length of 1.6 μm. As compared with the conventional Schottky gate PHEMTs, the gate leakage current was reduced by 4 orders of magnitudes and the gate breakdown voltage was increased up to 39 V. Well-behaved RF characteristics with the current gain cutoff frequency, f_T, of 9 GHz and the maximum oscillation frequency, f_max, of 38 GHz were obtained for the 1.6 μm-gate-length device     

Recessed-gate AlGaAs-InGaAs-GaAs pseudomorphic HEMT withSi-planar-doped etch stop layer

An improved slot etch technique based on an Si planar doped layer has been applied to gate recessing in the fabrication of AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistors (HEMTs). The devices exhibited comparable g_m with much better breakdown and leakage behaviour than conventional pseudomorphic HEMT devices     

Delta-doped AlGaN/AlN/GaN microwave HFETs grown by metalorganicchemical vapour deposition

The performance of an innovative delta-doped AlGaN/AlN/GaN heterojunction field-effect transistor (HFET) structure is reported. The epitaxial heterostructures were grown on semi-insulating SiC substrates by low-pressure metalorganic chemical vapour deposition. These structures exhibit a maximum carrier mobility of 1058 cm²/V s and a sheet carrier density of 2.35×10¹³ cm^-2 at room temperature, corresponding to a large n_s μ_n product of 2.49×10¹⁶ V s. HFET devices with 0.25 μm gate length were fabricated and exhibited a maximum current density as high as 1.5 A/mm (at V_G=+1 V) and a peak transconductance of g_m=240 mS/mm. High-frequency device measurements yielded a cutoff frequency of f_t≃50 GHz and maximum oscillation frequency f_max≃130 GHz     

0.3 dB minimum noise figure at 2.5 GHz of 0.13 μm Si/Si0.58Ge0.42 n-MODFETs

RF and microwave noise performances of strained Si/Si_0.58 Ge_0.42 n-MODFETs are presented for the first time. The 0.13 μm gate devices have de-embedded f_T=49 GHz, f_max =70 GHz and a record intrinsic g_m=700 mS/mm. A de-embedded minimum noise figure NF_min=0.3 dB with a 41 Ω noise resistance R_n and a 19 dB associated gain G_ass are obtained at 2.5 GHz, while NF_min=2.0 dB with G_ass=10 dB at 18 GHz. The noise parameters measured up to 18 GHz and from 10 to 180 mA/mm with high gain and low power dissipation show the potential of SiGe MODFETs for mobile communications     

Undoped epitaxial Si channel n-MOSFET grown by UHV-CVD withpreheating

Undoped epitaxial channel n-MOSFET with high transconductance was developed. In order to obtain a good crystal quality of the epitaxial layer and, thus, to achieve high performance, it is important to reduce the oxygen concentration at the epitaxial Si/Si substrate interface. In this paper, we describe the relationship between the electrical characteristics and the surface density of oxygen at the epitaxial Si/Si substrate. We also describe the dependence of the electrical characteristics on epitaxial Si thickness. The g_m of n-MOSFET with 40-nm epitaxial Si for 0.10-μm gate length was 630 mS/mm at V _d-1.5 V, and the drain current was 0.77 mA/μm. This g_m value in the case of the epitaxial Si channel is about 20% larger than that of bulk the MOSFET. These results show that epitaxial Si channel MOSFET's are useful for future high-speed ULSI devices     

应变Si1-xGex沟道PMOSFET空穴局域化研究

为充分利用应变 Si Ge材料相对于 Si较高的空穴迁移率 ,研究了 Si/Si Ge/Si PMOSFET中垂直结构和参数同沟道开启及空穴分布之间的依赖关系。在理论分析的基础上 ,以数值模拟为手段 ,研究了栅氧化层厚度、Si帽层厚度、Si Ge层 Ge组分及厚度、缓冲层厚度及衬底掺杂浓度对阈值电压、交越电压和空穴分布的影响与作用 ,特别强调了 δ掺杂的意义。模拟和分析表明 ,栅氧化层厚度、Si帽层厚度、Si Ge层 Ge组分、衬底掺杂浓度及 δ掺杂剂量是决定空穴分布的主要因素 ,而 Si Ge层厚度、缓冲层厚度和隔离层厚度对空穴分布并不敏感。最后总结了沟道反型及空穴分布随垂直结构及参数变化的一般规律 ,为优化器件设计提供了参考。     

Tensile-Strained Germanium CMOS Integration on Silicon

Monolithic integration of tensile-strained Si/ Germanium (Ge)-channel n-MOS and tensile-strained Ge p-MOS with ultrathin (equivalent oxide thickness ~14 Aring) HfO₂ gate dielectric and TaN gate stack on Si substrate is demonstrated. Defect-free Ge layer (279 nm) grown by ultrahigh vacuum chemical-vapor deposition is achieved using a two-step Ge-growth technique coupled with compliant Si/SiGe buffer layers. The epi-Ge layer experiences tensile strain of up to ~0.67% and exhibits a peak hole mobility of 250 cm²/V ldr s which is 100% higher than the universal Si hole mobility. The gate leakage current is two orders of magnitude lower compared to the reported results on Ge bulk.     

DC and RF performance of 0.25 μm p-type SiGe MODFET

The DC and RF performance of a 0.25 μm gate-length p-type SiGe modulation-doped field-effect transistor (MODFET) is reported. The hole channel consists of compressively strained Si_0.3Ge_0.7 layer grown on a relaxed Si_0.7Ge_0.3 buffer on a Si substrate. The combination of high-hole mobility, low-gate leakage current, and improved ohmic contact metallization results in an enhancement of the DC and RF performance. A maximum extrinsic transconductance (g(m_ext)) of 230 mS/mm was measured. A unity current gain cut-off frequency (fT) of 24 GHz and a maximum frequency of oscillation (f_max) of 37 GHz were obtained for these devices     

Thickness Dependence of Hole Mobility in Ultrathin SiGe-Channel p-MOSFETs

A fundamental understanding of the mechanisms responsible for the dependence of hole mobility on SiGe channel layer thickness is presented for channel thicknesses down to 1.8 nm. This understanding is critical to the design of strained SiGe p-MOSFETs, as lattice mismatch limits the thickness of SiGe that can be grown on Si and as Ge outdiffusion during processing reduces the Ge fraction. Temperature-dependent measurements are used to extract the phonon-limited mobility as a function of SiGe channel thickness for strained Si_0.57Ge_0.43 heterostructures on bulk Si. The hole mobility is shown to degrade significantly for channel thickness below 4 nm due to a combination of phonon and interface scattering. Due to the finite nature of the quantum-well barrier, SiGe film thickness fluctuation scattering is not significant in this structure for channel thickness greater than 2.8 nm.     

深亚微米应变SiGe沟PMOSFET特性模拟

为研究深亚微米尺度下应变 Si Ge沟改进 PMOSFET器件性能的有效性 ,运用二维数值模拟程序MEDICI模拟和分析了 0 .1 8μm有效沟长 Si Ge PMOS及 Si PMOS器件特性。Si Ge PMOS垂直方向采用 Si/Si Ge/Si结构 ,横向结构同常规 PMOS,N+ -poly栅结合 P型δ掺杂层获得了合理阈值电压及空穴局域化。研究表明 ,经适当设计的 Si Ge PMOS比对应 Si PMOS的 IDmax、gm、f T均提高 1 0 0 %以上 ,表明深亚微米尺度 Si Ge沟PMOSFET具有很大的性能提高潜力     

Metamorphic In0.4Al0.6As/In0.4Ga0.6As HEMTs on GaAs substrate

New In_0.4Al_0.6As/In_0.4Ga_0.6 As metamorphic (MM) high electron mobility transistors (HEMTs) have been successfully fabricated on GaAs substrate with T-shaped gate lengths varying from 0.1 to 0.25 μm. The Schottky characteristics are a forward turn-on voltage of 0.7 V and a gate breakdown voltage of -10.5 V. These new MM-HEMTs exhibit typical drain currents of 600 mA/mm and extrinsic transconductance superior to 720 mS/mm. An extrinsic current cutoff frequency f_T of 195 GHz is achieved with the 0.1-μm gate length device. These results are the first reported for In_0.4 Al_0.6As/In_0.4Ga_0.6As MM-HEMTs on GaAs substrate