Influence of Ballistic Effects in Ultra-Small MOSFETs

Single Gate (SG) and Double Gate (DG) MOSFETs with strained and unstrained Si channel are studied using semi-classical Monte Carlo simulation to investigate the influence of ballistic electrons. We analyze how the intrinsic ballisticity B_int, directly deduced from accurate counting of scattering events undergone by carriers in the channel, depends on channel length, channel doping, strain, MOS architectures and bias. Besides, we show that the intrinsic ballisticity B_int seems to be a relevant parameter to explain the performance of small devices. It is highlighted that in undoped channels shorter than 50 nm, quasi-ballistic effects are responsible for a significant improvement in the on-current. However, for channel length smaller than about 30 nm (B_int > 20%) the current tends to the ballistic limit and the increase in intrinsic ballisticity has a decreasing impact on the current.     

Thermal noise in nanometric DG-MOSFET

The noise performance of double-gated (DG) and single-gated (SG) MOSFETs is compared. We observe a significant improvement of the noise figure (NF) in the DG structure, which is explained in terms of a favorable increase of cross-correlation between the drain and gate currents. Finally, we showed that the presence of a residual P-type impurity in the channel of a DG structure induces noticeable changes in the spectral density of the gate current fluctuations that is reflected on the noise figure.     

Uncoupled mode space approach for analysis of nanoscale strained junctionless double-gate MOSFET

In this paper, we have analyzed the electrical characteristics of Strained Junctionless Double-Gate MOSFET (Strained JL DG MOSFET). A quantum mechanical transport approach based on non-equilibrium Green’s function (NEGF) method with the use of uncoupled mode space approach has been employed for this analysis. We have investigated the effects of high-\(\kappa \) materials as gate and spacer dielectrics on the device performance. Low OFF-state current, low DIBL, and low subthreshold slope have been obtained with increase in the gate and spacer dielectric constants. The electrical characteristics of strained JL DG MOSFET have also been compared with conventional JL DG MOSFET and Inversion Mode (IM) DG MOSFET. The results indicated that the Strained JL DG MOSFET outperforms the conventional JL and IM DG MOSFETs, yielding higher values of drain current.     

Monte Carlo analysis of dynamic characteristics and high‐frequency noise performances of nanoscale double‐gate MOSFETs

In this paper, a full‐band Monte Carlo simulator is employed to study the dynamic characteristics and high‐frequency noise performances of a double‐gate (DG) metal–oxide–semiconductor field‐effect transistor (MOSFET) with 30 nm gate length. Admittance parameters (Y parameters) are calculated to characterize the dynamic response of the device. The noise behaviors of the simulated structure are studied on the basis of the spectral densities of the instantaneous current fluctuations at the drain and gate terminals, together with their cross‐correlation. Then the normalized noise parameters (P, R, and C), minimum noise figure (NF_min), and so on are employed to evaluate the noise performances. To show the outstanding radio‐frequency performances of the DG MOSFET, a single‐gate silicon‐on‐insulator MOSFET with the same gate length is also studied for comparison. The results show that the DG structure provides better dynamic characteristics and superior high‐frequency noise performances, owing to its inherent short‐channel effect immunity, better gate control ability, and lower channel noise. Copyright © 2012 John Wiley & Sons, Ltd.     

NEGF simulations of the effect of strain on scaled double gate nanoMOSFETs

The effect of biaxial strain on double gate (DG) nanoscaled Si MOSFET with channel lengths in the nanometre range is investigated using Non-Equilibrium Green’s Functions (NEGF) simulations. We have employed fully 2D NEGF simulations in order to answer the question at which body thickness the effects of strain is masked by the confinement impact. Following ITRS, we start with a 14 nm gate length DG MOSFET having a body thickness of 9 nm scaling the transistors to gate lengths of 10, 6 and 4 nm and body thicknesses of 6.1, 2.6 and 1.3 nm. The simulated I _D–V _G characteristics show a 6% improvement in the on-current for the 14 nm gate length transistor mainly due to the energy separation of the Δ valleys. The strain effect separates the 2 fold from the 4 fold valleys thus keeping mostly operational transverse electron effective mass in the transport direction. However, in the device with an extreme body thickness of 1.3 nm, the strain effect has no more impact on the DG performance because the strong confinement itself produces a large energy separation of valleys.     

Impact of channel length,gate insulator thickness,gate insulator material,and temperature on the performance of nanoscale FETs

Aggressive technology scaling as per Moore’s law has led to elevated power dissipation levels owing to an exponential increase in subthreshold leakage power. Short channel effects (SCEs) due to channel length reduction, gate insulator thickness change, application of high-k gate insulator, and temperature change in a double-gate metal–oxide–semiconductor field-effect transistor (DG MOSFET) and carbon nanotube field-effect transistor (CNTFET) were investigated in this work. Computational simulations were performed to investigate SCEs, viz. the threshold voltage (V_th) roll-off, subthreshold swing (SS), and I_on/I_off ratio, in the DG MOSFET and CNTFET while reducing the channel length. The CNTFET showed better performance than the DG MOSFET, including near-zero SCEs due to its pure ballistic transport mechanism. We also examined the threshold voltage (V_th), subthreshold swing (SS), and I_on/I_off ratio of the DG MOSFET and CNTFET with varying gate insulator thickness, gate insulator material, and temperature. Finally, we handpicked almost similar parameters for both the CNTFET and DG MOSFET and carried out performance analysis based on the simulation results. Comparative analysis of the results showed that the CNTFET provides 47.8 times more I_on/I_off ratio than the DG MOSFET. Its better control over the threshold voltage, near-zero SCEs, high on-current, low leakage power consumption, and ability to operate at high temperature make the CNTFET a viable option for use in enhanced switching applications and low-voltage digital applications in nanoelectronics.     

Directional relays without voltage sensors for distribution networks with distributed generation: Use of symmetrical components

This paper presents two local algorithms using only currents measurements that could be used as a back-up protection (after the loss of the voltage sensors) in directional relays for distribution networks with distributed generation (DG), or as additional directional relay dispatched along the feeders. These algorithms are based on the symmetrical components (0-zero, 1-positive and 2-negative sequences) of the 3-phases currents. Due to the power flows generated by the DG the positive sequence current argument is unforeseeable, thus it is not possible to use only the positive sequence. Then, we first propose in this paper an algorithm using the I₂/I₀ ratio to locate a phase-to-ground fault upstream or downstream the detector. The second algorithm measures the zero and positive sequence components of the fifth harmonic of the current and calculates the I_{0_5}/I_{1_5} ratio. The performances of these algorithms are analysed for several DG power, fault resistance, capacitive current and neutral grounding (resistive and compensative grounding). The fluctuations of the phasors measurements is also taken into account in the range ±5% for the modulus and ±5° for the argument. The present paper shows that these algorithms can be reliable in the major part of the studied cases.     

A study of threshold voltage fluctuations of nanoscale double gate metal-oxide-semiconductor field effect transistors using quantum correction simulation

In this paper, we computationally investigate fluctuations of the threshold voltage introduced by random dopants in nanoscale double gate metal-oxide-semiconductor field effect transistors (DG MOSFETs). To calculate variance of the threshold voltage of nanoscale DG MOSFETs, a quantum correction model is numerically solved with the perturbation and the monotone iterative techniques. Fluctuations of the threshold voltage resulting from the random dopant, the gate oxide thickness, the channel film thickness, the gate channel length, and the device width are calculated. Quantum mechanical and classical results have similar prediction on fluctuations of the threshold voltage with respect to different designing parameters including dimension of device geometry as well as the channel doping. Fluctuation increases when the channel doping, the channel film thickness, and/or the gate oxide thickness increase. On the other hand, it decreases when the channel length and/or the device width increase. Calculations of the quantum correction model are quantitatively higher than that of the classical estimation according to different quantum confinement effects in nanoscale DG MOSFETs. Due to good channel controllability, DG MOSFETs possess relatively lower fluctuation, compared with the fluctuation of single gate MOSFETs (less than a half of the fluctuation[-11pc] of SG MOSFETs). To reduce fluctuations of the threshold voltage, epitaxial layers on both sides of channel with different epitaxial doping are introduced. For a certain thickness of epitaxial layers, the fluctuation of the threshold voltage decreases when epitaxial doping decreases. In contrast to conventional quantum Monte Carlo approach and small signal analysis of the Schrödinger-Poisson equations, this computationally efficient approach shows acceptable accuracy and is ready for industrial technology computer-aided design application.     

An analytical model for a TFET with an n-doped channel operating in accumulation and inversion modes

The tunnel field-effect transistor (TFET) is an ambipolar device that conducts current with the channel in both accumulation and inversion modes. Analytical expressions for the channel potential and current in a TFET with an n-doped channel when operating in the accumulation and inversion modes are proposed herein. The potential model is derived by solving the two-dimensional (2D) Poisson equation using the superposition principle while considering the charges present in the channel due to electron or hole accumulation along with the depletion charges. An expression for the tunneling current corresponding to the maximum tunneling probability is also derived. The tunneling current is obtained by analytically calculating the minimum tunneling length in a TFET when operating in the accumulation or inversion mode. The results of the proposed potential model is compared with technology computer-aided design (TCAD) simulations for TFET with various dimensions, revealing good agreement. The potential and current in an n-type TFET (nTFET) obtained using the proposed models are also analyzed.

     

Silicon-Germanium Structure in Surrounding-Gate Strained Silicon Nanowire Field Effect Transistors

In this paper we numerically examine the electrical characteristics of surrounding-gate strained silicon nanowire field effect transistors (FETs) by changing the radius (R_SiGe) of silicon-germanium (SiGe) wire. Due to the higher electron mobility, the n-type FETs with strained silicon channel films do enhance driving capability (∼8% increment on the drain current) in comparison with the pure Si one. The leakage current and transfer characteristics, the threshold-voltage (V_t), the drain induced barrier height lowering (DIBL), and the gate capacitance (C_G) are estimated with respect to different gate length (L_G), gate bias (V_G), and R_SiGe. For short channel effects, such as V_t roll-off and DIBL, the surrounding-gate strained silicon nanowire FET sustains similar characteristics with the pure Si one.     

Numerical Characterization of Dosimetry,Human Body Resistance and Heart Current Resulting from Power-Frequency Touch Current for an Anatomically Realistic Human Model

Characteristics of power-frequency touch current inside an anatomically realistic human model of Japanese adult were numerically analyzed under various scenarios of current paths using a modified scalar potential finite difference (SPFD) method. Then, complex distributions of the current density in the model were visually illustrated. Results of the dosimetry of current density for excitable tissues indicates that the touch current within the reference level (0.5 mA) does not always satisfy the basic restriction of current density in the light of ICNIRP guideline for general public. Two sets of the internal body resistances R_i (i.e., 1130–1510Ω and 1460–1920Ω) are obtained, depending on the conductivity sets used. Although R_i considerably depends on the current scenario concerned, the highest values of Ri were obtained for the hand-to-hand scenario, regardless of the conductivity set. The inhomogeneous model always gives a higher value of R_i than does the homogeneous model that has a single conductivity equivalent to the weighted-average conductivity of the inhomogeneous model. It is found that the conductivity of muscle has significant influence on R_i, and that the resistance around the wrist and ankle is one of the predominant parameters to decide R_i. It is clearly shown that the current scenarios affect the pattern of the heart current flow, especially the direction of it, to a large extent. It is found that a current of 34–40% of touch current flows into the heart, and then the heart-current ratio is remarkably larger than old data. The heart-current factors of around 0.85 obtained are almost independent of the current scenarios, unlike those indicated in IEC60479-1, provided that the direction of heart current is ignored. © 2009 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

An optimal algorithm for rectilinear steiner trees for channels with obstacles

The channel rectilinear Steiner tree problem is to construct an optimal rectilinear Steiner tree interconnecting n terminals on the upper shore and the lower shore of a channel without crossing any obstacles inside the channel. However, intersecting boundaries of obstacles is allowed. We present an algorithm that computes an optimal channel rectilinear Steiner tree in O(F₁(k)n + F₂(k)) time, where k is the number of obstacles inside the channel and F₁ and F₂ are exponential functions of k. For any constant k the proposed algorithm runs in O(n) time.     

包含同步发电机及电压源逆变器接口的微网控制策略

分布式电源(distributed generator,DG)并网接口方式有同步发电机组(synchronous generators,SG)接口和电压源逆变器(voltage source inverter,VSI)接口2类,文中提出了包含2种接口方式的微网控制策略。具有SG接口的DG通过其输出的有功功率和无功功率分别对微网的频率和电压进行下垂控制,具有VSI接口的DG通过输出电流的d、q分量分别对微网的频率和电压进行下垂控制。该控制策略可实现微网由联网运行模式向孤岛运行模式的平滑转换,并能够实现功率共享。具有SG接口的DG配置潜遗传变论域模糊控制电力系统稳定器后,可提高微网稳定性。仿真算例验证了该控制策略的有效性。     

Tunability and leakage currents of (Ba,Sr)TiO3 ferroelectric ceramics with various additives

The Ba_xSr_{1 − x} TiO₃ ferroelectric ceramics with magnesium (BSM) and neodymium (BSN) additives were studied. Measurements were made of tunability, dielectric losses (tan δ), leakage currents, the correlations between current-voltage I(U) and capacitance-voltage C(U) characteristics. I(U) characteristics of high quality BSM ceramics have four regions: Ohmic, where the conductivity is linear; the horizontal region (or negative differential resistivity); the exponential dependence; and the vertical current enhancement. These BSM samples (∼20% Mg additives) were distinguished by highest breakdown strength (more than 1000 V), low tan δ (less than 10^{− 3} at 1 MHz) and high tunability (up to 10% at E _max∼2 V/μm).     

CMOS Non‐tailed differential pair

A continuous‐time complementary metal–oxide–semiconductor differential pair that does not require the traditional tail current source as a way to control the direct current and common‐mode current is presented. Compared with a p‐channel long‐tailed pair, the proposed non‐tailed solution operates under a higher maximum input common‐mode voltage that includes (V_DD + V_SS)/2 even under low supply voltages. Experimental measurements on a prototype fabricated in a 0.35‐µm technology (with metal – oxide – semiconductor thresholds greater than 0.6 V) confirm this behavior for supply voltages as low as 1.2 V, whereas the long‐tailed pair with the same technology offers the same capability only for supplies higher than 1.6 V. Copyright © 2015 John Wiley & Sons, Ltd.     

Modulation on the electrical and optical properties of Na and Rh co-doped Ruddlesden-Popper layered Ca3Ti2O7

Layered perovskite Ca_2.91Na_0.09Ti_2-xRh_xO₇ (x?=?0.00, 0.02, 0.04, 0.06) were synthesized by a conventional solid-state reaction. Room temperature ferroelectricity has been confirmed. The remanent polarization increases with an increase of Rh content, which is due to a larger oxygen octahedral distortion by Rh doping. The coercive field increases with Rh doping as the pinning effect of oxygen vacancies reduce the mobility of domain wall. Remanent polarization and coercive field are caused by different mechanisms, so it is possible to modulate them independently to meet the requirement of application in ferroelectric field. The concentration of oxygen vacancy increased with Rh doping, leading to the significant increase of leakage current density. The bandgap of samples doped with Rh drastically decrease and the visible light response of the sample was improved by Rh doping due to the formation of impurity energy levels within the band gap.

     

Study of a coal-fired transonic disk MHD generator for a power system with CO2 recovery

A conceptual design of a transonic disk MHD channel is carried out for a power generation system with liquefaction recovery of CO₂. A previous study has shown that the subsonic disk MHD channel has rather poor performance and the supersonic disk channel yields sufficiently high power output, although its stability should be improved. The present paper proposes a transonic disk channel which can be stably operated with high power output. It is assumed that the transition between supersonic flow and subsonic flow is accompanied by a cylindrical shock wave in the channel. The transonic channel yields enthalpy extraction ratios of 20.2 and 22.9%, respectively, for thermal inputs of 1100 and 2000 MW, and is nearly equal to the performance of the supersonic channel. The stability of the transonic disk channel is examined by r-0 two-dimensional time-dependent calculations. The two-dimensional analysis shows that the transonic disk channel works stably with fewer load sections than the supersonic channel even when inlet perturbations are added. © 1998 Scripta Technica. Electr Eng Jpn, 122(2): 21–29, 1998     

Electrical Properties of Acceptor Doped BaTiO3

Electrical properties of acceptor (Mn, Mg or Mn+Mg)-doped BaTiO₃ ceramic have been studied in terms of oxygen vacancy concentration, various doping levels and electrical degradation behaviors. The solubility limit of Mn on Ti sites was confirmed to be close to or less than 1.0 mol%. Oxygen vacancy concentration of Ba(Ti_{0.995 –x}Mg_0.005Mn_x)O_{2.995 –y} (x = 0, 0.005, 0.01) was estimated to be 50 times greater than that of the un-doped BaTiO₃. The leakage current of 0.5 mol% Mn-doped BaTiO₃ was stable with time, which was much lower than that of the un-doped BaTiO₃. The BaTiO₃ specimen co-doped with 0.5 mol% Mg and 1.0 mol% Mn showed the lowest leakage current below 10^{– 10}A. It was confirmed that leakage currents of Mg-doped and un-doped BaTiO₃ under dc field are effectively suppressed by Mn co-doping as long as the Mn doping level is greater than Mg contents.     

Impact of high‐κ gate dielectric and other physical parameters on the electrostatics and threshold voltage of long channel gate‐all‐around nanowire transistor

High‐κ gate‐all‐around structure counters the Short Channel Effect (SCEs) mostly providing excellent off‐state performance, whereas high mobility III–V channel ensures better on‐state performance, rendering III–V nanowire GAAFET a potential candidate for replacing the current FinFETs in microchips. In this paper, a 2D simulator for the III–V GAAFET based on self‐consistent solution of Schrodinger–Poisson equation is proposed. Using this simulator, capacitance–voltage profile and threshold voltage are characterized, which reveal that gate dielectric constant (κ) and oxide thickness do not affect threshold voltage significantly at lower channel doping. Moreover, change in alloy composition of In_xGa_1‐xAs, channel doping, and cross‐sectional area has trivial effects on the inversion capacitance although threshold voltage can be shifted by the former two. Although, channel material also affects the threshold voltage, most sharp change in threshold voltage is observed with change in fin width of the channel (0.005 V/nm for above 10 nm fin width and 0.064 V/nm for sub‐10 nm fin width). Simulation suggests that for lower channel doping below 10²³ m⁻³, fin width variation affects the threshold voltage most. Whereas when the doping is higher than 10²³ m⁻³, both the thickness and dielectric constant of the oxide material have strong effects on threshold voltage (0.05 V/nm oxide thickness and 0.01 V/per unit change in κ). Copyright © 2014 John Wiley & Sons, Ltd.     

RF Performance of Strained SiGe pMOSFETs: Linearity and Gain

The RF performance of strained-SiGe pMOSFETs on SOI substrates has been investigated through the use of TCAD simulations. To optimize RF performance of strained-SiGe pMOSFETs, including intrinsic gain, linearity and g_m/I_d, we propose to vary the Ge concentration in the channel, shrink the SOI thickness and adopt an asymmetric doping profile along the channel. We find that neither strain nor the asymmetric doping approach is able to unlock the trade-off between intrinsic gain and linearity found in bulk and SOI relaxed Si MOSFETs. Instead, SOI layer thickness control provides an alternative approach to improving gain without sacrificing linearity. For optimized RF performance, the strained-SiGe pMOSFETs with high Ge concentrations (0.3 ≤ x ≤ 0.7) in the channel and thin SOI layers (< 20 nm) are preferred.