Correction to: A subthreshold low-power CMOS LC-VCO with high immunity to PVT variations

This paper presents a capacitor-free low dropout (LDO) linear regulator based on a dual loop topology. The regulator utilizes two feedback loops to satisfy the challenges of hearing aid devices, which include fast transient performance and small voltage spikes under rapid load-current changes. The proposed design works without the need of a decoupling capacitor connected at the output and operates with a 0–100 pF capacitive load. The design has been taped out in a \(0.18\,\upmu \hbox {m}\) CMOS process. The proposed regulator has a low component count, area of \(0.012\, \hbox {mm}^2\) and is suitable for system-on-chip integration. It regulates the output voltage at 0.9 V from a 1.0–1.4 V supply. The measured results for a current step load from 250 to 500 \(\upmu \hbox {A}\) with a rise and fall time of \(1.5\,\upmu \hbox {s}\) are an overshoot of 26 mV and undershoot of 26 mV with a settling time of \(3.5\,\upmu \hbox {s}\) when \({C_L}\) between 0 and 100 pF. The proposed LDO regulator consumes a quiescent current of only \(10.5\,\upmu \hbox {A}\). The design is suitable for application with a current step edge time of 1 ns while maintaining \(\Delta V_{out}\) of 64 mV.     

A 0.36 μW/channel recorder for external ambulatory ECG recorders

There is an increasing demand for long-term ECG monitoring applications which are very low power, small size and capable of wireless data transmission. This paper presents an analog front-end and also modulator for long-term ECG recording purpose. The fully integrated system features three independent channels and a modulator. The analog front-end includes a voltage-to-time conversion and a tunable modulator to achieve a very low power consumption for wireless transmission of the data without analog to digital converter. The proposed system is designed and simulated in a \(0.18\,\upmu \hbox {m}\) CMOS technology and occupies only \(0.245\,\mathrm{mm}^{2}\). It can record ECG signal with 9.2-bit resolution while consuming only \(0.36\,\upmu {\mathrm{W}}\) per channel from a 0.9 V supply. Also, it can transmit data consuming just \(0.72\,{\upmu }\mathrm{W}\) per channel from a 0.9 V supply. The input referred noise of the readout channel is \(2.01\,\upmu {\mathrm{V}}_{{{\rm rms}}}\).     

Low Voltage High Output Impedance Bulk-Driven Quasi-Floating Gate Self-Biased High-Swing Cascode Current Mirror

A low voltage self-biased high-swing cascode current mirror using bulk-driven quasi-floating gate MOSFET is proposed in this paper. The proposed current mirror bandwidth and especially the output impedance show a significant improvement compared to prior arts. The current mirror presented is designed using bulk-driven and bulk-driven quasi-floating gate N-channel MOS transistors, which helped it to operate at very low supply voltage of \({\pm }0.2\,\hbox {V}\). To achieve high output resistance, the current mirror uses regulated cascode stage followed by super cascode architecture. The small-signal analysis carried out proves the improvement achieved by proposed current mirror. The current mirror circuit operates well for input current ranging from 0 to \(250\,{\upmu }\mathrm{A}\) with good linearity and shows the bandwidth of 285 MHz. The input and output resistances are found as \(240\,\Omega \) and \(19.5\,\hbox {G}\Omega \), respectively. Further, the THD analysis and Monte Carlo simulations carried prove the robustness of proposed current mirror. The complete analysis is done using HSpice on UMC \(0.18\,\upmu \mathrm{m}\) technology.     

A Low-Voltage Fully Differential Pure Current Mode Current Operational Amplifier

In this paper a novel high-frequency fully differential pure current mode current operational amplifier (COA) is proposed that is, to the authors’ knowledge, the first pure MOSFET Current Mode Logic (MCML) COA in the world, so far. Doing fully current mode signal processing and avoiding high impedance nodes in the signal path grant the proposed COA such outstanding properties as high current gain, broad bandwidth, and low voltage and low-power consumption. The principle operation of the block is discussed and its outstanding properties are verified by HSPICE simulations using TSMC \(0.18\,\upmu \hbox {m}\) CMOS technology parameters. Pre-layout and Post-layout both plus Monte Carlo simulations are performed under supply voltages of \(\pm 0.75\,\hbox {V}\) to investigate its robust performance at the presence of fabrication non-idealities. The pre-layout plus Monte Carlo results are as; 93 dB current gain, \(8.2\,\hbox {MHz}\,\, f_{-3\,\text {dB}}, 89^{\circ }\) phase margin, 137 dB CMRR, 13 \(\Omega \) input impedance, \(89\,\hbox {M}\Omega \) output impedance and 1.37 mW consumed power. Also post-layout plus Monte Carlo simulation results (that are generally believed to be as reliable and practical as are measuring ones) are extracted that favorably show(in abovementioned order of pre-layout) 88 dB current gain, \(6.9\,\hbox {MHz} f_{-3\text {db}} , 131^{\circ }\) phase margin and 96 dB CMRR, \(22\,\Omega \) input impedance, \(33\,\hbox {M}\Omega \) output impedance and only 1.43 mW consumed power. These results altogether prove both excellent quality and well resistance of the proposed COA against technology and fabrication non-idealities.     

High-Accuracy Time-Mode Duty-Cycle-Modulation-Based Temperature Sensor for Energy-Efficient System Applications

This paper presents a new time-mode duty-cycle-modulation-based high-accuracy temperature sensor. Different from the well-known \({\varSigma }{\varDelta }\) ADC-based readout structure, this temperature sensor utilizes a temperature-dependent oscillator to convert the temperature information into temperature-related time-mode parameter values. The useful output information of the oscillator is the duty cycle, not the absolute frequency. In this way, this time-mode duty-cycle-modulation-based temperature sensor has superior performance over the conventional inverter-chain-based time domain types. With a linear formula, the duty-cycle output streams can be converted into temperature values. The design is verified in 65nm standard digital CMOS process. The verification results show that the worst temperature inaccuracy is kept within 1\(\,^{\circ }\mathrm{C}\) with a one-point calibration from \(-\)55 to 125 \(^{\circ }\mathrm{C}\). At room temperature, the average current consumption is only 0.8 \(\upmu \)A (1.1\(\,\upmu \)A in one phase and 0.5 \(\upmu \)A in the other) with 1.2 V supply voltage, and the total energy consumption for a complete measurement is only 0.384 \({\hbox {nJ}}\).     

Ultra-Fast Current Mode Sense Amplifier for Small $$I_{\mathrm{CELL}}$$ SRAM in FinFET with Improved Offset Tolerance

In this paper, a novel, high-performance and robust sense amplifier (SA) design is presented for small \(I_\mathrm{CELLl}\) SRAM, using fin-shaped field effect transistors (FinFET) in 22-nm technology. The technique offers data-line-isolated current sensing approach. Compared with the conventional CSA (CCSA) and hybrid SA (HSA), the proposed current feed-SA (CF-SA) demonstrates 2.15\(\times \) and 3.02\(\times \) higher differential current, respectively, for \({V}_{\mathrm{DD}}\) of 0.6 V. Our results indicate that even at the worst corner, CF-SA can provide 2.23\(\times \) and 1.7\(\times \) higher data-line differential voltage compared with CCSA and HSA, respectively. Further, 66.89 and 31.47 % reductions in the cell access time are achieved compared to the CCSA and HSA, respectively, under similar \(I_\mathrm{CELLl}\) and bit-line and data-line capacitance. Statistical simulations have proved that the CF-SA provides high read yield with 32.39 and 22.24 % less \(\upsigma _{\mathrm{Delay}}\). It also offers a much better read effectiveness and robustness against the data-line capacitance as well as \({V}_{\mathrm{DD}}\) variation. Furthermore, the CF-SA is able to tolerate a large offset of the input devices, up to 80 mV at \({V}_{\mathrm{DD}}=0.6\hbox {V}\).     

A 3.1–10.6 GHz UWB LNA Based on Self Cascode Technique for Improved Bandwidth and High Gain

In this work, we present a self cascode based ultra-wide band (UWB) low noise amplifier (LNA) with improved bandwidth and gain for 3.1–10.6 GHz wireless applications. The self cascode (SC) or split-length compensation technique is employed to improve the bandwidth and gain of the proposed LNA. The improvement in the bandwidth of SC based structure is around 1.22 GHz as compared to simple one. The significant enhancement in the characteristics of the introduced circuit is found without extra passive components. The SC based CS–CG structure in the proposed LNA uses the same DC current for operating first stage transistors. In the designed UWB LNA, a common source (CS) stage is used in the second stage to enhance the overall gain in the high frequency regime. With a standard 90 nm CMOS technology, the presented UWB LNA results in a gain \(\hbox {S}_{21}\) of \(20.10 \pm 1.65\,\hbox {dB}\) across the 3.1–10.6 GHz frequency range, and dissipating 11.52 mW power from a 1 V supply voltage. However, input reflection, \(\hbox {S}_{11}\), lies below \(-\,10\) dB from 4.9–9.1 GHz frequency. Moreover, the output reflection (\(\hbox {S}_{22}\)) and reverse isolation (\(\hbox {S}_{12}\)), is below \(-\,10\) and \(-\,48\) dB, respectively for the ultra-wide band region. Apart from this, the minimum noise figure (\(\hbox {NF}_{min}\)) value of the proposed UWB LNA exists in the range of 2.1–3 dB for 3.1–10.6 GHz frequency range with a a small variation of \(\pm \,0.45\,\hbox {dB}\) in its \(\hbox {NF}_{min}\) characteristics. Linearity of the designed LNA is analysed in terms of third order input intercept point (IIP3) whose value is \(-\,4.22\) dBm, when a two tone signal is applied at 6 GHz with a spacing of 10 MHz. The other important benefits of the proposed circuit are its group-delay variation and gain variation of \(\pm \,115\,\hbox {ps}\) and \(\pm \,1.65\,\hbox {dB}\), respectively.     

A Reduced-sp-$$\hbox {D3L}_{\mathrm{sum}}$$ Adder-Based High Frequency $$4\times 4$$4×4 Bit Multiplier Using Dadda Algorithm

A low-power, high-speed \(4\times 4\) multiplier using Dadda algorithm is proposed. The full adder blocks used in this multiplier have been designed using reduced-split precharge-data driven dynamic sum logic. Flip flops used in the pipeline registers have been designed to increase input signal noise margin, resulting in the minimization of output signal glitches. The multiplier circuit is implemented in 1P-9M Low-K UMC 90nm CMOS process technology. Post-layout simulations are carried out using Cadence Virtuoso. The proposed multiplier operates at a clock frequency of 3.5 GHz, with an average dynamic power consumption of 1.096 mW at a temperature of \(27\,^{\circ }\hbox {C}\) and 1 V supply voltage and occupies a chip area of \(76\,\upmu \hbox {m}\times 102\,\upmu \hbox {m}\).     

Design of 0.5 V voltage-combiner based OTA with 60 dB gain 250 kHz UGB in CMOS

A gain enhancement technique for a pseudo differential OTA based on voltage combiner, suitable for sub-1 V supply is presented in this letter. The proposed technique uses a G _m boosted voltage combiner. Unlike the typical voltage combiner which has an approximated gain of \(2\,\frac{{\text{V}}}{{\text{V}}}\), this voltage combiner can produce gain more than \(5\,\frac{{\text{V}}}{{\text{V}}}\). So it help us achieve nearly 60 dB DC gain with 250 kHz UGB for the pseudo differential OTA at a capacitive load of 10 pF. Power dissipation is very low i.e. 716 nW at supply of 0.5 V. So as to facilitate maximum swing at 0.5 V supply and lower the power consumption, MOS transistors are biased in weak/moderate inversion. The OTA is designed in standard 45 nm CMOS process. Phase margin of is more than \(55^{\circ }\) for a typical load of 10 pF. The input referred noise is \(150\,\upmu {\text{V}}{/}\sqrt{{\text{Hz}}}\) at 10 Hz and slew rate \(0.02\,{\text{V}}{/}\upmu{\text{s}}\) for 10 pF load.     

Design considerations of CMOS active inductor for low power applications

Previous studies have shown that \(g_m/I_D\) (transconductance-to-drain-current) ratio based design is useful for optimizing analog circuits. In this paper, we explore challenges associated with designing a low-power active inductor. We focus in particular on sizing issues that arise as the transistor speed is maximized and the current consumption is minimized. Finally, we apply the results to design an amplifier integrated with an active inductor in \(0.18\,\upmu \hbox{m}\) CMOS process and show that by systematically working through sizing issues, a \(10\,\upmu \hbox{A}\) sub GHz amplifier can be designed.     

New refractive index profiles of dispersion-flattened highly nonlinear fibers for future all-optical signal processing in wdm optical networks

In this paper, we demonstrate new dissimilar refractive index profiles for highly nonlinear ultra-flattened dispersion fibers with noteworthy effective area \((A_\mathrm{eff})\) for future optical signal processing. The newly proposed fibers named from Type 1 to Type 5 have a flattened dispersion over S, C, L and U bands. Predominantly, few-mode HNL-UFF fiber of Type 3 yields dispersion-flattened characteristics over a range of 250 nm of optical communication spectrum with a mere 0.2 ps/nm km variation in dispersion and a dispersion slope of \(0.0057\hbox { ps}/\hbox {nm}^{2}\) km due to the contribution of higher-order modes to the dispersion characteristics of the fiber. Moreover, it has a moderate nonlinear coefficient of \(8.03\hbox { W}^{-1}\,\hbox {km}^{-1}\). By modifying the refractive index profile of Type 3 fiber, Type 4 and Type 5 fibers are obtained in order to ensure single-mode operation, while the zero flattened dispersion characteristics of the fiber are compromised. Among the newly proposed fibers, Type 4 fiber offers a very low ITU-T cutoff wavelength of \(1.33~\upmu \hbox {m}\), whereas in the case of Type 5 fiber it is \(1.38~\upmu \hbox {m}\). Moreover, Type 4 and Type 5 fibers have good nonlinear coefficients of \(12.26\hbox { W}^{-1}\,\hbox {km}^{-1}\) and \(11.45\hbox { W}^{-1}\,\hbox {km}^{-1}\), respectively. By virtue of the proposed optimized index profile, an insensitive behavior toward bending is displayed by Type 3, Type 4 and Type 5 fibers. In addition, Type 4 fiber provides a better splice loss of 0.25 dB.     

Application of photonic crystal ring resonator nonlinear response for full-optical tunable add–drop filtering

In this paper, we investigate the application of Kerr-like nonlinear photonic crystal (PhC) ring resonator (PCRR) for realizing a tunable full-optical add–drop filter. We used silicon (Si) nano-crystal as the nonlinear material in pillar-based square lattice of a 2DPhC. The nonlinear section of PCRR is studied under three different scenarios: (1) first only the inner rods of PCRR are made of nonlinear materials, (2) only outer rods of PCRR have nonlinear response, and (3) both of inner and outer rods are made of nonlinear material. The simulation results indicate that optical power required to switch the state of PCRR from turn-on to turn-off, for the nonlinearity applied to inner PCRR, is at least \(2000\, \hbox {mW}{/}\upmu \hbox {m}^{2}\) and, for the nonlinearity applied to outer PCRR, is at least \(3000\, \hbox {mW}{/}\upmu \hbox {m}^{2}\) which corresponds to refractive index change of \(\Delta n_\mathrm{NL }= 0.085\) and \(\Delta n_\mathrm{NL }= 0.15\), respectively. For nonlinear tuning of add–drop filter, the minimum power required to 1 nm redshift the center operating wavelength \((\lambda _{0} = 1550\, \hbox {nm})\) for the inner PCRR scenario is \(125\, \hbox {mW}{/}\upmu \hbox {m}^{2}\) (refractive index change of \(\Delta n_\mathrm{NL}= 0.005)\). Maximum allowed refractive index change for inner and outer scenarios before switch goes to saturation is \(\Delta n_\mathrm{NL }= 0.04\) (maximum tune-ability 8 nm) and \(\Delta n_\mathrm{NL }= 0.012\) (maximum tune-ability of 24 nm), respectively. Performance of add–drop filter is replicated by means of finite-difference time-domain method, and simulations displayed an ultra-compact size device with ultra-fast tune-ability speed.     

65-nm CMOS Voltage-to-Time Converter for 5-GS/s Time-Based ADCs

This paper discusses a voltage-to-time converter (VTC) designed for use in a time-based analog-to-digital converter. The VTC considered in this work is based on a starved-inverter topology. Linearity, delay, and jitter of the VTC are analyzed to facilitate a physical understanding of the circuit performance. The design is experimentally verified in a 65-nm CMOS technology. Measurement results show that the VTC, operating with a 5-GHz clock, has an output delay range of \(\pm 25\,{\text{ ps }}\), 4.4 effective number of bits (ENOB), and output jitter of \(0.5\,\text{ ps }\) RMS while consuming 4 mW of power. The input effective resolution bandwidth (ERBW) of the VTC is measured to be 4.1 GHz, over which the ENOB remains above 3.5 bits. The same VTC, operating with a 7.5-GHz clock, consumes 9.7 mW of power from a 1.2-V supply, has ENOB of >3.8 bits, ERBW of >7 GHz, output jitter of \(0.4\,\text{ ps }\) RMS, and output delay range of \(\pm 25\,\text{ ps }\). The VTC achieves the widest input bandwidth of any VTC reported to date.     

Study on the Effect of Mn,Zn, and Sb on Undercooling Behavior of Sn-Ag-Cu Alloys Using Differential Thermal Analysis

Differential thermal analysis (DTA) has been conducted on directionally solidified near-eutectic Sn-3.0 wt.%Ag-0.5 wt.%Cu (SAC), SAC \(+\) 0.2 wt.%Sb, SAC \(+\) 0.2 wt.%Mn, and SAC \(+\) 0.2 wt.%Zn. Laser ablation inductively coupled plasma mass spectroscopy was used to study element partitioning behavior and estimate DTA sample compositions. Mn and Zn additives reduced the undercooling of SAC from 20.4\(^\circ \hbox {C}\) to \(4.9^\circ \hbox {C}\) and \(2^\circ \hbox {C}\), respectively. Measurements were performed at cooling rate of \(10^\circ \hbox {C}\) per minute. After introducing 200 ppm \(\hbox {O}_2\) into the DTA, this undercooling reduction ceased for SAC \(+\) Mn but persisted for SAC \(+\) Zn.     

Photonic crystal-based optical filter: a brief investigation

Ring resonator-based channel drop filters are investigated conceptually and analytically with different ring (square and hexagonal) structures. In the proposed architecture, silicon rods (\(n=3.4641\)) are contrived over an air substrate of refractive index \(n=1\) in the equilateral triangular lattice which has the lattice constant \(a=900\,\hbox {nm}\). The characteristics of the design are examined for various types of pillars (circular and elliptical) and are reported in the analysis. The band gap for each structure is calculated and observed by plane-wave expansion method. The normalized transmission spectra and resonance wavelengths for different photonic crystal ring resonators are obtained using 2D finite-difference time-domain method. From the investigation, the resonance of circular pillar falls over the region of the third window at C-band (1530–1565 nm) which has the lowest attenuation losses and most widely used. Full width at half maximum and quality factor of the desired layout are also being calculated. The size of the device is about \(20 \times 14\,{\upmu }\hbox {m}\) which is highly compact and useful for the integration of photonic circuits.     

Ab␣Initio Study of Aluminium Impurity and Interstitial-Substitutional Complexes in Ge Using a Hybrid Functional (HSE)

The results of an ab?initio modelling of aluminium substitutional impurity (\({\hbox {Al}}_{\rm Ge}\)), aluminium interstitial in Ge [\({\hbox {I}}_{\rm Al}\) for the tetrahedral (T) and hexagonal (H) configurations] and aluminium interstitial-substitutional pairs in Ge (\({\hbox {I}}_{\rm Al}{\hbox {Al}}_{\rm Ge}\)) are presented. For all calculations, the hybrid functional of Heyd, Scuseria, and Ernzerhof in the framework of density functional theory was used. Defects formation energies, charge state transition levels and minimum energy configurations of the \({\hbox {Al}}_{\rm Ge}\), \({\hbox {I}}_{\rm Al}\) and \({\hbox {I}}_{\rm Al}{\hbox {Al}}_{\rm Ge}\) were obtained for ?2, ?1, 0, \(+\)1 and \(+\)2 charge states. The calculated formation energy shows that for the neutral charge state, the \({\hbox {I}}_{\rm Al}\) is energetically more favourable in the T than the H configuration. The \({\hbox {I}}_{\rm Al}{\hbox {Al}}_{\rm Ge}\) forms with formation energies of ?2.37 eV and ?2.32 eV, when the interstitial atom is at the T and H sites, respectively. The \({\hbox {I}}_{\rm Al}{\hbox {Al}}_{\rm Ge}\) is energetically more favourable when the interstitial atom is at the T site with a binding energy of 0.8 eV. The \({\hbox {I}}_{\rm Al}\) in the T configuration, induced a deep donor (\(+\)2/\(+1\)) level at \(E_{\mathrm {V}}+0.23\) eV and the \({\hbox {Al}}_{\rm Ge}\) induced a single acceptor level (0/?1) at \(E_{\mathrm {V}}+0.14\) eV in the band gap of Ge. The \({\hbox {I}}_{\rm Al}{\hbox {Al}}_{\rm Ge}\) induced double-donor levels are at \(E_{\rm V}+0.06\) and \(E_{\rm V}+0.12\) eV, when the interstitial atom is at the T and H sites, respectively. The \({\hbox {I}}_{\rm Al}\) and \({\hbox {I}}_{\rm Al}{\hbox {Al}}_{\rm Ge}\) exhibit properties of charge state-controlled metastability.     

Low-Voltage CMOS Switch for High-Speed Rail-To-Rail Sampling

Sampling switches have a dominant role in switched-capacitor circuits and analog-to-digital convertors. Since they act as input gates, their nonlinearities directly degrade the quality of the input signals. The scaling-down trend of CMOS technology and increasing demands for high-speed and power-efficient circuits pose design challenge in high-speed sampling switches for low-voltage applications. To address this issue, an optimized CMOS switch is proposed in this paper consisting of a bootstrapped NMOS switch and a boosted PMOS switch as a transmission gate. By utilizing this technique, the nonlinearity resulting from the threshold voltage variation (body effect) of NMOS switch is mitigated, considerably. To evaluate the proposed switch, it is designed in 0.18 \(\upmu \hbox {m}\) CMOS process technology. According to the obtained simulation results, this switch can achieve total harmonic distortion of \(-\)78.81 and \(-\)62.99 dB in 100 MS/s at \(V_\mathrm{dd}\) = 1 Volt and 50 MS/s at \(V_\mathrm{dd}\) = 0.8 V, respectively.     

Electrochemical,Structural and Magnetic Analysis of Electrodeposited CoCu/Cu Multilayers: Influence of Cu Layer Deposition Potential

The electrochemical, structural and magnetic properties of CoCu/Cu multilayers electrodeposited at different cathode potentials were investigated from a single bath. The Cu layer deposition potentials were selected as \(-\,0.3,\,\hbox {V}\) \(-\,0.4\,\,\hbox {V}\), and \(-\,0.5\,\hbox {V}\) with respect to saturated calomel electrode (SCE) while the Co layer deposition potential was constant at \(-\,1.5\,\hbox {V}\) versus SCE. For the electrochemical analysis, the current-time transients were obtained. The amount of noble non-magnetic (Cu) metal materials decreased with the increase of deposition potentials due to anomalous codeposition. Further, current-time transient curves for the Co layer deposition and capacitance were calculated. In the structural analysis, the multilayers were found to be polycrystalline with both Co and Cu layers adopting the face-centered cubic structure. The (111) peak shifts towards higher angle with the increase of the deposition potentials. Also, the lattice parameters of the multilayers decrease from 0.3669 nm to 0.3610 nm with the increase of the deposition potentials from \(-\,0.3\,\hbox {V}\) to \(-\,0.5\,\hbox {V}\), which corresponds to the bulk values of Cu and Co, respectively. The electrochemical and structural results demonstrate that the amount of Co atoms increased and the Cu atoms decreased in the layers with the increase of deposition potentials due to anomalous codeposition. For magnetic measurements, the saturation magnetizations, \(M_s\) obtained from the magnetic curves of the multilayers were obtained as 212 kA/m, 276 kA/m, and 366 kA/m with \(-\,0.3\,\hbox {V}\), \(-\,0.4\,\hbox {V}\), and \(-\,0.5\,\hbox {V}\) versus SCE, respectively. It is seen that the \(M_s\) values increased with the increase of the deposition potentials confirming the increase of the Co atoms and decrease of the Cu amount. The results of electrochemical and structural analysis show that the deposition potentials of non-magnetic layers plays important role on the amount of magnetic and non-magnetic materials in the layers and thus on the magnetic properties of the multilayers.     

Dependence of thermal sensitivity of LPFG on waveguide and material parameters

This article demonstrates the effect of waveguide and material parameters on thermal sensitivity trends adopted by different cladding modes based on long-period fiber grating. Three-layer fiber geometry-based mathematical model has been implemented to estimate cladding modes. It is observed that for a cladding mode, the sign and magnitude of thermal sensitivity slope depend upon the designed grating period closer to period at dispersion turn around point. The \(\hbox {LP}_{10}\) and \(\hbox {LP}_{11}\) cladding modes have shown blueshift and maximum thermal sensitivity above all other modes at designed grating periods of 225 and \(195\,\upmu \hbox {m}\), respectively. The material parameter of fiber (thermo-optic coefficient) has also resulted in increment in sensitivity with the increase in difference amid its values for core and cladding region.     

A continuous-time delta-sigma ADC for portable ultrasound scanners

A fully differential fourth-order 1-bit continuous-time delta-sigma ADC designed in a 65 nm process for portable ultrasound scanners is presented in this paper. The circuit design, implementation and measurements on the fabricated die are shown. The loop filter consists of RC-integrators, programmable capacitor arrays, resistors and voltage feedback DACs. The quantizer contains a pulse generator, a high-speed clocked comparator and a pull-down clocked latch to ensure constant delay in the feedback loop. Using this implementation, a small and low-power solution required for portable ultrasound scanner applications is achieved. The converter has a supply voltage of 1.2 V, a bandwidth of 10 MHz and an oversampling ratio of 16 leading to an operating frequency of 320 MHz. The design occupies a die area of \(0.0175\hbox { mm}^2\). Simulations with extracted parasitics show a SNR of 45.2 dB and a current consumption of \(489 \,\upmu \hbox {A}\). However, by adding a model of the measurement setup used, the performance degrades to 42.1 dB. The measured SNR and current consumption are 41.6 dB and \(495\,\upmu \hbox {A}\), which closely fit with the expected simulations. Several dies have been measured, and an estimation of the die spread distribution is given.