MMIC用多层磁膜电感研究

采用磁控溅射生长磁膜工艺,结合BCB(苯并环丁烯)平坦化技术,首次制作了"金属线圈/磁膜/金属线圈(M/F/M)"和"磁膜/金属线圈/磁膜/金属线圈(F/M/F/M)"两种结构的多层磁膜电感,整个工艺与标准MMIC工艺兼容.在2 GHz处,"金属线圈/磁膜/金属线圈"结构电感的电感量为7.5 nH,品质因数为7.17,...     

硅基COZrO铁氧体磁膜结构RF集成微电感

制作了一种新型磁膜结构射频集成微电感.该电感使用溶胶-凝胶法制备的CoZrO铁氧体作为磁性薄膜;采用平面单匝形式的金属线圈,从而形成"SiO2绝缘层/磁膜层(CoZrO)/SiO2绝缘层/Cu线圈"的结构,具有结构简单、制作工艺与常规集成工艺兼容等特点.同时,采用相同工艺同批制作了无磁膜微电感作为对比样品,并取各项结构参数与磁膜电感相一致.测试结果表明,2GHz处,磁膜结构微电感的感值(L)为1.75nH、品质因数(Q)为18.5,与无磁膜微电感相比,L和Q的值分别提高了25%和23%.     

硅基CoZrO铁氧体磁膜结构RF集成微电感

制作了一种新型磁膜结构射频集成微电感.该电感使用溶胶-凝胶法制备的CoZrO铁氧体作为磁性薄膜;采用平面单匝形式的金属线圈,从而形成"SiO2绝缘层/磁膜层(CoZrO)/SiO2绝缘层/Cu线圈"的结构,具有结构简单、制作工艺与常规集成工艺兼容等特点.同时,采用相同工艺同批制作了无磁膜微电感作为对比样品,并取各项结构参数与磁膜电感相一致.测试结果表明,2GHz处,磁膜结构微电感的感值(L)为1.75nH、品质因数(Q)为18.5,与无磁膜微电感相比,L和Q的值分别提高了25%和23%.     

基于闭合磁路的框式薄膜电感的研究

通过磁控溅射工艺制备出三种框式薄膜电感,其中特殊磁芯电感、全磁膜电感为设计制作的具有闭合磁性回路的特殊薄膜电感,而三文治结构电感是目前流行的薄膜电感,这些电感均由下层磁芯层、下层绝缘层(聚偏二氯乙烯,厚度约为40μm)、线圈和线圈中心的磁膜、上层绝缘层和上层磁芯层组成,其差别在于磁芯结构不同。在1~3 MHz频率范围内,比较了三种电感的等效电感、寄生电容和损耗因子。结果表明:与三文治结构电感和全磁膜电感相比,特殊磁芯电感有较高的等效电感量和较小的寄生电容,但损耗较后两者高。     

采用不同中间夹层的双记录层磁光光盘热光特性比较

磁光存储技术是一种颇受关注的下一代光存储技术.为提高单个磁光光盘的存储容量,途径之一是采用多值存储、多波长读出技术,实现所谓三维磁光存储.通常使用不同波长的蓝光来实现信号的读写操作.如果不同波长的激光在磁光存储多层膜中产生热场分布的差异较大,将有利于提高读出信号的信噪比.本文结合光学矩阵法及有限元方法分析了中间夹层分别为SiN、GaP时,磁光存储多层膜的热光特性.结果表明在蓝光波段,用GaP层替代传统的SiN中间夹层,将使磁光光盘具有更好的热光特性.     

微电子学、集成电路

TN42008010839硅基完全集成DC/DC转换器中多层平面电感设计与建模/李清华,邵志标,耿莉(西安交通大学电子与信息工程学院)//西安交通大学学报.―2007,41(4).―463～466.为提高完全集成低压低功率DC/DC转换器转换效率与输出电流能力,提出了一种多层混联螺旋电感结构。该结构基于标准0.5μm2P3M CMOS工艺,将下面较薄的两层金属线圈多点并联,再与最上层金属线圈串联。多点并联结构有效地增加了等效金属层的厚度,串联结构增加了线圈之间的互感值,从而可以在不增加额外工艺成本的条件下显著提高平面电感的品质因数、单位面积电感值和电感线…     

怎样制作结构最佳的功率分频电感

近来,高保真声箱用功率分频电感虽有采用磁性线圈结构的,但目前仍以空心线圈结构为主,且绕组尺寸大多不尽合理。因此分频电感匝数多、导线粗和体积大等问题比较突出。本文介绍一种多层空心线圈计算方法。可按预定的电感量(L)及其直流电阻(R)要求获得绕组最佳结构尺寸,即可使L/R比值达到最大值。按计算绕制的电感量误差一般小于5％,     

Fe-ZnSe纳米复合颗粒膜的制备和磁电阻效应

采用射频溅射法制备了"纳米铁磁金属颗粒-半导体基体"Fe-ZnSe复合颗H粒膜,研究了颗粒膜的结构、磁性和磁电阻效应.实验结果表明,在室温下Fe-ZnSe复合颗粒膜中纳米Fe颗粒表现出超顺磁性,颗粒膜的磁电阻变化率△ρ/ρ0数值达到4.6%;颗粒膜的磁电阻变化率△ρ/ρ0随温度的变化关系表明△ρ/ρ0数值随温度的下降而增大.     

Fe膜及磁场沉积对TbDy-Fe膜磁伸性能的影响

为了提高TbDv-Fe膜的低场磁敏性,采用离子束溅射沉积(IBSD)法制备TbDy-Fe超磁致伸缩薄膜,分别研究了纯Fe膜与TbDy-Fe单层膜、TbDy-Fe/Fe耦合多层膜的复合及磁场下溅射沉积对TbDy-Fe膜磁致伸缩性能的影响;用振动样品磁强计(VSM)测试薄膜磁滞回线,用电容位移测量仪测试薄膜悬臂梁自由端偏转量,并计算出磁致伸缩系数λ.结果表明,由IBSD法制备的纯Fe膜、TbDy-Fe单层膜、TbDy-Fe/Fe复合膜的易磁化轴均平行于膜面,TbDy-Fe/Fe复合膜在低场下的磁化强度与磁导率均高于TbDy-Fe单层膜(在100 kA/m时,TbDy-Fe/Fe复合膜的磁化强度比TbDy-Fe单层膜高173%).纯Fe膜分别与TbDy-Fe单层膜、TbDy-Fe/Fe耦合多层膜进行复合均可提高薄膜磁致伸缩性能;磁场下溅射沉积所得180 nm纯Fe膜 640 nmTbDy-Fe/Fe耦合多层膜,由于在其膜面内短轴方向产生感生磁各向异性,从而使磁致伸缩性能得到进一步的提高,在150 kA/m的磁场下它的λ值可达到650×10-6.     

非晶态TbFeCo磁光膜的HREM研究

磁光介质的性质与其微观结构有密切的关系,H.J.leamy等曾研究过RE-TM非晶态材料的柱状微结构[1]。但未涉及Tb Fe Co膜,且所采用的复型技术显得不适用。在与磁光介质性能劣化相联系的实用化上,Tetsuo Zijima等研究过RE-TM膜的稳定性,其着重点限于氧的扩散和Co在Tb Fe Co膜中的作用,未对晶化引起劣化给予仔细的研究[2]。本文对磁控溅射Tb Fe Co磁光膜的老化及晶化引起的微结构变化进行了HREM研究。由XMA测得该膜的成分为Fe36.5Co48.8Tb14.7(WT％)     

A Fully Integrated Thin‐Film Inductor and Its Application to a DC‐DC Converter

This paper presents a simple process to integrate thin‐film inductors with a bottom NiFe magnetic core. NiFe thin films with a thickness of 2 to 3 μm were deposited by sputtering. A polyimide buffer layer and shadow mask were used to relax the stress of the NiFe films. The fabricated double spiral thin‐film inductor showed an inductance of 0.49 μH and a Q factor of 4.8 at 8 MHz. The DC‐DC converter with the monolithically integrated thin‐film inductor showed comparable performances to those with sandwiched magnetic layers. We simplified the integration process by eliminating the planarization process for the top magnetic core. The efficiency of the DC‐DC converter with the monolithic thin‐film inductor was 72% when the input voltage and output voltage were 3.5 V and 6 V, respectively, at an operating frequency of 8 MHz.     

新颖的常规硅工艺实现的侧向螺线型片上集成电感

提出了一种用常规硅工艺实现的片上集成电感的螺线型新结构．制造工艺使用标准双层金属布线的常规硅工艺．测量了螺线型集成电感的S参数，从测量数据计算了集成电感的参量．实验的侧向螺线型片上集成电感的Q值峰值为1.3，电感量为22nH．对用两层金属层实现的侧向螺线型片上集成电感和单层金属的常规平面螺旋电感的实验结果进行了比较，电感量和Q值与常规平面螺旋电感有可比性．     

新颖的常规硅工艺实现的侧向螺线型片上集成电感

提出了一种用常规硅工艺实现的片上集成电感的螺线型新结构．制造工艺使用标准双层金属布线的常规硅工艺．测量了螺线型集成电感的S参数，从测量数据计算了集成电感的参量．实验的侧向螺线型片上集成电感的Q值峰值为1.3，电感量为22nH．对用两层金属层实现的侧向螺线型片上集成电感和单层金属的常规平面螺旋电感的实验结果进行了比较，电感量和Q值与常规平面螺旋电感有可比性．     

Surface micromachined solenoid on-Si and on-glass inductors for RFapplications

RF performance of surface micromachined solenoid on-chip inductors fabricated on a standard silicon substrate (10 Ω·cm) has been investigated and the results are compared with the same inductors on glass. The solenoid inductor on Si with a 15-μm thick insulating layer achieves peak quality (Q-) factor of 16.7 at 2.4 GHz with inductance of 2.67 nH. This peak Q-factor is about two-thirds of that of the same inductor fabricated on glass. The highest performance has been obtained from the narrowest-pitched on-glass inductor, which shows inductance of 2.3 nH, peak Q-factor of 25.1 at 8.4 GHz, and spatial inductance density of 30 nH/mm². Both on-Si and on-glass inductors have been modeled by lumped circuits, and the geometrical dependence of the inductance and Q-factor have been investigated as well     

氧化多孔硅上制作Cu电感的研究

给出了一种厚膜氧化多孔硅(OPS)层上制作Cu电感的新型工艺技术。由于OPS是一种低损耗的材料,铜的电阻率很低,采用OPS隔离硅衬底和Cu线圈能够降低电感的寄生损耗,提高电感Q值。实验过程中将孔隙度>56%的多孔硅厚膜利用两步氧化法氧化为OPS厚膜,通过种子层溅射/光刻/电镀Cu/刻蚀种子层的方法完成了Cu线圈的电镀。获得了1nH的电感,其Q值在10GHz的频率下达到了9,电感的自谐振频率超过20GHz。     

Design issues for monolithic DC-DC converters

This paper presents various ideas for integrating different components of dc-dc converter on to a silicon chip. These converters are intended to process power levels up to 0.5W. Techniques for integrating capacitors and design issues for MOS transistors are discussed. The most complicated design issue involves inductors. Expressions for trace resistance and inductance estimation of on-chip planar spiral inductor on top metal layer of CMOS process are compared. These inductors have high series resistance due to low metal trace thickness, capacitive coupling with substrate and other metal traces, and eddy current loss. As an alternative, a CMOS compatible three-dimensional (3-D) surface micromachining technology known as plastic deformation magnetic assembly (PDMA) is used to fabricate high quality inductors with small footprints. Experimental results from a monolithic buck converter using this PDMA inductor are presented. A major conclusion of this work is that the 3-D "post-process" technology is more viable than traditional integrated circuit assembly methods for realizing of micro-power converters.     

双层悬空结构射频微电感制作研究

利用MEMS工艺制作了一种双层悬空结构的圆形射频微电感,研究了双层结构微电感中微带线宽度对其性能的影响。研究表明,双层悬空结构的圆形射频微电感不仅具有较大的电感量,而且其Q值也较高;双层微电感的Q值随微带线宽度的增大而升高,而电感量则随微带线宽度的增大而降低。对于微带线宽度为60μm的双层微电感,在频率2～4GHz时,其电感量可达到5nH左右,Q值达到20。     

Design of multilevel pyramidically wound symmetric inductor for CMOS RFIC’s

This paper presents the design of a multilevel pyramidically wound symmetric (MPS) inductor structure. Being multilevel, the MPS inductor achieves high inductance to area ratio and hence occupies smaller silicon area. The symmetric inductor is realized by winding the metal trace of the spiral coil down and up in a pyramidal manner exploiting the multilevel VLSI interconnects technology. Closed form expressions are also developed to estimate the self resonating frequency (f _res ) of the MPS inductor and results are compared to two layer conventional symmetric and asymmetric stack. The estimation is also validated with full wave electromagnetic simulation. The performance of various MPS inductors of different metal width, metal offsets and outer diameter is demonstrated. For an inductance of 8 nH, the MPS inductor reduces the area by 65–95% over conventional planar symmetric inductors and 71–94% over its equivalent pair of asymmetric planar inductors. The performance is also compared to other symmetric inductors reported in literature. With MPS inductor, the cost and size of RF IC’s will be reduced significantly.     

Flip-Chip-Assembled Air-Suspended Inductors

This paper discusses high-performance planar suspended inductors for hybrid integration with microwave circuits. The inductors are fabricated using a silicon surface micromachining foundry process and assembled using flip-chip bonding. The silicon substrate is removed, leaving a metal inductor suspended 60 mum above the microwave substrate, thus reducing the parasitic capacitance and loss. Various rectangular, octagonal, and circular inductor geometries with one to five windings are designed with inductance values between 0.65 and 16 nH to demonstrate the flexibility of this technique. Measured self-resonant frequencies are between 5 and 34.8 GHz, with quality factors from 45 to 100. Equivalent circuits extracted from measurement for each inductor type show good agreement with measured impedance and full-wave simulations over frequency. The dc current handling limit is 200 mA