Performance and hot-carrier reliability of 100 nm channel lengthjet vapor deposited Si3N4 MNSFETs

Metal-nitride-semiconductor FETs (MNSFETs) having channel lengths down to 100 mm and a novel jet vapor deposited (JVD) Si₃N₄ gate dielectric have been fabricated and characterized. When compared with MOSFETs having a thermal SiO₂ gate insulator, the MNSFETs show a comparable drain current drive, transconductance, subthreshold slope and pre-stress interface quality. A novel charge pumping technique is employed to characterize the hot-carrier induced interface-trap generation in MNSFETs and MOSFETs. Under identical substrate current during stress, MNSFETs show less interface-state generation and drain current degradation, for various channel lengths, stress times and supply voltages, despite the fact that the Si-Si₃N₄ barrier (2.1 eV) is lower than the Si-SiO₂ barrier (3.1 eV). The time and voltage dependence of hot-carrier degradation has been found to be distinctly different for MNSFETs compared to SiO₂ MOSFETs     

Multi-frequency transconductance technique for interface characterization of deep sub-micron SOI–MOSFETs

A multi-frequency transconductance technique for interface characterization of sub-micron SOI–MOSFETs is implemented. This technique is shown to be highly suitable for interface characterization in SOI devices where conventional charge-pumping techniques cannot be applied. Using this multi-frequency technique, sub-micron SOI–MNSFETs with a SiN dielectric deposited by a novel jet-vapor-deposition (JVD) process are characterized. Results are compared with charge pumping results obtained on bulk MNSFETs with identically processed JVD nitrides.     

Low frequency noise sources in InAlAs/InGaAs MODFETs

Detailed analysis of the 1/f low-frequency noise (LFN) in In/sub 0.52/Al/sub 0.48/As/InGaAs MODFET structures is performed, for low drain bias (below pinch-off voltage), in order to identify the physical origin and the location of the noise sources responsible for drain current fluctuations in the frequency range 0.1 Hz-10/sup 5/ Hz. Experimental data were analyzed with the support of a general modeling of the 1/f LFN induced by traps distributed within the different layers and interfaces which constitute the heterostructures. Comparative noise measurements are performed on a variety of structures with different barrier (InAIAs, InP) and different channel (InGaAs lattice matched to InP, strained InGaAs, InP) materials. It is concluded that the dominant low frequency noise sources of InAlAs/InGaAs MODFET transistors in the ON state are generated by deep traps distributed within the "bulk" InAlAs barrier and buffer layers. For reverse gate bias, the gate current appears to be the dominant contribution to the channel LFN, whereas both the gate current and the drain and source ohmic contacts are the dominant sources of noise when the device is biased strongly in the ON state. Heterojunction FET's on InP substrate with InP barrier and buffer layers show significantly lower LFN and appear to be more suitable for applications such as nonlinear circuits that have noise upconversion.     

Characterization of the frequency dispersion of transconductance and drain conductance of GaAs MESFET

Frequency dispersions of the transconductance and the drain conductance of ion-implanted gallium arsenide (GaAs) metal-semiconductor field-effect transistors (MESFETs) are measured and analyzed. In the linear region of the MESFET (low drain voltage), a positive transconductance dispersion is observed, which is caused by the deep-level traps at the surface between the source and the gate. In the saturation region (high drain voltage), however, a negative transconductance dispersion becomes dominant. The drain conductance does not show a dispersion in the linear region, while a distinct positive dispersion is observed in the saturation region with the same activation energy as the negative transconductance dispersion. The difference of the dispersion activation energy of the MESFET with and without the p-buried layer beneath the channel indicates that the negative transconductance and the drain conductance dispersion are caused by the deep-level traps at the channel-substrate interface. Because there exists the high electric field at the drain edge of the gate and an electron accumulation layer is formed, the potential in the channel becomes lower when the drain current is larger with high gate voltage. The emission of electrons from electron traps with lower potential is the cause of the negative frequency dispersion.     

Study of the Drain Leakage Current in Bottom-Gated Nanocrystalline Silicon Thin-Film Transistors by Conduction and Low-Frequency Noise Measurements

The drain leakage current in n-channel bottom-gated nanocrystalline silicon (nc-Si) thin-film transistors is investigated systematically by conduction and low-frequency noise measurements. The presented results indicate that the leakage current, controlled by the reverse biased drain junction, is due to Poole-Frenkel emission at low electric fields and band-to-band tunneling at large electric fields. The leakage current is correlated with single-energy traps and deep grain boundary trap levels with a uniform energy distribution in the band gap of the nc-Si. Analysis of the leakage current noise spectra indicates that the grain boundary trap density of 8.5 times 10¹² cm ^-2 in the upper part of the nc-Si film is reduced to 2.1 times 10¹² cm^-2 in the lower part of the film, which is attributed to a contamination of the nc-Si bulk by oxygen     

Effects of traps on thin film transistors

Trap effects on Weimer-type thin film transistors (TFT) were studied. Measurements of thermally stimulated current (TSC), temperature dependence of drain current and MOS structure capacitance were performed to study trap distribution in TFT's. It was found that the steady state Fermi level lies near to the conduction band (0·1–0·05 eV) in the TFT. Only those traps lying near or above the Fermi level can affect the performance of TFT. Drain current relaxation effects for a step-gate voltage, and drain current hysteresis for a sine-wave gate voltage, were studied as trap effects on TFT performance. These phenomena were interpreted in terms of trap kinetics, and the roles of traps in the insulator film and in the semiconductor film were identified. The energy depth, density and cross section of traps affecting TFT performance were estimated.     

Influence of the dynamic access resistance in the g/sub m/ and f/sub T/ linearity of AlGaN/GaN HEMTs

The decrease of transconductance g/sub m/ and current gain cutoff frequency f/sub T/ at high drain current levels in AlGaN/GaN high-electron mobility transistors (HEMTs) severely limits the linearity and power performance of these devices at high frequencies. In this paper, the increase of the differential source access resistance r/sub s/, with drain current is shown to play an important role in the fall of g/sub m/ and f/sub T/. The increase of r/sub s/ occurs due to the quasi-saturation of the electron velocity in the source region of the channel at electric fields higher than 10 kV/cm. This has been confirmed by both experimental measurements and two-dimensional drift-diffusion simulations. Through simulations, we have identified HEMT structures with source implanted regions (or n/sup ++/ cap layers) as good candidates in order to increase the linearity of the g/sub m/ and f/sub T/ versus current profile.     

50-nm T-gate metamorphic GaAs HEMTs with f/sub T/ of 440 GHz and noise figure of 0.7 dB at 26 GHz

GaAs-based transistors with the highest f/sub T/ and lowest noise figure reported to date are presented in this letter. A 50-nm T-gate In/sub 0.52/Al/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/As metamorphic high-electron mobility transistors (mHEMTs) on a GaAs substrate show f/sub T/ of 440 GHz, f/sub max/ of 400 GHz, a minimum noise figure of 0.7 dB and an associated gain of 13 dB at 26 GHz, the latter at a drain current of 185 mA/mm and g/sub m/ of 950 mS/mm. In addition, a noise figure of below 1.2 dB with 10.5 dB or higher associated gain at 26 GHz was demonstrated for drain currents in the range 40 to 470 mA/mm at a drain bias of 0.8 V. These devices are ideal for low noise and medium power applications at millimeter-wave frequencies.     

Role of velocity saturation in lifting pinchoff condition in long-channel MOSFET

The role of velocity saturation due to high-field mobility degradation in lifting the pinchoff condition in a long-channel MOSFET is described. The electric field on the drain end at the onset of current saturation is always extremely high leading to the velocity saturation of the carriers. This velocity saturation leads to the saturation value n/sub sD/=n/sub so/V/sub g/'/2V/sub c/=I/sub Dsat//q nu /sub th/ W on the drain end, in contrast with the well-known pinchoff behaviour, where the carrier density is shown to vanish at the saturation point. The carrier distribution, as well as the velocity distribution as a function of the channel distance along the length of the channel, is presented.<>     

547-GHz f/sub t/ In/sub 0.7/Ga/sub 0.3/As-In/sub 0.52/Al/sub 0.48/As HEMTs with reduced source and drain resistance

We fabricated 30-nm gate pseudomorphic channel In/sub 0.7/Ga/sub 0.3/As-In/sub 0.52/Al/sub 0.48/As high electron mobility transistors (HEMTs) with reduced source and drain parasitic resistances. A multilayer cap structure consisting of Si highly doped n/sup +/-InGaAs and n/sup +/-InP layers was used to reduce these resistances while enabling reproducible 30-nm gate process. The HEMTs also had a laterally scaled gate-recess that effectively enhanced electron velocity, and an adequately long gate-channel distance of 12nm to suppress gate leakage current. The transconductance (g/sub m/) reached 1.5 S/mm, and the off-state breakdown voltage (BV/sub gd/) defined at a gate current of -1 mA/mm was -3.0 V. An extremely high current gain cutoff frequency (f/sub t/) of 547 GHz and a simultaneous maximum oscillation frequency (f/sub max/) of 400 GHz were achieved: the best performance yet reported for any transistor.     

Leakage current and defect characterization of pn-source/drain diodes

A good control of the transient enhanced dopant diffusion is needed for MOSFET scaling down to the sub 50 nm regime. Carbon ion implant is known to significantly suppress the transient enhanced boron diffusion. However, carbon implantation is also reported to increase diode leakage current. This paper investigates the impact of ion implantation and annealing conditions during source/drain extension formation on leakage current behavior of boron/phosphorous diodes of PFET transistors. Analyzing the leakage current it is difficult to distinguish between the influence of the increased electric field due to the reduced diffusion and possible additional trap centers in the space charge region. This distinction can be made by electrical characterization, as shown in this paper. The leakage current mechanism is found to be trap assisted tunneling with phonon interaction. The corresponding trap energy within the band gap is 0.58 ± 0.10 eV. The carbon concentration in the space charge region measured by SIMS is below the detection limit. Also in electrical measurements, which are more sensitive, no significant influence of carbon related traps is observed. The leakage current is increased by the application of a Flash Anneal additionally to a Rapid Thermal Anneal for recrystallization of the silicon substrate.     

Profiling interface traps in MOS transistors by the DCcurrent-voltage method

Position profiling the interface trap density along the channel length of metal-oxide-silicon transistors by the Direct-Current Current-Voltage method is illustrated for five density variations: zero, peaked in drain junction space-charge layer, constant in channel, nonconstant in channel, and peaked in drain junction space-charge layer and nonconstant in channel. The interface trap densities were monitored by MOS transistor's d.c. body current and the density profiles were obtained from the body-drain and body-source differential conductance versus drain or source bias voltage. An experimental demonstration is given for a 1.6 μm n-channel Si MOS transistor with about 10¹¹ traps/cm² generated by channel hot electron stress     

Characterization of deep levels in modulation-doped AlGaAs/GaAs FET's

Deep levels in modulation-doped field-effect transistors (MODFET's) fabricated from MBE-grown AlGaAs/GaAs heterostructures, have been characterized by a modified deep-level transient spectroscopy (DLTS) technique. Assuming donor-like traps in the AlGaAs layer, it is shown that the threshold voltage Vtvaries exponentially with time under pulsed-biased conditions. This result is verified experimentally by observing the transient in the drain current IDin long-gate FET's biased in saturation. The resulting Δ √{I_{D}} DLTS spectrum reveals an electron trap with an activation energy of 0.472 eV in Si-doped Al0.3Ga0.7As.     

High-field effects in silicon nitride passivated GaN MODFETs

This paper presents a detailed study of high-field effects in GaN MODFETs. Degradation of DC characteristics and change of flicker noise due to hot electron and high-reverse current stresses in Si/sub 3/N/sub 4/ passivated GaN MODFETs have been investigated. The authors observe that during hot electron stress, electron trapping in the barrier layer and interface state creation occur. These cause a positive shift of V/sub t/, reduce I/sub D/, skew the transfer characteristics, and degrade g/sub m/. Flicker noise (1/f) measurements show that after hot electron stress, the scaled drain current noise spectrum (S/sub I(D)//I/sub D//sup 2/) decreases in depletion, but increases only slightly in strong accumulation, corroborating the creation of interface states but only a small creation of transition-layer tunnel traps that contribute to 1/f noise. During high-reverse current stress, electron trapping dominates for the first 50-60 s and then hole trapping and trap creation begin to manifest. However, there still is net electron trapping under the gate after one hour of stress. The degradation processes bring about a positive shift of V/sub t/, degrade I/sub D/ and g/sub m/, and increase reverse leakage. After high-reverse current stress, S/sub I(D)//I/sub D//sup 2/ increases substantially in strong accumulation, indicating the creation of transition layer tunnel traps.     

Drain-bias dependence of threshold voltage stability of amorphous silicon TFTs

Amorphous silicon (a-Si:H) thin-film transistors (TFTs) used in emerging, nonswitch applications such as analog amplifiers or active loads, often have a bias at the drain terminal in addition to the gate that can alter their threshold voltage (V/sub T/) stability performance. At small gate stress voltages (0/spl les/V/sub ST//spl les/15 V) where the defect state creation instability mechanism is dominant, the presence of a bias at the TFT drain decreases the overall shift in V/sub T/(/spl Delta/V/sub T/) compared to the /spl Delta/V/sub T/ in the absence of a drain bias. The measured shift in V/sub T/ appears to agree with the defect pool model that the /spl Delta/V/sub T/ is proportional to the number of induced carriers in the a-Si:H channel.     

Gate-induced drain leakage current degradation and its time dependence during channel hot-electron stress in n-MOSFETs

The effects of channel hot-electron stress on the gate-induced drain leakage current (GIDL) in n-MOSFETs with thin gate oxides have been studied. It is found that under worst case stress, i.e. a high density of generated interface states Delta D/sub it/, the enhanced GIDL exhibits a significant drain voltage dependence. Whereas Delta D/sub it/ increases significantly the leakage current at low V/sub d/, it has minor effects at high V/sub d/. On the other hand, the electron trapping was found to increase the leakage current rather uniformly over both low and high V/sub d/ regions. In addition, GIDL degradation can be expressed as a power law time dependence (i.e. Delta I/sub leak/=A.t/sup n/), and the time dependence value n varies according to the dominant damage mechanism (i.e. electron trapping against Delta D/sub it/), similar to that reported for on-state device degradation.<>     

Mapping charge carrier density in organic thin-film transistors by time-resolved photoluminescence lifetime studies

The device performance of organic transistors is strongly influenced by the charge carrier distribution. A range of factors effect this distribution, including injection barriers at the metal-semiconductor interface, the morphology of the organic film, and charge traps at the dielectric/organic interface or at grain boundaries. In our comprehensive experimental and analytical work we demonstrate a method to characterize the charge carrier density in organic thin-film transistors using time-resolved photoluminescence spectroscopy. We developed a numerical model that describes the electrical and optical responses consistently. We determined the densities of free and trapped holes at the interface between the organic layer and the SiO₂ gate dielectric by comparison to electrical measurements. Furthermore by applying fluorescence lifetime imaging microscopy we determine the local charge carrier distribution between source and drain electrodes of the transistor for different biasing conditions. We observe the expected hole density gradient from source to drain electrode.     

DC, RF, and microwave noise performances of AlGaN/GaN HEMTs on sapphire substrates

High-performance AlGaN/GaN high electron-mobility transistors with 0.18-/spl mu/m gate length have been fabricated on a sapphire substrate. The devices exhibited an extrinsic transconductance of 212 mS/mm, a unity current gain cutoff frequency (f/sub T/) of 101 GHz, and a maximum oscillation frequency (f/sub MAX/) of 140 GHz. At V/sub ds/=4 V and I/sub ds/=39.4 mA/mm, the devices exhibited a minimum noise figure (NF/sub min/) of 0.48 dB and an associated gain (Ga) of 11.16 dB at 12 GHz. Also, at a fixed drain bias of 4 V with the drain current swept, the lowest NFmin of 0.48 dB at 12 GHz was obtained at I/sub ds/=40 mA/mm, and a peak G/sub a/ of 11.71 dB at 12 GHz was obtained at I/sub ds/=60 mA/mm. With the drain current held at 40 mA/mm and drain bias swept, the NF/sub min/,, increased almost linearly with the increase of drain bias. Meanwhile, the Ga values decreased linearly with the increase of drain bias. At a fixed bias condition (V/sub ds/=4 V and I/sub ds/=40 mA/mm), the NF/sub min/ values at 12 GHz increased from 0.32 dB at -55/spl deg/C to 2.78 dB at 200/spl deg/C. To our knowledge, these data represent the highest f/sub T/ and f/sub MAX/, and the best microwave noise performance of any GaN-based FETs on sapphire substrates ever reported.     

Slow transients observed in AlGaN/GaN HFETs: effects of SiN/sub x/ passivation and UV illumination

Very slow drain current and surface potential transients have been observed in AlGaN/GaN heterostructure field effect transistors that are subjected to high bias stress. Simultaneous measurements of drain current and surface potential indicate that large change in surface potential after stress is responsible for the reduction in drain current in these devices. Measurements of surface potential profile from the gate edge toward the drain as a function of time indicate that surface potential changes occur mostly near the gate. It is proposed that the surface potential changes are caused by electrons which tunnel from the gate under high bias stress and get trapped at the surface states near the gate. Passivation of the surface with SiN/sub x/ reduces the transient magnitudes to a large extent. This correlates with a large improvement in microwave power performance in these devices after passivation. UV illumination of these devices totally eliminates the drain current and surface potential transients.     

High-energy tail electrons as the mechanism for the worst-case hot-carrier stress degradation of the deep submicrometer N-MOSFET

Experimental evidence, based on sensitively modulating the concentration of the high-energy tail of the electron energy distribution, reveals an important trend in the mid-to-high gate stress voltage (V/sub g/) regime, where device degradation is seen to continuously increase with the applied V/sub g/, for a given drain stress voltage V/sub d/. The shift in the worst-case degradation point from V/sub g//spl ap/V/sub d//2 to V/sub g/=V/sub d/, depicting an uncorrelated behavior with the substrate current, is caused by the injection of the high-energy tail electrons into the gate oxide, when the oxide field near the drain region becomes increasingly favorable as V/sub g/ approaches V/sub d/. This letter offers an improved framework for understanding the worst-case hot-carrier stress degradation of deep submicrometer N-MOSFETs under low bias condition.