A single-chip 2B1Q U-interface transceiver

A single-chip transceiver designed to meet the American National Standards Institute (ANSI) requirements for the U-interface in the integrated services digital network (ISDN) is described. The device utilizes linear, jitter-compensated, and nonlinear echo cancellation and the 2B1Q line code to achieve high performance in the presence of near-end crosstalk and other impairments. The 2-μm, single-metal, double-polysilicon, 5-V CMOS VLSI chip includes all the necessary analog and digital signal processing blocks for a network-termination of line-termination U-interface to be realized with the addition of a passive-line termination circuit and a transformer. Operation over 4.7 km of 0.4-mm cable or 7.5 km of 0.5-mm cable, with a bit error rate of 10^-7, is possible     

An ISDN echo-cancelling transceiver chip set for 2B1Q coded U-interface

A three-chip set for a 2B1Q U-interface transceiver has been developed. The chip set is composed of an analog front-end (AFE), echo-canceller (EC), and receiver (RCV) LSIs. The AFE LSI includes a 12-b accuracy oversampling analog/digital converter. The EC and RCV LSIs are 26- and 16-bit microprogrammable digital signal processors, respectively. A digital phase-locked loop is used to minimize the analog part. Residual echo increase by a timing phase jump is compensated for by a newly introduced additional adaptive filter. Infinite impulse response filters and multiresponse filters reduce the necessary number of taps for both the echo canceller and the decision-feedback equalizer. The AFE and the two digital signal processor LSIs are implemented in 1.6- and 1.2-μm double-metal layer CMOS processes, respectively. A 6-km loop coverage was realized with a less than 10^-7 error rate. Total power consumption by the chip set is 580 mW at 5-V single supply     

A rate adaption coprocessor for terminal adapters andU-interface modems

A multistandard rate adapter coprocessor chip, designed for use in ISDN terminal adapters and U-interface modems, is presented. It provides a compact, low-power protocol converter to connect asynchronous (up to 19200 b/s) and synchronous (up to 64 kb/s) data terminal equipment with any digital 64-kb/s network. The multistandard rate adapter chip was developed in a 2-μm CMOS technology using a hierarchical design methodology. The rate adapter is the cornerstone of a 144-kb/s U-interface modem and a major breakthrough for the next-generation multistandard terminal adapter     

U-band shield suspended-stripline Gunn DRO and VCO

A millimeter-wave IC dielectric resonator oscillator (DRO) is proposed. Equations that give the resonant frequency of the dielectric resonator DR in suspended stripline (SSL) are derived. A U-band voltage-controlled oscillator (VCO) with varactor tuning also has been developed. The Gunn diode and varactor used in both of the oscillators are commercially available packaged devices. Restrictions on the performance of the oscillators imposed by packaged and mounted networks and the self-characteristics of the solid-state devices have been analyzed. An electronic tuning range greater than 1000 MHz with an output power exceeding 15 dBm across the bandwidth in the 53-GHz region has been realized for the SSL VCO. An SSL DRO with an output power of more than 17 dBm and a mechanical tuning range of 1.5 GHz in the 54-GHz region has been achieved     

Fully digital M-ary PSK and M-ary QAMdemodulators for land mobile satellite communications

A fully digital implementation of digital modems is the preferred option of system designers because high performance can be achieved at reasonable cost. The author explains the beneficial features inherent in fully digital demodulator implementations. Other features which are required for land mobile satellite communication systems are also discussed. Recently reported techniques for the synchronisation and detection of M-ary PSK and M-ary QAM modulation schemes are reviewed with emphasis placed on those which are well suited to digital implementation     

The number of digital straight lines on an N×N grid

The number of digital straight lines on an N×N grid is shown. A digital straight line is equivalent to a linear dichotomy of points on a square grid. The result is obtained by determining a way of counting the number of linearly separable dichotomies of points on the plane that are not necessarily in general position. The analysis is easily modified to provide a simple solution to a similar problem considered by C. Berenstein and D. Lavine (1988) on the number of digital straight lines from a fixed starting point     

A single-chip CMOS analog/digital mixed NTSC decoder

A single-chip CMOS LSI that integrates all analog-to-digital (A/D), digital-to-analog (D/A), peripheral, and digital signal processing circuits necessary for a digital National Television System Committee (NTSC) signal decoder is described. The LSI chip accepts composite NTSC video signals in analog form, digitizes them using the on-chip A/D converter, converts them to component RGB signals, and then converts the signals to analog form by using the on-chip D/A converters. The development of circuits that maximize use of the input digital data is discussed. A 6-b A/D circuit is used to reduce the circuit size. Circuits that help maintain acceptable picture quality despite 6-b resolution were developed. Besides analog NTSC signal input and RGB signal output, the IC can also input and output digital NTSC signals, Y/C (luminance, chrominance) signals, and RGB signals. Applications of the LSI are presented     

Correction of (sin x)/x distortion introduced bydiscrete-time/continuous-time signal conversion

A new analytical method is proposed for the correction of the (sin x)/x distortion which is characteristic of the spectra of discrete-time signals converted to continuous-time waveforms. The method is based on the adjustment of the quality factors associated with the poles of the reconstruction filter transform function. Simulation results show that, in spite of its simplicity, the new technique yields significant improvements in the frequency spectrum of the continuous-time signal after the conversion     

Order N log2 N WHT/DHT algorithm

An efficient algorithm is proposed which computes the coefficients of the higher order discrete Hartley transform (DHT) directly from the coefficients of lower-order DHTs. With this new development, the two-stage Walsh-Hadamard transform/discrete Hartley transform (WHT/DHT) is comparable to the existing fast algorithms. The same approach can also be used for the computation of DCT coefficients     

Robustness of mean E{X} and R charts

The effect of nonnormality on E{X} and R charts is reported. The effect of departure from normality can be examined by comparing the probabilities that E{X} and R lie outside their three-standard-deviation and two-standard-deviation control limits. Tukey's λ-family of symmetric distributions is used because it contains a wide spectrum of distributions with a variety of tail areas. The constants required to construct E{X} and R charts for the λ-family are computed. Control charts based on the assumption of normality give inaccurate results when the tails of the underlying distribution are thin or thick. The validity of the normality assumption is examined by using a numerical example     

A single-chip GaAs RF transceiver for 1.9-GHz digital mobilecommunication systems

A 1.9-GHz single-chip GaAs RF transceiver has been successfully developed using a planar self-aligned gate FET suitable for low-cost and high-volume production. This IC includes a negative voltage generator for 3-V single voltage operation and a control logic circuit to control transmit and receive functions, together with RF front-end analog circuits-a power amplifier, an SPDT switch, two attenuators for transmit and receive modes, and a low-noise amplifier. The IC can deliver 22-dBm output power at 30% efficiency with 3-V single power supply, The new negative voltage generator operates with charge time of less than 200 ns, producing a low level of spurious outputs below -70 dBc through the power amplifier. The generator also suppresses gate-bias voltage deviations to within 0.05 V even when gate current of -144 μA flows. The IC incorporates a new interface circuit between the logic circuit and the switch which enables it to handle power outputs over 24 dBm with only an operating voltage of 3 V. This transceiver will be expected to enable size reductions in telephones for 1.9-GHz digital mobile communication systems     

Modeling the gate I/V characteristic of a GaAsMESFET for Volterra-series analysis

The authors show that the Taylor-series coefficients of a FET's gate/drain I/V characteristic, which is used to model this nonlinearity for Volterra-series analysis, can be derived from low-frequency RF measurements of harmonic output levels. The method circumvents many of the problems encountered in using DC measurements to characterize this nonlinearity. This method was used to determine the incremental gate I/V characteristic of a packaged Aventek AT10650-5 MESFET biased at a drain voltage of 3 V and drain current of 20 mA. The FET's transconductance was measured at DC, and its small-signal equivalent circuit (including the package parasitics) was determined by adjusting its circuit element values until good agreement between calculated and measured S parameters was obtained. The FET was then installed in a low-frequency test fixture. Excellent results were obtained     

Optimum control of N-input K-output matrixconverters

Significant developments of the general optimum control theory presented in a previous paper by the authors (1988) are discussed for the specific case of multiphase matrix converters. Results hold, regardless of system configuration, input and output voltage waveforms, and loads. Applications to the most practical converter structures are illustrated, and implementation criteria of the optimum control method are derived. Simulated results confirm the flexibility and effectiveness of the approach     

An O(kn) algorithm for a circularconsecutive-k-out-of-n:F system

An O(k×n) algorithm is described for evaluating the reliability of a circular consecutive-k-out- n:F system     

A technique for real-time measurement of Nth-orderderivativesdNV/dIN

A technique for the measurement of device derivatives d ^NV/dI^N of arbitrary order N described. Measurement is accomplished by injecting a test current composed of the sum of N square waves into the rest device, and then multiplying the corresponding voltage change by the product of those same square waves, followed by low-pass filtering. The algorithm is implemented in real time using a mixture of analog and digital circuitry, and its application to semiconductor laser control in high-speed optical communications is described     

A monolithic digital chirp synthesizer chip with I andQ channels

A monolithic digital chirp synthesizer (DCS) chip has been developed using GaAs/AlGaAs HI²L technology. The 6500-HBT-gate DCS chip is capable of producing linear frequency-modulated (chirp) waveforms or single-frequency waveforms. The major components of the DCS are two 28-b pipelined accumulators, a 1.8 kb sine ROM, a 1.8 kb cosine ROM, and two 8 b digital-to-analog converters (DACs). The total chip area is 4.877 mm×6.172 mm using a minimum feature size of 1.5 μm. All components of the DCS are fully functional and the device has been clocked to 450 MHz with a power dissipation of 18 W     

CMOS analog front end of a transceiver with digital echocancellation for ISDN

A CMOS analog front-end which contains a novel pulse-shaping circuit, an extremely linear-line-driver state, an oversampling second-order noise-shaping coder, and a wake-up signal detector is discussed. An analog front-end for 4B 3T coded signals is realized in a 2.5-μm CMOS technology and operates up to 4.5 km with 0.4-mm-diameter lines, needing only one 5-V power supply. It is possible to transmit 2B 1Q coded signals also, using a modified pulse-shaping circuit     

Spectral shaping and digital synthesis of an M-ary timeseries

The use of pulse shaping to control transmitted spectral density precisely is examined. A digital filter architecture is described that not only mitigates the traditional problems of lengthy development intervals and cost manufacturing methods, but offers the additional features of intrinsically coding high-speed binary (M=2) data into M-ary symbols while ensuring highly reproducible, baud-normalized, transmitter pulse shaping. A conceptual basis for the digital synthesis method is first described, including a functional circuit appropriate to the simplest filter realizations. Spectral effects internal to the filter are considered, and a simple method to obtain desired transmitted spectra is outlined. It is shown that even relatively short pulses used in high-level modulation systems lead to impractical memory storage demands; however, the simple expedient of segmenting the finite impulse function greatly reduced the individual memory requirements, though it necessitates intermediate adding operations. Experimental examples illustrate the design methodology for quaternary (M=4) data signals in a Nyquist communication channel and serve as points of reference for addressing performance and design flexibility     

DC-20 GHz N×M passive switches

High-order, bidirectional, DC-20-GHz switch networks are discussed. Single-chip 1×2, 1×4, and 2×2 switch MMICs have been demonstrated. Multiple chips have been used to demonstrate 4×4 and 1×16 switches. The switches all use a combination of series and shunt passive FET switching elements. The 1×4 switch is made of a single stage of switching elements, rather than the usual two stages of 1×2 switches. The 2×2 switch is comprised of two stages of 1×2 switches. The multiple-chip 4×4 switch is made of four stages of 1×2 switches (using the 2×2 switch MMICs). Two stages of 1×4 switches are used to make the 1×16 switch