VHDL语言分析器的设计与实现

ＶＨＤＬ高级综合系统是逻辑设计领域的热点，作为其前端的ＶＨＤＬ语言分析器是综合系统中其它各子系统（如综合、模拟等）的支撑，它生成ＶＨＤＬ源描述的中间格式并将此结果存入数据库供其它子系统引用。本文重点介绍基于ＶＨＤＬ ＩＥＥＥ１０７６－１９８７全集的ＶＨＤＬ语言分析器的设计与实现技术，并给出了有关结果，该分析器通过了许多实例。     

RTL综合中的格式剖别

由于寄存器传输级（RTL）行为描述可以精确地确定数字系统的操作,所以寄存器传输级综合成为当前EDA行业的主流设计方法。实现从寄存器传输级行为描述到门级结构描述转换的RTL综合,是组合逻辑／时序逻辑综合理论在HDL（硬件描述语言）上的具体应用。设计寄存器传输级综合工具的基础是格式判别,即将行为描述中的组合逻辑与时序逻辑区分开来,利用组合逻辑综合与时序逻辑综合分别进行处理从而完成寄存器传输级综合,提出一种易于实现的格式判别方法,该方法利用赋值语句为核心的中间数据格式以及逻辑综合所能接受的条件判断此赋值语句组合是组合逻辑还是时序逻辑,并生成不同层次、功能相对独立的RT单元以便利用对应的组合逻辑综合或时序逻辑综合处理此RT单元,从而在实现RTL综合的过程中使组合逻辑综合和时序逻辑综合得到最大限度的重用。最后文中给出一些测试实例和结果分析,通过测试实例和结果分析表明该文提出手方法不但有效地区分了组合逻辑和时序逻辑,而且由于通过对组合逻辑综合和时序逻辑综合最大限度的重用,使寄存器传输级综合的开发时间大大缩短,此方法已经用于作者的RTL综合系统中。     

扩展的高层次行为描述内部模型

随着片上系统(SOC)技术的发展,越来越多的功能模块被集成到单一芯片中。适合硬件描述的HDL语言很难满足实现复杂算法功能的要求,C++等高级语言可以高效地描述算法功能,但是在综合和验证时遇到很大困难。文章介绍了一种允许使用C和VHDL独立描述原始模块,通过创建统一内部模型IIR的办法实现对功能元件和算法模块的混合处理。IIR内部模型以XML文件格式作为外部存储,能够方便地被划分、综合、验证等处理程序使用,避免了重复的原始描述文件分析,提高了研发效率。     

Hardware assisted high-level debugging

Hardware assistance has long been used for logic level and functional unit level hardware debugging, as well as for machine language level software debugging. Such hardware assistance includes probes to detect signals, comparators to identify matches with expected patterns, buffers to record selected events, and independent logic and software to analyze and interpret the observed events. It can also include the ability to generate selected signals to stimulate the object being debugged and the ability to isolate it from normal changes so its state can be examined. Through knowledge of the data structures and algorithms used by the operating systems, and the runtime representation, register usage, and code bursts produced by compilers, it is possible to take advantage of such hardware assistance in high-level debugging. High-level debugging here refers to debugging in terms of abstractions supported by the operating system and programming languages, as well as user defined abstractions built on top of these. This paper discusses design considerations behind a project to build such a hardware assisted high-level debugger.     

High-level synthesis,cryptography, and side-channel countermeasures: A comprehensive evaluation

Side-channel attacks pose a severe threat to both software and hardware cryptographic implementations. Current literature presents various countermeasures against these kinds of attacks, based on approaches such as hiding or masking, implemented either in software, or on register–transfer level or gate level in hardware. However, emerging trends in hardware design lean towards a system-level approach, allowing for faster, less error-prone, design process, an efficient hardware/software co-design, or sophisticated validation, verification, and (co)simulation strategies. In this paper, we propose a Boolean masking scheme suitable for high-level synthesis of substitution–permutation network-based encryption. We implement both unprotected and protected PRESENT, AES/Rijndael and Serpent encryption in C language, utilizing the concept of dynamic logic reconfiguration, synthesize it for Xilinx FPGA, and we compare our results regarding time and area utilization. We evaluate the effectiveness of proposed countermeasures using both specific and non-specific t-test leakage assessment methodology. We discuss the leakage assessment results, and we identify and discuss the related limitations of the system-level approach and the high-level synthesis.