栅长为83-nm的毫米波低噪声InP基PHEMTs的研制

本文设计并实现了一种83-nm T型栅的InP基In0.52Al0.48As/In0.65Ga0.35As赝配高电子迁移率晶体管（PHEMT）。该器件的总栅宽为2×30μm,展现了良好的DC直流、RF射频以及低噪声特性,包括最大饱和电流密度Idss和最大有效跨导gm,max分别为894mA/mm和1640mS/mm。基于1~110 GHz全频段在片测试的S参数外推获得的最大截止频率ft和最大振荡频率fmax分别为247GHz和392GHz。测得的器件拐点（稳定因子k=1）频率为102GHz,因此,基于拐点外推获得的fmax更加准确。采用冷源法完成器件的在片噪声参数的测试,测得的最小噪声系数NFmin在30GHz时为1dB,相关增益Gass为14.5dB。这些良好结果的获得是由于沟道层中InAs摩尔组分的增加,沟道层厚度的减小,栅长的缩短以及寄生效应的减小。这些优良的特性使得该器件非常适合于毫米波频段低噪声单片集成电路的应用。     

Ultra low noise characteristics of AlGaAs/InGaAs/GaAs pseudomorphicHEMT's with wide head T-shaped gate

The fully passivated low noise AlGaAs/InGaAs/GaAs pseudomorphic (PM) HEMT with 0.13 μm T-shaped gate was fabricated using dose split electron beam lithography method (DSM). This device exhibited low noise figures of 0.31 and 0.45 dB at 12 and 18 GHz, respectively. These noise figures are the lowest value ever reported for the GaAs based HEMT's. These results are attributed to the extremely low gate resistance which results from wide head T-shaped gate having the higher ratio more than 10 of gate head length to gate footprint     

Improvement on the noise performance of InAs-based HEMTs with gate sinking technology

Improvement on the RF and noise performance for 80 nm InAs/In_0.7Ga_0.3As high-electron mobility transistor (HEMT) through gate sinking technology is presented. After gate sinking at 250 °C for 3 min, the device exhibited a high transconductance of 1900 mS/mm at a drain bias of 0.5 V with 1066 mA/mm drain-source saturation current. A current-gain cutoff frequency (f_T) of 113 GHz and a maximum oscillation frequency (f_max) of 110 GHz were achieved at extremely low drain bias of 0.1 V. The 0.08 × 40 μm² device with gate sinking demonstrated 0.82 dB minimum noise figure and 14 dB associated gain at 17 GHz with only 1.14 mW DC power consumption. Significant improvement in RF and noise performance was mainly attributed to the reduction of gate-to-channel distance together with the parasitic source resistance through gate sinking technology.     

A 2-18 GHz low-noise/high-gain amplifier module

The effectiveness of the two-tier matrix amplifier as a very-low-noise device with very high associated gains across multioctave frequency bands is theoretically and experimentally demonstrated. Experimental modules whose topology is based on a computer-optimized design exhibit an average noise figure of F=3.5 dB with an associated average gain of G=17.8 dB across the 2-18 GHz frequency band. These state-of-the-art results were achieved with GaAs MESFETs whose minimum noise figure is F=2.2 dB at 18 GHz and whose gate dimensions are 0.25×200 μm. The design considerations and the test results are discussed in detail     

Extremely low-noise performance of GaAs MESFETs with wide-headT-shaped gate

Fully ion-implanted low-noise GaAs MESFETs with a 0.11-μm Au/WSiN T-shaped gate have been successfully developed for applications in monolithic microwave and millimeter-wave integrated circuits (MMICs). In order to reduce the gate resistance, a wide Au gate head made of a first-level interconnect is employed. As the wide gate head results in parasitic capacitance, the relation between the gate head length (L_h) and the device performance is examined. The gate resistance is also precisely calculated using the cold FET technique and Mahon and Anhold's method. A current gain cutoff frequency (f_T) and a maximum stable gain (MSG) decrease monotonously as L_h increases on account of parasitic capacitance. However, the device with L_h of 1.0 μm, which has lower gate resistance than 1.0 Ω, exhibits a noise figure of 0.78 dB with an associated gain of 8.7 dB at an operating frequency of 26 GHz. The measured noise figure is comparable to that of GaAs-based HEMT's     

0.3 dB minimum noise figure at 2.5 GHz of 0.13 μm Si/Si0.58Ge0.42 n-MODFETs

RF and microwave noise performances of strained Si/Si_0.58 Ge_0.42 n-MODFETs are presented for the first time. The 0.13 μm gate devices have de-embedded f_T=49 GHz, f_max =70 GHz and a record intrinsic g_m=700 mS/mm. A de-embedded minimum noise figure NF_min=0.3 dB with a 41 Ω noise resistance R_n and a 19 dB associated gain G_ass are obtained at 2.5 GHz, while NF_min=2.0 dB with G_ass=10 dB at 18 GHz. The noise parameters measured up to 18 GHz and from 10 to 180 mA/mm with high gain and low power dissipation show the potential of SiGe MODFETs for mobile communications     

Enhanced characteristics in gate-recessed and sidewall-recessed AlGaAs/InGaAs PHEMTs by citric-based selective wet etching

Improved device performance in Al_0.2Ga_0.8As/In_0.15Ga_0.85As gate-recessed enhancement-mode pseudomorphic high electron mobility transistors (E-PHEMTs) and sidewall-recessed depletion-mode PHEMTs (D-PHEMTs) using a newly developed citric buffer etchant are reported. The innovated etchant near room temperature (23°C) possesses a high GaAs/Al_0.2Ga_0.8As or In_0.15Ga_0.85As/Al_0.2Ga_0.8As etching selectivity (>250) applied to an etched stop surface. For E-PHEMTs, the transconductance (G_m) of 315?mS/mm and high linearity of 0.46?V-wide gate voltage swing (drop of 10% peak G_m), corresponding to 143?mA/mm-wide I_DS, even at a gate length of 1?µm is obtained. For microwave operation, this 1?µm-gate E-PHEMT shows the f_max (maximum operation frequency) of 29.2?GHz and the f_T (cut-off frequency) of 11.2?GHz, respectively. The measured minimum noise figure (NF_min), under V_DS?=?3?V and I_DS?=?7.5?mA, is 0.56?dB at 1?GHz with the associated gain of 10.86?dB. The NF_min is less than 1.5?dB in the frequency range from 1 to 4?GHz. In addition, an effective and simple method of selective gate sidewall recess is utilized to etch the low barrier in In_0.15Ga_0.85As channel at mesa sidewalls for D-PHEMTs. For D-PHEMTs with 1?×?100?µm² exhibit a very low gate leakage current of 2.4?μA/mm even at V_GD?=??10?V and high gate breakdown voltage over 25?V. As compared to that of no sidewall recess, nearly two orders of reduction in magnitude of gate leakage current and 100% improvement in gate breakdown voltage are achieved.     

DC and RF Characteristics of 0.15 pm Power Metamorphic HEMTs

DC and RF characteristics of 0.15 °m GaAs power metamorphic high electron mobility transistors (MHEMT) have been investigated. The 0.15 °m ° 100 °m MHEMT device shows a drain saturation current of 480 mA/mm, an extrinsic transconductance of 830 mS/mm, and a threshold voltage of ‐0.65 V. Uniformities of the threshold voltage and the maximum extrinsic transconductance across a 4‐inch wafer were 8.3% and 5.1%, respectively. The obtained cut‐off frequency and maximum frequency of oscillation are 141 GHz and 243 GHz, respectively. The 8 ° 50 °m MHEMT device shows 33.2% power‐added efficiency, an 18.1 dB power gain, and a 28.2 mW output power. A very low minimum noise figure of 0.79 dB and an associated gain of 10.56 dB at 26 GHz are obtained for the power MHEMT with an indium content of 53% in the InGaAs channel. This excellent noise characteristic is attributed to the drastic reduction of gate resistance by the T‐shaped gate with a wide head and improved device performance. This power MHEMT technology can be used toward 77 GHz band applications.     

Low-noise HEMT using MOCVD

Low-noise HEMT AlGaAs/GaAs heterostructure devices have been developed using metal organic chemical vapor deposition (MOCVD). The HEMT's with 0.5-µm-long and 200-µm-wide gates have shown a minimum noise figure of 0.83 dB with an associated gain of 12.5 dB at 12 GHz at room temperature. Measurements have confirmed calculations on the effect of the number of gate bonding pads On the noise figure for different gate Widths. Substantial noise figure improvement was observed Under low-temperature operation, especially compared to conventional GaAs MESFET's. A two-stage amplifier designed for DBS reception using the HEMT in the first stage has displayed a noise figure under 2.0 dB from 11.7 to 12.2 GHz.     

2.3–21 GHz broadband and high linearity distributed low noise amplifier

This paper focuses on the design of a 2.3–21 GHz Distributed Low Noise Amplifier (LNA) with low noise figure (NF), high gain (S₂₁), and high linearity (IIP3) for broadband applications. This distributed amplifier (DA) includes S/C/X/Ku/K-band, which makes it very suitable for heterodyne receivers. The proposed DA uses a 0.18 μm GaAs pHEMT process (OMMIC ED02AH) in cascade architecture with lines adaptation and equalization of phase velocity techniques, to absorb their parasitic capacitances into the gate and drain transmission lines in order to achieve wide bandwidth and to enhance gain and linearity. The proposed broadband DA achieved an excellent gain in the flatness of 13.5 ± 0.2 dB, a low noise figure of 3.44 ± 1.12 dB, and a small group delay variation of ±19.721 ps over the range of 2.3–21 GHz. The input and output reflection coefficients S₁₁ and S₂₂ are less than −10 dB. The input compression point (P_1dB) and input third-order intercept point (IIP3) are −1.5 dBm and 11.5 dBm, respectively at 13 GHz. The dissipated power is 282 mW and the core layout size is 2.2 × 0.8 mm².     

Very low-noise Al/sub 0.3/Ga/sub 0.7/As/Ga/sub 0.65/In/sub 0.35/As/GaAs single quantum-well pseudomorphic HEMTs

AlGaAs/GaInAs/GaAs pseudomorphic HEMTs with an InAs mole fraction as high as 35% in the channel has been successfully fabricated. The device exhibits a maximum extrinsic transconductance of 700 mS/mm. At 18 GHz, a minimum noise figure of 0.55 dB with 15.0 dB associated gain was measured. At 60 GHz, a minimum noise figure as low as 1.6 dB with 7.6 dB associated gain was also obtained. This is the best noise performance yet reported for GaAs-based HEMTs.<>     

Concurrent design of Schottky diode limiter and LNA

In this paper concurrent design of Schottky diode based limiter and low noise amplifier (LNA), based on noise matching, is investigated to achieve minimum noise figure (NF) of the receiver chain. In design procedure of the LNA, the noise figure is minimum, gain at central frequency is 14.5 dB, and limiter structure tolerates up to 5 W continuous wave input power. In the proposed concurrent design, a pass-band filter is applied at the LNA output to attenuate undesired out-of-band signals. In the proposed design, the limiter-LNA is implemented with a 0.25 µm gate length AlGaAs/InGaAs pHEMT process. Measured noise figure of chain is 2.7 dB and average gain over 8.5–9.5 GHz frequency range and the gain at 9 GHz center frequency are 10 dB and 14.5 dB respectively. The performance results of proposed matching network are compared with traditional 50 Ω matching networks in limiter-LNA with identical circuit specifications.

     

0.1-µm Gate-length pseudomorphic HEMT's

AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistors (HEMT's) with a gate length of 0.1 µm have been successfully fabricated. The HEMT's exhibit a maximum transconductance of 540 mS/mm with excellent pinch-off characteristics. A maximum stable gain (MSG) as high as 18.2 dB was measured at 18 GHz. At 60 GHz the device has demonstrated a minimum noise figure of 2.4 dB with an associated gain of ∼6 dB. These are the best gain and noise results reported to date for HEMT's.     

A low power high gain UWB LNA in 0.18-μm CMOS

A low power high gain differential UWB low noise amplifier (LNA) operating at 3-5 GHz is presented.A common gate input stage is used for wideband input matching; capacitor cross coupling (CCC) and current reuse techniques are combined to achieve high gain under low power consumption. The prototypes fabricated in 0.18-μm CMOS achieve a peak power gain of 17.5 dB with a -3 dB bandwidth of 2.8-5 GHz, a measured minimum noise figure (NF) of 3.35 dB and -12.6 dBm input-referred compression point at 5 GHz, while drawing 4.4 mA from a 1.8 V supply. The peak power gain is 14 dB under a 4.5 mW power consumption (3 mA from a 1.5 V supply). The proposed differential LNA occupies an area of 1.01 mm~2 including test pads.     

Two-port noise figure optimization of source-degenerated cascode CMOS LNAs

This paper presents a noise figure optimization technique for source-degenerated cascode CMOS LNAs with lossy gate inductors. The optimization technique, based on two-port theory, takes into account second order parasitic components. The effect of inductive source degeneration on LNA noise parameters is discussed. Measured noise figures agree well with the simulations confirming the accuracy of the noise model and allowing us to investigate the contributions of various components to the overall noise figure. A 0.18-μm CMOS LNA with an integrated inductor (Q = 7.5) achieves a noise figure of 1.16 dB and a return loss of 20 dB at 1.4 GHz, drawing 39 mA from a 1.8-V voltage supply, having gain (S ₂₁) of 14.5 dB, input P1dB of ?17.5 dBm, and input IP3 of ?13 dBm. LNAs with external inductors having quality factor of Q = 170 and Q = 40 achieve noise figures of 0.65 dB and 0.68 dB and a return loss of 20 dB at 1.4 GHz, drawing 37 mA from a 1.8-V voltage supply, having gain (S ₂₁) of 17 dB, input P1dB of ?22 dBm, and input IP3 of ?14 dBm. The large power consumption of the presented designs was intentionally selected in order to reduce the noise figure, an acceptable trade-off for LNA’s targeted for radio telescope applications, and to assess the impact of the large currents flowing through interconnect metals on the noise figure     

Inductor-less PVT robust gain switching balun LNA for multistandard applications

An inductor-less single to differential low-noise amplifier (LNA) is proposed for multistandard applications in the frequency band of 0.2–2 GHz. The proposed LNA incorporates noise cancellation and voltage shunt feedback configuration to achieve minimum noise characteristics and low power consumption. In addition to noise cancellation, trans-conductance of common-source stage is scaled to improve the noise performance. In this way, noise figure (NF) of LNA below 3 dB is achieved. An additional capacitor C_c is used to correct the gain and phase imbalance at the output. The gain switching has been enabled with a step size of 4 dB for high linearity and power efficiency. The bias point of all transistors is chosen such that the variation in g_m is not more than 10%. The proposed LNA is implemented in UMC 0.18-μm RF CMOS technology. The core area is 182 μm × 181 μm. Moreover, the LNA has better ratio of relevant performance to area. The proposed balun LNA is validated by rigorous Monte Carlo simulation. The 3σ deviation of gain and NF is less than 5%. Finally, the proposed LNA is robust to unavoidable PVT variations.     

Impact of Al composition on RF noise figure of AlGaAs/GaAsheterojunction bipolar transistors

The influence of Al content on the RF noise characteristics of Al _xGa_1-xAs/GaAs heterojunction bipolar transistors (HBT's) is presented. It is shown that the minimum noise figure (F_min) at 2 GHz is reduced by increasing the Al mole fraction (x). This observed improvement in noise figure is directly correlated to the differences in dc current gain. The lowest measured F_min(2 GHz) of HBT's with emitter dimensions 2×(3.5×30) μm², were 1.3, 1.61, and 2.1 dB for x=0.35, 0.30, and 0.25 devices, respectively at I_c=3 mA. The measured results were found to agree well with calculated values over a wide range of collector currents     

High microwave and ultra-low noise performance of fullyion-implanted GaAs MESFETs with Au/WSiN T-shaped gate

Fully ion-implanted n⁺ self-aligned GaAs MESFETs with high microwave and ultra-low-noise performance have been fabricated. T-shaped gate structures composed of Au/WSiN are employed to reduce gate resistance effectively. A very thin and high-quality channel with high carrier concentration can be formed by adopting the optimum annealing temperature for the channel, and the channel surface suffers almost no damage by using ECR plasma RIE for gate formation. GaAs MESFETs with a gate length as short as 0.35 μm demonstrated a maximum oscillation frequency of 76 GHz. At an operating frequency of 18 GHz, a minimum noise figure of 0.81 dB with an associated gain of 7.7 dB is obtained. A K_f factor of 1.4 estimated by Fukui's noise figure equation, which is comparable to those of AlGaAs/GaAs HEMTs with the same geometry, reveals that the quality of the channel is very high     

Ultralow-noise W-band pseudomorphic InGaAs HEMT's

Low-noise planar doped pseudomorphic (PM) InGaAs high-electron-mobility transistors (HEMTs) with a gate length of 0.1 μm for W-band operation are discussed. These devices feature a multiple-finger layout with air bridges interconnecting the sources to reduce gate resistance. The device exhibits a minimum noise figure of 2.5 dB with an associated gain of 4.7 dB at 92.5 GHz. This result demonstrates the feasibility of using PM InGaAs HEMTs for W-band low-noise receivers without the need for using lattice-matched InP HEMTs     

Microwave performance of 0.25-µm gate length high electron mobility transistors

The performance of 0.25-µm gate length high electron mobility transistors (HEMT's) is reported. Devices were fabricated on layers grown by MBE. One of the heterostructures had no undoped AlGaAS spacer layer (wafer A), whereas the other had a 40-Å spacer layer (wafer B). The maximum stable gain on both wafers was ∼ 12 dB at 18 GHz. The minimum noise figure measured was 0.60 dB at 8 GHz and 1.3 dB at 18 GHz. Wafer A yielded devices with a unity current gain cutoff frequency ftof 65 GHz whereas wafer B gave an ftof 70 GHz. These results can be attributed primarily to the high quality material, low parasitic resistance, and short gate length.