10Gb/s突发模式时钟数据恢复电路设计

突发模式的时钟数据恢复是10G EPON系统的关键技术之一。本文介绍了一种基于XNOR/XOR门的振荡器,分析了其工作原理与性能,以此为基础设计了半速率突发时钟恢复电路。设计采用SMIC 0.13?m CMOS工艺进行了流片验证,芯片面积为675?m ? 625?m。测试结果表明,该电路可以即时的实现10Gbit/s的突发数据恢复,恢复出的时钟数据符合IEEE 802.3av标准,锁定时间小于5bit。     

高速光突发模式接收机设计

介绍了一种高速光突发模式接收机。整形电路采用直流耦合跨阻抗前馈式结构。突发同步恢复电路采用一种新颖的固定相位调节振荡器。仿真表明：在传输速率为1．25Gb／s，误码率BER≤10^-9时，接收灵敏度为-25dBm（平均光功率）。最大可接收光功率-1dBm，动态范围可高达24dB，两分组信号保护时间为20ns。对速率为5Gb／s的NRZ突发数据可在10ps之内建立比特同步。     

采用相邻采样求和的突发模式相位插值型CDR

提出了一种具有良好抑制输入数据抖动性能的突发模式相位插值型时钟数据恢复电路。在传统相位插值型电路结构的基础上,在采样保持电路与相位插值电路之间加入一级求和电路,理论分析和仿真结果表明,恢复时钟相位变化受输入数据抖动的影响明显减小。电路基于1.1 V SMIC 40 nm 1P8M CMOS工艺搭建,其数据率为6.25 Gb/s,消耗功耗为6.7 mW,版图面积为0.35 mm²。     

高速光突发模式接收机设计

介绍了一种高速光突发模式接收机.其中整形电路采用直流耦合跨阻抗前馈式结构,突发同步恢复电路采用一种新颖的固定相位调节振荡器.仿真表明:在速率为1.25Gb/s、误码率BER≤10-9时,接收灵敏度为25dBm,动态范围可高达24 dB,并且可在10ps之内建立比特同步.     

CMOS 5 Gb/s串行接收器

设计了一个使用0.13μm CMOS工艺制造的低电压低功耗串行接收器。它的核心电路工作电压为1V,工作频率范围从2.5 GHz到5 GHz。接收器包括两个1:20的解串器、一个输入信号预放大器以及时钟恢复电路。在输入信号预放大器中设计了一个简单新颖的电路,利用前馈均衡来进一步消除信号的码间串扰,提高接收器的灵敏度。测试表明,接收器功耗45 mW。接收器输入信号眼图闭合0.5UI,信号差分峰-峰值150 mV条件下误码率小于10~(-12)。接收器还包含了时钟数据恢复电路,其中的相位插值器通过改进编码方式,使得输出信号的幅度能够保持恒定,并且相位具有良好的线性度。     

1.25～3.125 Gb/s连续数据速率CDR设计

设计了一款工作速率为1.25～3.125 Gb/s的连续可调时钟数据恢复(CDR)电路,可以满足多种通信标准的设计需求.CDR采用相位插值型双环路结构,使系统可以根据应用需求对抖动抑制和相位跟踪能力独立进行优化.针对低功耗和低噪声的需求,提出一种新型半速率采样判决电路,利用电流共享和节点电容充放电技术,数据速率为3.125 Gb/s时,仅需要消耗50 μA电流.芯片采用0.13 μm工艺流片验证,面积0.42 m㎡,功耗98 mw,测试结果表明,时钟数据恢复电路接收PRBS7序列时,误码率小于10-12.     

高速光突发模式外调制器驱动电路设计

阐述了高速突发模式外调制器电路的设计要点,着重讨论了消光比、啁啾对光发射机的影响,对匹配问题进行了详细讨论,设计了性能良好的前向匹配电路及电吸收调制器驱动电路,其工作速率为12 Gb/s,运用这些技术设计的光发射机消光比大于23.3 dB,啁啾小于13.4GHz.     

一种10Gb/s具有周期性相位校准双沿触发CDR和CTLE/DFE组合均衡功能的接收端

This paper presents the design of a 10 Gb/s low power wire-line receiver in the 65 nm CMOS process with 1 V supply voltage. The receiver occupies 300×500 μm2. With the novel half rate period calibration clock data recovery （CDR） circuit, the receiver consumes 52 mW power. The receiver can compensate a wide range of channel loss by combining the low power wideband programmable continuous time linear equalizer （CTLE） and decision feedback equalizer （DFE）.     

2.5Gb/s 0.18μm CMOS时钟数据恢复电路

采用TSMC公司标准的0.18μm CMOS工艺,设计并实现了一个全集成的2.5Gb/s时钟数据恢复电路.时钟恢复由一个锁相环实现.通过使用一个动态的鉴频鉴相器,优化了相位噪声性能.恢复出2.5GHz时钟信号的均方抖动为2.4ps,单边带相位噪声在10kHz频偏处为-111dBc/Hz.恢复出2.5Gb/s数据的均方抖动为3.3ps.芯片的功耗仅为120mW.     

2.5Gb/s 0.18μm CMOS时钟数据恢复电路

采用TSMC公司标准的0．18μm CMOS工艺，设计并实现了一个全集成的2．5Gb／s时钟数据恢复电路．时钟恢复由一个锁相环实现．通过使用一个动态的鉴频鉴相器，优化了相位噪声性能．恢复出2．5GHz时钟信号的均方抖动为2．4ps，单边带相位噪声在10kHz频偏处为-111dBc／Hz．恢复出2．5Gb／s数据的均方抖动为3．3ps．芯片的功耗仅为120mW．     

A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology

A 33.6–33.8 Gb/s burst-mode clock/data recovery circuit (BMCDR) is presented in this paper. To reduce the data jitter and generate the high-frequency output clock, the LC gated voltage-controlled oscillator is presented. To receive and transmit the broadband data, a wideband input matching circuit and a wideband data buffer are presented, respectively. The phase selector is proposed to overcome the false phase lock due to the full-rate operation. This proposed BMCDR has been fabricated in a 90 nm CMOS process. The measured peak-to-peak and rms jitters for the recovered data are 7.56 ps and 1.15 ps, respectively, for a 33.72 Gb/s, 2 $^{11} -$1 PRBS. The measured bit error rate is less than $10^{-8}$ for a 33.72 Gb/s, 2$^{7} -$1 PRBS. It consumes 73 mW without buffers from a 1.2 V supply.      

Gb/s级光前置放大器的基本电路形式

通过对由InGaAs-PIN或InGaAs-APD与GaAsFET或HEMT配合组成的光前置放大器分类比较,找出了适合Gb/s高速光纤通信前置放大器的电路形式。介绍了几种典型电路,讨论和分析了其设计、制作和测试结果。     

A 2.5 Gb/s Run-Length-Tolerant Burst-Mode CDR Based on a 1/8th-Rate Dual Pulse Ring Oscillator

A 2.5 Gb/s burst-mode clock and data recovery (CDR) circuit is presented that uses a 1/8th-rate ring oscillator with two pulses running simultaneously that are phase independent. One “tune” pulse sets the delay of the ring by phase locking it to a reference. The other “clock” pulse tracks the phase of the incoming data by a process of pulse removal and reinsertion. Because both pulses share the same ring, there is no frequency mismatch between the incoming data stream and the recovered clock in frequency synchronous systems, allowing for large data run lengths. A 1:8 data-demux clock is naturally generated by tapping the clock pulse along the ring. Phase acquisition is instantaneous from a single data edge. Run length tolerance is larger than 72 bits. The 0.6 mm$^{2}$ 0.13 $mu$m CMOS chip includes a CML-to-CMOS input buffer, PLL with on-chip loop filter, PRBS checker, 1:8 data demux, and eight output buffers. It has 2.7 ${rm UI}_{rm pp}$ measured jitter tolerance at 100 kHz and consumes 42 mW from a single 1.2 V supply.      

5Gb/s光接收机前端放大电路的设计

利用SMIC0.18μm CMOS工艺设计了适用于同步数字光纤传输系统SONET OC-96(5Gb/s)的光接收机前端放大电路.跨阻放大器(TIA)采用全差分结构,利用震荡反馈技术和可调节共源共栅(RGC)结构来增加其带宽.限幅放大器(LA)采用有源电感反馈和改进的Cherry-Hooper以获得高的增益带宽积.HSPICE仿真结果表明光接收机前端放大电路具有92dBΩ的中频增益,3.7GHz的-3dB带宽,对于输入电流峰峰值从4μA到50μA变化时,50Ω负载线上的输出眼图限幅在550mV,核心电路功耗为60mW.     

一种适用于内嵌时钟串行链路的5Gbps小面积CDR

本文提出了一种支持多标准的具有系数可调的均衡器和宽跟踪能力的时钟数据恢复电路。基于对系统参数和一阶 bang-bang 时钟数据恢复电路的环路特性分析,推导出电路设计参数。考虑到抖动性能,追踪能力以及芯片面积,文中采用了一阶数字滤波器和6-bit DAC以及高线性度的相位插值器实现了高相位调整精度和小面积的时钟恢复电路,同时该结构实现了±2200ppm的频偏跟踪能力,使得该结构适用于不同源的高速串行传输系统,尤其是内嵌时钟结构。该设计已经在55nm CMOS工艺上流片验证,测试结果显示符合误码率的要求以及抖动容忍规范。该测试芯片整体面积是0.19mm2,其中时钟恢复电路只占0.0486mm2 而且该电路工作在5Gbps,供电电压为1.2V时,只消耗30mW。     

2.5 Gb/s Optical Transponder技术与设计

网络容量增长的同时也促进了光纤通信技术的发展，使得宽带传输和接入方式处于越来越重要的地位，如何有效地解决光纤干线上和大部分基于电缆局域网的信号转换成为亟待解决的问题，光收发器(opticaltransponder)很好地解决了宽带传输和接入的这一“瓶颈”问题．2．5Gb／s是目前最流行的传输速率，其相应transponder用于SDH／SonetOC-48／STM-16的光／电接口．文章介绍了2．5Gb／soptical transponder的功能、结构等技术和相应的设计方案．     

2.5 Gb/s Optical Transponder技术与设计

网络容量增长的同时也促进了光纤通信技术的发展,使得宽带传输和接入方式处于越来越重要的地位,如何有效地解决光纤干线上和大部分基于电缆局域网的信号转换成为亟待解决的问题,光收发器(opticaltransponder)很好地解决了宽带传输和接入的这一“瓶颈”问题。2.5 Gb/s是目前最流行的传输速率,其相应transponder用于SDH/Sonet OC-48/STM-16的光/电接口。文章介绍了2.5 Gb/s optical transponder的功能、结构等技术和相应的设计方案。     

2.5 V 43–45 Gb/s CDR Circuit and 55 Gb/s PRBS Generator in SiGe Using a Low-Voltage Logic Family

An alternative design approach for implementing high-speed digital and mixed-signal circuits is proposed. It is based on a family of low-voltage logic gates with reduced transistor stacking compared to series-gated emitter-coupled logic. It includes a latch, an xor gate, and a MUX with mutually compatible interfaces. Topologies and characteristics of the individual gates are discussed. Closed-form propagation delay expressions are introduced and verified with simulations. The proposed design style was used to implement a 43–45 Gb/s CDR circuit with a 600MHz locking range and a 55 Gb/s PRBS generator with a$2^7!-!1$sequence length. The circuits were fabricated in a SiGe BiCMOS technology with$f _T = 120~hboxGHz$. Corresponding measurement results validate the proposed design style and establish it as a viable alternative to emitter-coupled logic in high-speed applications. Both circuits operate from a 2.5 V nominal power supply and consume 650 mW and 550 mW, respectively.     

40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS

High-speed front-end amplifiers and CDR circuits play critical roles in broadband data receivers as the former needs to perform amplification at high data rate and the latter has to retime the data with the extracted low-jitter clock. In this paper, the design and experimental results of 40 Gb/s transimpedance-AGC amplifier and CDR circuit are described. The transimpedance amplifier incorporates reversed triple-resonance networks (RTRNs) and negative feedback in a common-gate configuration. A mathematical model is derived to facilitate the design and analysis of the RTRN, showing that the bandwidth is extended by a larger factor compared to using the shunt-series peaking technique, especially in cases when the parasitic capacitance is dominated by the next stage. Operating at 40 Gb/s, the amplifier provides an overall gain of 2 kOmega and a differential output swing of 520 mV_pp with for input spanning from to . The measured integrated input-referred noise is 3.3muA_rms. The half-rate CDR circuit employs a direction-determined rotary-wave quadrature VCO to solve the bidirectional-rotation problem in conventional rotary-wave oscillators. This guarantees the phase sequence while negligibly affecting the phase noise. With 40 Gb/s 2³¹ - 1 PRBS input, the recovered clock jitter is and 0.7ps_rms. The retimed data exhibits 13.3 ps_pp jitter with BER . Fabricated in 90 nm digital CMOS technology, the overall amplifier consumes 75 mW and the CDR circuit consumes 48 mW excluding the output buffers, all from a 1.2 V supply.