Bistable switching in supercritical n+-n-n+GaAs transferred electron devices

Bistable switching in supercritically doped n⁺-n-n⁺GaAs transferred electron devices (TED's) is investigated experimentally and interpreted in computer simulations, for which details of the computer program are given. Three switching modes all leading to stable anode domains are discussed, namely: 1) cathode-triggered traveling domain; 2) cathode-triggered accumulation layer; 3) anode-triggered domain. Relative current drops up to 40 percent, and switching times down to 60 ps are obtained in low-duty-cycle pulsed experiments with threshold currents around 400 mA. Optimum device parameters are shown to be as follows: 1) doping in the 3-4 × 10¹⁵cm^-3range; 2) length around 6 µm; 3) doping gradients below 20 percent; 4) high-quality interfaces.     

Voltage distributions in X-band n+-n-n+Gunn devices using a SEM

The SEM has been used as a voltage measuring probe to obtain voltage distributions in X-band n⁺-n-n⁺mesa structure Gunn devices. Dynamic distributions are obtained by operating the instrument in the stroboscopic mode. The results show accumulation layers in the oscillating device and the amplifier mode has a high field anode region.     

Corner currents in p+-n-n+diodes with n+isolation diffusions

The magnitude of corner currents in rectangular diffused p⁺-n-n⁺diodes with deep n⁺isolation diffusions is discussed. Curves are given to illustrate the importance of this current in diodes and IIL structures.     

Voltage distribution in n+-n-n+and metal-cathode n-n+GaAs X-band oscillators using a SEM

Time-averaged and dynamic results have been obtained in n⁺-n-n⁺and metal cathode n-n⁺GaAsX-band devices, using a new voltage measurement scheme in the SEM. The n⁺-n-n⁺devices show accumulation layer propagation, and the metal-cathode devices show a trapped dipole domain behavior.     

Self-aligned In0.53Ga0.47As/semi-insulating/n+InP junction field-effect transistors

Depletion-mode junction field-effect transistors (JFET's) with InGaAs p-n junctions grown on compensated Fe:InP or highly resistive In0.52Al0.48As isolation layers grown on n⁺-InP substrates have been fabricated using a combination of molecular-beam epitaxy and metalorganic chemical vapor deposition growth techniques. Using a self-aligned gate technology with a 1-µm gate length, devices with high transconductance (80 mS/mm), low leakage current (<100 nA), and a gate-to-source capacitance of 0.4 pF have been fabricated. This is apparently the first report where InP-based alloy FET's have been fabricated on an isolated n⁺-substrate. This structure has application to monolithically integrated photoreceivers.     

Theoretical investigation of n+-n-n+Ga0.47In0.53As TEO's up to the millimeter-wave range

Theoretical investigations of n⁺-n-n⁺Ga0.47In0.53As TED's have been performed up to the millimeter-wave range. Accumulation layer transit time mode of oscillation has been pointed out up to about 50 GHz. n⁺-n-n⁺GaInAs devices exhibit higher output power and efficiency in the 30-GHz region than GaAs and InP similar devices, but their frequency behavior is poor because of their higher energy relaxation time.     

Forward current—Voltage and switching characteristics of p+-n-n+(epitaxial) diodes

The forward-biased current-voltage and forward-to-reverse biased switching characteristics of p⁺-n-n⁺epitaxial diodes are investigated. The manner in which the n-n⁺junction affects the flow of injected minority carriers in the epitaxial region is characterized by a leakage parameter a. Experimentally, for diodes with epitaxial film widths much less than a diffusion length, a "box" profile accurately describes the injected minority carriers in the n region. The current is found to increase with increased epitaxial width at a fixed bias. A general switching expression for epitaxial diodes is presented and the validity of the expression is shown experimentally. The experimental values of a, determined independently from the current-voltage and switching characteristics, are in good agreement and show that the leakage of the high-low junction is dominated by the recombination of minority carriers in the n-n⁺space-charge region.     

Field-enhanced tunneling and barrier lowering in Al—n+GaAs—nGaAs Schottky contacts grown by MBE

A thin, highly Si-doped (n-type) interfacial layer is used for controlled barrier lowering in n-type GaAs. The thickness and the doping density of the interfacial n+ layer in the range of 50-100 Å, are extracted from the measured electrical characteristics of Schottky contacts. A model for field-enhanced tunneling current in metal--nGaAs Schottky structures is presented and the experimental results for Al-n+ GaAs devices fabricated using molecular beam epitaxy (MBE) show good agreement.     

Optimum design of n+-n-double-diffused drain MOSFET to reduce hot-carrier emission

Channel electric field reduction using an n⁺-n^-double-diffused drain MOS transistor to suppress hot-carrier emission is investigated. The double-diffused structure consists of a deep low-concentration P region and a shallow high-concentration As region. The channel electric field strongly depends on such process and device parameters as the length of the n^-diffusion region, drain junction depth, gate oxide thickness, gate length, applied voltage, and P implant energy. The optimum condition for a double-diffused structure is determined based on those parameter dependences of the channel electric field. The results of the optimum drain impurity profile to give the minimum channel electric field are obtained when the maximum lateral electric field is located at the boundary between the P region and the As region. The hot-carrier immunity of MOSFET and test circuits are improved by two orders of magnitude and one order of magnitude, respectively, under the optimum conditions.     

Spectral response of n+-n-p and n+-p photodiodes

Results of calculations for the quantum efficiency of three different types of n⁺-p, n⁺-n-p, and OCI-HLE diodes are reported. Exact numerical modeling of current density equations, modified to include bandgap reduction and Auger recombination is used to compute the quantum efficiency of these diodes. It is found that an optimized n⁺-p structure can result in over all spectral response comparable to the n⁺-n-p structure, although it is not as good as that of the OCI-HLE type of diodes. Further, these calculations show that one can achieve low dark current in these diodes, but at the expense of lower quantum efficiency particularly for wavelengths less than 0.4 µm.     

Carrier distribution and low-field resistance in short n+-n--n+and n+-p--n+structures

In the present paper, we calculate the potential, field, and carrier distributions in short n⁺-n^--n⁺and n⁺-p^--n⁺devices and estimate the low-field resistance. The results of the calculations present a set of universal curves which may be used to find the minimum carrier density in the sample, the barrier height, the electric field at the boundary, etc. Our calculations show that electron injection becomes very important when the doping level is smaller than 1.5 × 10¹⁴(cm^-3). (T/300 K)/ L²(µm) for GaAs diodes, whereLis the sample length. The low-field resistance of the sample is limited by the thermionic emission of the sample and by the diffusion and drift in the sample. The thermionic emission dominates at low temperatures, in short samples, and the diffusion-drift dominates in longer samples at higher temperatures. The experimental values of low-field resistance for GaAs 0.4-µm n⁺-n^--n⁺devices at 77 and 300 K are in good agreement with the predicted values. The agreement is not so good for 0.25-µm devices and for n⁺-p^--n⁺devices. In the latter case, the disagreement may be due to uncertainty in the doping level because the low-field resistance of the n⁺-p^--n⁺structure is shown to be very sensitive to the doping level of the p-region.     

Corner currents in rectangular diffused p+-n-n+diodes

The low-level injection dc characteristics of rectangular p⁺-n-n⁺diodes are discussed, and the vertical, lateral, and corner current components are analyzed and measured. It is shown that the corner current can be a significant fraction of the total current and a simple analytic expression is given.     

Ultra-thin silicon-dioxide breakdown characteristics of MOS devices with n+and p+polysilicon gates

In this work we investigate the effect of the gate material on the breakdown characteristics of ultra-thin silicon dioxide films at low voltages (<6 V). When MOS capacitors are stressed with a positive gate voltage, the charge to breakdown and time to breakdown at a fixed oxide-voltage drop are significantly smaller in p+ polysilicon-gate capacitors than in n+ polysilicon-gate capacitors. The results are interpreted in terms of a simple model of hole tunneling resulting from hot-hole generation in the anode by hot electrons entering from the silicon dioxide. Extrapolation of high-voltage-breakdown lifetime measurements for relatively thick-oxide devices to low voltages may be complicated by this mechanism.     

Characteristics of an all-implanted p+-n-n+solar cell

This work presents the main electrooptical parameters of a p⁺-n-n⁺single-crystalline silicon solar cell, whose front p⁺-n junction and the backside n-n⁺contact were fabricated through masked ion implantation of boron (¹¹B+) and phosphorus (³¹p+), respectively. The distinctive feature of the cells consists of the use of the front junction silicon dioxide mask as an AR layer in the finished devices.     

Evaluation of the profile constants of p+-n-n+hyperabrupt junctions

A method for evaluating the profile constants of a p⁺-n-n⁺hyperabrupt junction is given. The method is useful in the design and characterization of hyperabrupt tuning varactors.     

Forward transient characteristics of gold-doped silicon p+-n-n+diodes

The transient response of high-resistivity long-base low-lifetime p⁺-n-n⁺silicon diodes was examined experimentally. The diodes were doped with gold in order to reduce the minority carrier lifetime. Voltage oscillations were observed at different current levels. A large inductive effect was shown to exist when the diode was forward biased in a negative resistance region of the dc voltage-current characteristics.     

Diffusion and recombination 1/f noise in long n+-p Hg1—xCdxTe diodes

1/f noise in long n⁺-p Hg1-xCdxTe diodes with x = 0.30 is studied at 193 K. The 1/f noise is considered to be generated by diffusion and recombination fluctuations. A distinction is made between cases a (all minority carriers contribute to the 1/f noise) and b (only the excess minority carriers contribute to the 1/f noise). Measurements on long nonplanar diodes show that case a is valid, indicating that all minority carriers contribute equally to the 1/f noise; this should be valid for any long-junction device in which the current flow is by diffusion and recombination of minority carriers. The lifetime τnof the electrons in the p-region is measured by the input impedance method, and the Hooge parameter αHof the device is evaluated. τnis of the order of 10^-6to 10^-7s and depends somewhat on bias. Near zero bias αHis of the order of 5 × 10^-3in close agreement with Handel's coherent state 1/f noise theory, which yields αH= 4.6 × 10^-3. Due to the nonplanar geometry of the studied diodes, the measurement of τnis not always equally reliable. Larger values of τnare accompanied by larger values of αH, because the noise measurements give αH/τn, and its value practically independent of bias. We also evaluated τnby putting αH= 4.6 × 10^-3; the τnvalues are then much closer and agree rather well with Honeywell lifetime tables. Preliminary measurements at 113 K also indicate coherent state 1/f noise, whereas data at 273 K give αH= 5 × 10⁵, in agreement with the Umklapp 1/f noise theory.     

Device design for the submicrometer p-channel FET with n+polysilicon gate

CMOS has become one of the most important technologies for VLSI applications. If the conventional n⁺polysilicon gate approach is to be maintained for VLSI CMOS, the p-channel transistor will cause problems in scaling down to submicrometers due to the counter-doping that is necessary to adjust the threshold voltage to a reasonable value. The depth of the p⁺source-drain junctions will also cause short-channel effects. This paper presents in-depth analysis of the submicrometer p-channel transistor structure. The effects of the counter-doping junction depth and the source-drain junction depth on the device subthreshold characteristics are discussed. Criteria for the submicrometer p-channel transistor structure with good subthreshold characteristics are presented. A new technique for minimizing the counter-doping junction depth is also presented. Submicrometer p-channel transistors with n⁺polysilicon gate were fabricated using this new technique as well as techniques for forming very shallow p⁺-junctions. Devices with submicrometer channel lengths showed very good subthreshold characteristics, as predicted by simulations.     

A high-speed frequency divider using n+-Ge Gate AlGaAs/GaAs MISFET's

A high-speed divide-by-four static frequency divider is fabricated using n+ -Ge gate AlGaAs/GaAs heterostructure MISFET's. The divider circuit consists of two master-slave T-type flip-flops (T-FF's) and an output buffer based on source-coupled FET logic (SCFL). A maximum toggle frequency of 11.3 GHz with a power dissipation of 219 mW per T-F/F is obtained at 300 K using 1.0-µm gate FET's.     

Noise in short n+-n--n+GaAs diodes

Noise measurements in a short, near-ballistic, n⁺-n^--n⁺GaAs diode are reported. The device had a linear characteristic below 100 mA. It showed1/fnoise at low frequencies and a white noise close to the thermal noise of the device conductancegat high frequencies. The1/fnoise is most likely mobility fluctuation noise; we evaluated Hooge's parameter α and found a value of 1.95 × 10^-6at room temperature and 0.959 × 10^-6at liquid nitrogen temperature. We also observed a1/fnoise spectrum turning over into1/f^0.5spectrum at 77 K.