Effect of Ag doping on the electrical properties of thermally deposited CdS–La2O3 TFTs

This paper describes a new approach for repairing memories. Repair is implemented by deletion of either rows and/or columns on which faulty cells lie. These devices are commonly referred to as redundant memories, because redundant columns and rows are added. A new repair technique and an algorithm are proposed. The algorithm is based on a fault-counting technique and on a reduced-covering approach. The innovative feature is that reduced covering permits an heuristic, but efficient, criterion to be included in the selection of the rows and/or columns to be deleted. This retains independence of the repair process on the distribution of faulty cells in memory, while allowing a good repairability/ unrepairability detection. The main benefits that result by using the proposed repair algorithm are a reduction in execution time to determine the repair-solution for the device under test and its suitability for implementation in a defect analysis system. Illustrative examples and theoretical results are provided to substantiate the validity of the proposed repair technique     

Built-in redundancy analysis for memory yield improvement

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. The yield improvement and testing issues have become the most critical challenges for memory manufacturing. Conventionally, redundancies are applied so that the faulty cells can be repairable. Redundancy analysis using external memory testers is becoming inefficient as the chip density continues to grow, especially for the system chip with large embedded memories. This paper presents three redundancy analysis algorithms which can be implemented on-chip. Among them, two are based on the local-bitmap idea: the local repair-most approach is efficient for a general spare architecture, and the local optimization approach has the best repair rate. The essential spare pivoting technique is proposed to reduce the control complexity. Furthermore, a simulator has been developed for evaluating the repair efficiency of different algorithms. It is also used for determining certain important parameters in redundancy design. The redundancy analysis circuit can easily be integrated with the built-in self-test circuit.     

Identify unrepairability to speed-up spare allocation for repairing memories

In this paper, we discuss some strategies for identifying unrepairable memories, and from that to introduce a novel theorem that can make more precise identification. A new algorithm for searching repair solutions is also proposed, which characterizes the rows, and columns of defective memory cells with revised effective coefficients. We have simulated it on many generated example maps, and compared it with the previous algorithms to verify its efficiency. It's combined with those arranged strategies of judging unrepairability to generate a complete flow. The complete algorithm has also been run on many examples with various memory sizes, defect numbers, and distribution types. The simulation results further show that identifying unrepairability in advance can help the reconfiguration procedure run much faster than searching solutions directly.     

A Fast Built-in Redundancy Analysis for Memories With Optimal Repair Rate Using a Line-Based Search Tree

With the growth of memory capacity and density, test cost and yield improvement are becoming more important. In the case of embedded memories for systems-on-a-chip (SOC), built-in redundancy analysis (BIRA) is widely used as a solution to solve quality and yield issues by replacing faulty cells with extra good cells. However, previous BIRA approaches focused mainly on embedded memories rather than commodity memories. Many BIRA approaches require extra hardware overhead to achieve the optimal repair rate, which means that 100% of solution detection is guaranteed for intrinsically repairable dies, or they suffer a loss of repair rate to minimize the hardware overhead. In order to achieve both low area overhead and optimal repair rate, a novel BIRA approach is proposed and it builds a line-based searching tree. The proposed BIRA minimizes the storage capacity requirements to store faulty address information by dropping all unnecessary faulty addresses for inherently repairable die. The proposed BIRA analyzes redundancies quickly and efficiently with optimal repair rate by using a selected fail count comparison algorithm. Experimental results show that the proposed BIRA achieves optimal repair rate, fast analysis speed, and nearly optimal repair solutions with a relatively small area overhead.      

A Novel Built-In Self-Repair Approach for Embedded RAMs

In this paper, a novel built-in self-repair approach, block-level reconfiguration architecture, is proposed. Our approach is based on the concept of divided word line (DWL) for high-capacity memories, including SRAMs and DRAMs. This concept is widely used in low-power memory designs. However, the characteristics of divided word line memories have not been used for fault-tolerant applications. Therefore, we propose the block_repair fault-tolerant architecture based on the structure of DWL for high-capacity memories. The redundant rows of a memory array are divided into blocks and reconfiguration is performed at the block level instead of the traditional row level. Our fault-tolerant architecture can improve the yield for memory fabrication significantly. Moreover, the characteristics of low power and fast access time of DWL memories are also preserved. The reconfiguration mechanism of our block_repair architecture requires negligible hardware overhead. According to experimental results, the hardware overheads are less than 0.73% and 0.48% for 256-Kbit SRAMs and 8-Mbit DRAMs, respectively. The repair rate of our approach with previous memory repair algorithms is compared. It is found that block_repair approach improves repair rate significantly. The yield improvement over traditional row-based approaches is also analyzed. Simulated results show that the present approach can significantly improve fabrication yield.     

A new accurate yield prediction method for system-LSI embedded memories

The authors propose a new accurate yield prediction method for system-LSI embedded memories to improve the productivity of chips. Their new method is based on the failure-related yield prediction method in which failure bits in memory are tested to see whether they are repairable or not by using built-in redundancies. The important concept of the new method is called "repairable matrix' (RM). In RM, rm/sub ij/=1 means that i row redundancy sets and j column redundancy sets are needed for repair, where rm/sub ij/ is an element of the matrix. Here, RM can indicate all the candidate combinations of the number of row and column redundancy sets for repair. The new yield prediction method using RM solves two problems, "asymmetric repair' and "link set.' These have a significant effect on accurate yield prediction but have not yet been approached by conventional analytical methods. The calculation of yield by the new method is demonstrated in two kinds of advanced memory devices that have different design rules, failure situations, and redundancy designs. The calculated results are consistent with the actual yield. On average, the difference in accuracy between the new method and conventional analytical methods is about 5%.     

量子纠缠联想记忆

提出一种基于量子纠缠的联想记忆神经网络(QuEAM).对比传统的联想记忆网络,QuEAM的存储容量得到了指数级的增大.学习算法是根据纠缠量度的性质,采用Grover量子迭代算法的基本原理局域放大量子位(qubit)的概率振幅,相当于传统计算机的按位操作,讨论了这个学习算法下的量子基本原理.最后给出具体的例子说明了算法的有效性.     

ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips

Complex system-on-a-chip (SOC) designs usually consist of many memory cores. Efficient yield-enhancement techniques thus are required for the memory cores in SOCs. This paper presents an infrastructure intelligent property (IIP) for testing, diagnosing, and repairing multiple memory cores in SOCs. The proposed IIP can perform parallel testing for multiple memories, and serial diagnosis or repair for one memory each time. In the repair mode, the proposed IIP can execute various redundancy analysis algorithms. Therefore, the user can select a better redundancy analysis algorithm for each memory core being tested according to its redundancy structure. Simulation results show that the proposed IIP needs less test time and redundancy analysis time than the processor-based built-in self-repair scheme. We also have realized the proposed IIP for four types of memories - two 8 K 64 bit SRAMs, one 4 K x 16 bit SRAM, and one 2 K x 32 bit SRAM - based on TSMC 0.18-mum standard cell technology. Simulation results show that the area overhead of the IIP is only about 4.6%.     

Tutorial on semiconductor memory testing

This article is a tutorial introduction to the field of semiconductor memory testing. It begins by describing the structure and operation of the main types of semiconductor memory. The various ways in which manufacturing defects and failure mechanisms can cause erroneous memory behavior are then reviewed. Next we describe the different contexts in which memories are tested together with the corresponding different types of tests. The closely related processes of fault modeling and test development are then summarized. Various design for testability strategies for memories are also presented. Finally, current trends in the design and testing of memory are outlined.This work was supported by the Natural Sciences and Engineering Research Council of Canada under grant OGP 0105567.     

Reliability Analysis of Phased-Mission System With Independent Component Repairs

This paper proposes a hierarchical modeling approach for the reliability analysis of phased-mission systems with repairable components. The components at the lower level are described by continuous time Markov chains which allow complex component failure/repair behaviors to be modeled. At the upper level, there is a combinatorial model whose structure function is represented by a binary decision diagram (BDD). Two BDD ordering strategies, and consequently two evaluation algorithms, are proposed to compute the phased-mission system (PMS) reliability based on Markov models for components, and a BDD representation of system structure function. The performance of the two evaluation algorithms is compared. One algorithm generates a smaller BDD, while the other has shorter execution time. Several examples, and experiments are presented in the paper to illustrate the application, and the advantages of our approach.     

Efficient built-in redundancy analysis for embedded memories with 2-D redundancy

A novel redundant mechanism is proposed for embedded memories in this paper. Redundant rows and columns are added into the memory array as in the conventional approaches. However, the redundant rows and columns are divided into row blocks and column blocks, respectively. The reconfiguration is performed at the row (column) block level instead of the conventional row (column) level. Based on the proposed redundant mechanism, we first show that the complexity of the redundancy allocation problem is NP-complete. Thereafter, an extended local repair-most (ELRM) algorithm suitable for built-in implementation is proposed. The complexity of the ELRM algorithm is O(N), where N denotes the number of memory cells. According to the simulation results, the hardware overhead for implementing this algorithm is below 0.17% for a 1024/spl times/2048-b SRAM. Due to the efficient usage of the redundant elements, the manufacturing yield, repair rate, and reliability can be improved significantly.     

Highly parallel collision detection processor for intelligentrobots

A collision detection VLSI processor is proposed in order to achieve ultrahigh-performance processing with an ideal parallel processing scheme. A large number of coordinate transformations and memory accesses to the obstacle memory are fully utilized in the processing algorithm, so that direct collision detection can be executed with a VLSI-oriented regular data flow. The structure of each processing element (PE) is very simple because a PE mainly consists of a COordinate Rotational DIgital Computer (CORDIC) arithmetic unit for the coordinate transformation and memories for the storage of manipulator and obstacle information. When 100 PEs are used for parallel processing, the performance is about 10,000 times faster than that of conventional approaches using a single general-purpose microprocessor     

Receiver memory management method for HARQ in LTE‐based satellite communication system

For the successful deployment of the long term evolution (LTE)‐based mobile satellite service, the price of a user terminal is one of the major factors. A user terminal for the LTE‐based satellite communication needs to be implemented with a similar hardware size that is used for a terrestrial LTE user terminal. However, for quality of service provision, the satellite user terminal needs a larger size of memories than the terrestrial terminal does. This is very evident by considering that the N‐channel stop and wait hybrid automatic repeat request requires proportionally increasing memory size by the propagation delay, resulting in unmanageable amount of memories in the satellite system. To resolve this problem, we propose an efficient memory management method at the user terminal when the size of memory is insufficient. The simulation results in this paper reveal that the proposed method can increase the throughput about 20.7% when a user terminal is operated under very low throughput condition with an insufficient memory size, compared with the case without memory management scheme. In addition, we show that the additional throughput gain can be obtained by the packet scheduling using the information of receiver memory status. Copyright © 2015 John Wiley & Sons, Ltd.     

Defect Analysis and Defect Tolerant Design of Multi-port SRAMs

Multi-port SRAMs are often implemented using static random access memory (SRAM) due to its fast operation and the ability to support multiple read and write operations simultaneously, thus increasing data throughput in embedded systems and meeting the expected demands of parallel or pipelined microprocessors. With the continuous scaling of transistor feature size, designing low power robust memories and investigating their failure characteristics become critical. In this paper, we study the defects occurring in the multi-port SRAM cells. The memory is modeled at the transistor level and analyzed for electrical defects by applying a set of test patterns. Not only have existing models been taken into account in our simulation but also a new fault model, namely, simultaneous deceptive destructive read fault for the multi-port memory is introduced. In addition, we extend our study to the defect tolerant design of memories by proposing a differential current-mode sense amplifier for 3-port SRAM based register file. We examine the fault models of resistive defects within the SRAM cell and its failure boundary. A read disturb fault for multi-port memories is tested on the faulty cell by simultaneous read operations with different numbers of ports. Experimental results show that the proposed current-mode sensing scheme has improvements for memory fault-tolerance of resistive defects at 4.6× for dual-port read and 5.8× for 3-port read compared to voltage-mode sensing with 0.18 μm manufacturing process technology.     

An on-line BIST RAM architecture with self-repair capabilities

The emerging field of self-repair computing is expected to have a major impact on deployable systems for space missions and defense applications, where high reliability, availability, and serviceability are needed. In this context, RAM (random access memories) are among the most critical components. This paper proposes a built-in self-repair (BISR) approach for RAM cores. The proposed design, introducing minimal and technology-dependent overheads, can detect and repair a wide range of memory faults including: stuck-at, coupling, and address faults. The test and repair capabilities are used on-line, and are completely transparent to the external user, who can use the memory without any change in the memory-access protocol. Using a fault-injection environment that can emulate the occurrence of faults inside the module, the effectiveness of the proposed architecture in terms of both fault detection and repairing capability was verified. Memories of various sizes have been considered to evaluate the area-overhead introduced by this proposed architecture     

嵌入式存储器的内建自修复设计

目前，关于嵌入式存储器的内建自测试（MBIST）技术已经日趋成熟。基于这种背景．研究了一种高效的内建自修复（MBISR）方法，试验表明它具有低面积开销和高修复率等优点，保证了嵌入式存储器不仅可测．而且可修复。极大地提高了芯片的成品率。     

A 65 nm 1 Gb 2b/cell NOR Flash With 2.25 MB/s Program Throughput and 400 MB/s DDR Interface

This paper describes a 1.8 V, 1 Gb 2 b/cell NOR flash memory, based on time-domain voltage-ramp reading concept and designed in a 65 nm technology. Program method, architecture and algorithm to reach 2.25 MB/s programming throughput are also presented, as well as the read concept, allowing 70 ns random access time and a 400 MB/s sustained read throughput via a DDR interface.     

物理层网络编码中连续相位调制信号的非相干多符号检测

基于连续相位调制(CPM)的物理层网络编码(PNC)由于其高效的吞吐率和频谱利用率特性引起了越来越多的关注。现有关于CPM-PNC检测的研究大多建立在到达中继端的两节点信号载波相位完全同步或相位差已知的基础上。实际应用中,这一载波相位差不可避免,也很难准确估计。针对这一问题,该文提出一种中继端存在未知载波相位差条件下的CPM-PNC非相干多符号检测算法。该算法根据最大似然检测原理,通过观察多个码元来实现中间码元的检测,充分利用了CPM信号的相位记忆特性。仿真结果表明,该文所提出的CPM-PNC非相干多符号检测算法性能优越。而且随着观察窗口长度的增大,其性能显著提高并逐渐趋近最优相干检测性能。在误码率(BER)为10-4 时,相比于非相干单符号检测,观察窗口长度为5个码元时的CPM-PNC非相干多符号检测有6.7 dB的性能增益。     

Synthesis of custom interleaved memory systems

This paper presents a novel approach to the synthesis of interleaved memory systems that is especially suited for application-specific processors. Our synthesis system generates the optimized interleaved memories for a specific algorithm and finds the best mapping of arrays in that algorithm onto the memory system to achieve high performance. The design space is four-dimensional (4-D) and comprises the number of memory banks, the type of memory components, the storage scheme, and the range of clock period in the system. Optimal designs are found among the Pareto points (a set of nondominated points in the design space) computed for our memory model under the performance and cost criteria set by the designer. The memory model includes all the components of an interleaved memory system and covers a lookup table-based address generation with data alignment. The synthesis is based on a general periodic storage scheme, which enables efficient handling of irregular and overlapped access patterns. The synthesis process is the exhaustive search of the heavily pruned design space, and the pruning is based on mathematically proven properties of periodic storage schemes. This paper presents the theorems, the synthesis algorithm, and the methods of effective word and bank address generation. Examples are given to illustrate the effectiveness of our method     

Yield enhancement techniques for 3-dimensional random access memories

As the advances of process technology keep growing, three-dimensional (3D) integration with through silicon vias is a new alternative solution to extend Moore’s law especially for random access memories (RAMs). In general, the reliability and fabrication yield of the traditional 2D memories can be improved by the incorporation of some form of redundancy. However, for 3D integration, the scenarios for the repair process are totally different. The redundancy exclusively added in a memory tier can also be reused to repair defects in the other memory tier after the bonding process. That is, the concept of inter-tier redundancy can be exploited to further increase the yield of 3D memories. Die-to-die and die-to-wafer bonding can be adopted. In this paper, we propose an efficient die-stacking flow and the corresponding built-in self-repair architectures for yield enhancement of 3D memories. The matching problem for die stacking can be converted into a bipartite graph maximal matching problem and the traditional algorithm can be used to solve this problem. Experimental results show that the proposed stacking flow, algorithm, and the corresponding BISR (built-in self-repair) architecture can improve fabrication yield significantly.