Impact of high-/spl kappa/ dielectric HfO/sub 2/ on the mobility and device performance of sub-100-nm nMOSFETs

Scaling of Si MOSFETs beyond the 90-nm technology node requires performance boosters in order to satisfy the International Technology Roadmap for Semiconductors requirements for drive current in high-performance transistors. Amongst the preferred near term solutions are transport enhanced FETs utilizing strained Si (SSi) channels. Additionally, high-/spl kappa/ dielectrics are expected to replace SiO/sub 2/ around or after the 45-nm node to reduce the gate leakage current problem, facilitating further scaling. However, aside from the many technological issues such as trapped charge and partial crystallization of the dielectric, both of which are major issues limiting the reliability and device performance of devices employing high-/spl kappa/ gate stacks, a fundamental drawback of MOSFETs with high-/spl kappa/ dielectrics is the mobility degradation due to strong soft optical phonon scattering. In this work we study the impact of soft optical phonon scattering on the mobility and device performance of conventional and strained Si n-MOSFETs with high-/spl kappa/ dielectrics using a self-consistent Poisson Ensemble Monte Carlo device simulator, with effective gate lengths of 67 and 25-nm. Additionally we have also briefly investigated the effect (the percentage change) that a trapped charge within the gate oxide will have on the drive current for both a SiO/sub 2/ oxide and an equivalent oxide thickness of high-/spl kappa/ dielectric.     

Validity of constant voltage stress based reliability assessment of high-/spl kappa/ devices

Charge trapping in high-/spl kappa/ gate dielectrics affects the result of electrical characterization significantly. DC mobility degradation and device threshold voltage instability and C-V and I-V hysteresis are a few examples. The charging effects in high-/spl kappa/ gate dielectric also affect the validity of conventional reliability test methodologies developed for SiO/sub 2/ devices. In this paper, we review high-/spl kappa/ materials specific phenomena that can affect the validity of constant-voltage-stress-based reliability test methods to address the direction of future reliability study on high-/spl kappa/ devices.     

Special reliability features for Hf-based high-/spl kappa/ gate dielectrics

Several special reliability features for Hf-based high-/spl kappa/ gate dielectrics are highlighted, including: 1) trapping-induced threshold voltage (V/sub th/) shift is much more of a concern than TDDB in determining the operating lifetime; 2) n-channel MOSFETs (nMOSFETs) are more vulnerable than p-channel MOSFETs (pMOSFETs); and 3) MOSFETs with polySi gates are more vulnerable than those with metal gates. These will be discussed in the context of existing electron/hole traps and trap generation by high-field stress. A novel technique to probe traps in ultrathin gate dielectrics, inelastic electron tunneling spectroscopy (IETS), will be shown to be capable of revealing the energies and locations of traps in high-/spl kappa/ gate dielectrics.     

Electron trap generation in high-/spl kappa/ gate stacks by constant voltage stress

Positive bias constant voltage stress combined with charge pumping (CP) measurements were applied to study trap generation phenomena in SiO/sub 2//HfO/sub 2//TiN stacks. Using gate stacks with varying thicknesses of the interfacial SiO/sub 2/ layer (IL) or high-/spl kappa/ layer and analysis for frequency-dependent CP data developed to address trap depth profiling, the authors have determined that the defect generation in the stress voltage range of practical importance occurs primarily within the IL on as-grown "precursor" defects most likely caused by the overlaying HfO/sub 2/ layer. The generated traps can be passivated by a forming gas or nitrogen (N/sub 2/) anneal, whereas a postanneal stress reactivates these defects. The results obtained identify the IL as one of the major targets for reliability improvement of high-/spl kappa/ stacks.     

Threshold voltage instabilities in high-/spl kappa/ gate dielectric stacks

Over recent years, there has been increasing research and development efforts to replace SiO/sub 2/ with high dielectric constant (high-/spl kappa/) materials such as HfO/sub 2/, HfSiO, and Al/sub 2/O/sub 3/. An important transistor reliability issue is the threshold voltage stability under prolonged stressing. In these materials, threshold voltage is observed to shift with stressing time and conditions, thereby giving rise to threshold voltage instabilities. In this paper, we review various causes of threshold voltage instability: charge trapping under positive bias stressing, positive charge creation under negative bias stressing (NBTI), hot-carrier stressing, de-trapping and transient charge trapping effects in high-/spl kappa/ gate dielectric stacks. Experimental and modeling studies for these threshold voltage instabilities are reviewed.     

SEU reliability analysis of advanced deep-submicron transistors

A systematic evaluation of the single-event-upset (SEU) reliability of the advanced technologies-high-/spl kappa/ gate dielectric, elevated source-drain (E-SD), and lateral asymmetric channel (LAC) MOSFETs is presented for the first time in this work. Our simulations results gives a clear view of how the short channel effects in a device governs its SEU reliability and how this reasoning evolves at the circuit level. It is shown that devices with worsened short-channel effects (high-/spl kappa/ gate dielectric transistors) have a significantly reduced SEU-reliability in contrast to the devices with controlled short-channel effects (LAC and E-SD) or even a conventional device.     

Hot carrier degradation of HfSiON gate dielectrics with TiN electrode

Hot carrier reliability of the HfSiON dielectric with the TiN metal gate electrode has been studied in the nMOS and pMOS short channel transistors. Hot carrier induced degradation of the high-/spl kappa/ gate stack devices are severe than the one in the SiO/sub 2//poly devices. It is determined that total threshold voltage shift during a hot carrier stress is a sum of contributions from both hot carrier and cold carrier effects. The hot carrier contribution induces permanent damage while cold carrier contribution is shown to be reversible. The contribution from the cold carrier can be evaluated by applying a de-trapping (opposite polarity) bias after the stress.     

Magnetic resonance studies of trapping centers in high-/spl kappa/ dielectric films on silicon

The electrical properties of high dielectric constant materials being considered for replacements of SiO/sub 2/ in metal-oxide semiconductor (MOS) field effect transistors are dominated by point defects. These point defects play important roles in determining the response of these films in almost any imaginable reliability problem. A fundamental understanding of these defects may help to alleviate the problems which they can cause. The best known methods for determining the structure of electrically active defects in MOS materials and devices are conventional electron spin resonance (ESR) and electrically detected magnetic resonance (EDMR). In this paper, we review the limited ESR and EDMR work performed to date on high-/spl kappa/ materials. A discussion of magnetic resonance techniques as well as a brief overview of the extensively studied Si/SiO/sub 2/ system is also included.     

Effect of the Interfacial $hbox{SiO}_{2}$ Layer in High-$k$ $ hbox{HfO}_{2}$ Gate Stacks on NBTI

A relative contribution of the interface and bulk dielectric defects to negative bias temperature instability (NBTI) in the metal/HfO₂/SiO₂ gate stacks was investigated. Interface trap generation was assessed by the direct-current current-voltage (DCIV) technique, which independently measures the interface defect density from bulk oxide charges and delineates the contribution of the interface defect generation to the overall NBTI measured by the threshold voltage shift (DeltaV_TH). The metal/high-fc induced traps in the interfacial SiO₂ layer were found to control the fast transient trap charging/generation processes, which affect the power-law exponents of DeltaV_TH and the stress-generated interface trap density DeltaD_IT stress time dependencies. Similar kinetics of the long-term DeltaV_TH(t) and DeltaD_IT(t) dependencies in the high-fe and SiO₂ gate stacks suggests that the degradation is governed by the same mechanism of trap charging/generation in the SiO₂ film. The investigation leads to a novel methodology for the time-to-failure (TTF) extrapolation, in which the measured DeltaV_TH and DeltaD_IT values are adjusted for the contributions from the fast transient defect charging/generation processes. It is shown that the conventional TTF analysis might greatly overestimate TTF. Post-NBTI stress recovery at zero relaxation voltage measured by the DCIV method showed that oxide charges and interface traps relax at the same rate indicating that the interface processes may dominate DeltaV_TH relaxation. At positive relaxation voltages, however, the oxide charge relaxation exhibits a fast transient component. Relaxation at positive bias also shows an as yet unexplained fast component in the interface trap recovery.     

Energy and Spatial Distribution of Traps in SiO2/Al2O3 nMOSFETs

The energy and spatial profiling of the interface and near-interface traps in n-channel MOSFETs with SiO₂/Al₂ O₃ gate dielectrics is investigated by charge-pumping (CP) measurements. By increasing the amplitude as well as lowering the frequency of the gate pulse, an increase of the charge recombined per cycle was observed, and it was explained by the contributions of additional traps located higher in energy and deeper in position at the SiO₂/Al₂O₃ interface. In addition, CP currents, acquired after different constant voltage stress, have been used to investigate the trap generation in this dielectric stack     

Hot-Carrier- and Constant-Voltage-Stress-Induced Low-Frequency Noise in Nitrided High- $k$ Dielectric MOSFETs

Understanding and minimization of low-frequency noise (LFN) originating from high- $k$ (HK) gate dielectrics in newgeneration MOSFETs are of critical importance to applications in RF, analog, and digital circuits. To understand the effect of stress conditions on noise, nMOSFETs were subjected to accelerated hot-carrier stress (HCS) and positive constant-voltage stress (CVS). The additional LFN introduced through stressing was evaluated on nMOSFETs with TiN metal gate and HfSiON gate dielectric. Nitridation of HfSiO gate-dielectric MOSFETs was achieved by either a high-temperature $hbox{NH}_{3}$ anneal or a lower temperature plasma anneal. Influence of different dielectric nitridation procedures on the stress-induced degradation of transconductance, threshold properties, and LFN was studied. Worst degradation conditions, i.e., $V_{g} = V_{d}$, were used for HCS, whereas for CVS, the vertical field was fixed at 10 MV/cm for all transistors to achieve comparable stressing conditions. Plasma-nitrided devices showed less increase in their noise in the linear operation region than the thermally nitrided devices. This difference in noise behavior is attributed to the nitrogen profile across the HK/Si interface and in the bulk of the HK oxide caused by different nitridation techniques. The dielectric defect profile resultant from different annealing techniques was consistent with the spectral form of the observed drain-voltage LFN.      

Total reflection X-ray fluorescence spectrometry for the introduction of novel materials in clean-room production environments

In this paper, a number of case studies on the analysis of novel metallic contaminants on conventional and alternative substrates using the technique of total reflection X-ray fluorescence spectrometry (TXRF) is presented. Investigated materials include Si and Ge substrates, high-/spl kappa/ dielectric contaminants, and layers, and Si wafers contaminated with elements from metal gates and Cu interconnects. One focus is on the application and optimization of detection limits in direct TXRF. For the TXRF analysis of contaminants on Si wafers, a general conclusion is that a combination of three excitation sources is needed to cover the whole range of interest: a low-energy excitation (about 5 keV, e.g., WM/spl alpha/, Cr K/spl alpha/) for the low Z elements such as Na, Mg, and Al, a moderate-energy excitation (10-20 keV, e.g., WL/spl beta/, MoK/spl alpha/) for the 3d-transition elements, and a high-energy excitation (25-35 keV, e.g., W, continuum) for the analysis of elements such as Zr, Ru, Mo, and Pd. Also, for the analysis of novel substrates using direct TXRF, a careful selection of the excitation source results in better detection limits. In this way, detection limits at 10/sup 10/-10/sup 11/ at/cm/sup 2/ can be achieved, even for novel contaminants and substrates. As the International Technology Roadmap for Semiconductors (ITRS) requires control below 5/spl times/10/sup 9/ at/cm/sup 2/, the application of a preconcentration procedure such as vapor phase decomposition-droplet collection TXRF (VPD-DC-TXRF) is required. Proper use of this procedure allows the improvement of the detection limits by two to three orders of magnitude, depending on wafer size and chemical collection efficiency. The usability of this preconcentration procedure in combination with TXRF will be demonstrated for noble elements and germanium substrates.     

Comparison of Hafnium Precursors for the MOCVD of HfO2 for Gate Dielectric Applications

Hafnium oxide films were deposited on Si (100) substrates using metal-organic chemical vapor deposition (MOCVD) and evaluated for gate dielectric applications. For this study, two types of precursors were tested: an oxygenated one, Hf butoxide-mmp, and an oxygen-free one, Hf diethyl-amide. Depositions were carried out in the temperature range of 350–650°C. However, the discussion is focused on amorphous films. The films were compared on the basis of growth rate, phase development, density, interface characteristics, and electrical properties. A similar amorphous to polycrystalline phase transition temperature was found for both precursors. For low deposition temperatures the growth rate for the amide precursor was significantly higher than for the butoxide-mmp precursor and films prepared with the amide precursor contained a lower carbon impurity content than with the butoxide-mmp one. The dielectric constant was slightly higher for amorphous HfO₂ deposited from the amide precursor than for the butoxide-mmp one. Only in respect to the trap density does the butoxide precursor seem advantageous.     

Role of annealing temperature in the oxide charge distribution in high-$$\kappa $$-based MOS devices: simulation and experiment

The effect of rapid thermal annealing on the oxide charge distribution of Al/HfO\(_2\)/SiO\(_2\)/Si metal–oxide–semiconductor structures are studied using technology computer-aided design (TCAD) simulations and experiments. The simulated electrical characteristics are compared with experimentally obtained data. The interface traps are found to be nonuniform in nature and laterally distributed following a Gaussian profile. The distribution of interface trap charges arises because of spatial electric field variation in the oxide film upon gate bias application. The interface trap density is found to decrease with increase in annealing temperature. It is further observed that, at higher annealing temperature, the fixed oxide charge density increases due to interfacial Hf silicate formation.     

Enhanced SiO/sub 2/ reliability on deuterium-implanted silicon

Stress-induced leakage current and time-dependent dielectric breakdown were investigated to examine the reliability of gate oxides grown on hydrogen- and deuterium-implanted silicon substrates. An order of magnitude improvement in charge-to-breakdown was observed for the deuterium-implanted devices as compared with the hydrogen-implanted ones. Such reliability improvement may be explained by the reduction of defects in the SiO/sub 2/ and Si/SiO/sub 2/ interface, such as Si dangling bonds, weak Si-Si bonds, and strained Si-O bonds due to the retention of implanted deuterium at the interface and in the bulk oxide as confirmed by secondary ion mass spectroscopy.     

Impact of STI on the reliability of narrow-width pMOSFETs with advanced ALD N/O gate stack

For the first time, a shallow trench isolation (STI)-induced enhanced degradation in pMOSFETs for ultrathin gate oxide devices has been observed. The I/sub D/ degradation is enhanced as a reduction in the gate width and the hot carrier (HC) or negative bias temperature instability (NBTI) effect. Extensive studies have been compared for atomic layer deposition (ALD)-grown and plasma-treated oxide pMOSFETs. Different temperature dependences were observed. At room temperature, hole trap is dominant for the device degradation, in which hole-trap-induced V/sub T/ is significant, whereas at high temperature under NBTI stress, interface trap becomes more significant, which dominates the device I/sub D/ degradation. In addition, the V/sub T/ rolloff can be modeled as a width narrowing effect specifically for STI. More importantly, the NBTI-induced interface/oxide traps are strongly related to the hydrogen and N/sub 2/ content in the gate oxide formation process. The interface trap generation is suppressed efficiently using the ALD-grown gate oxide. These results provide a valuable guideline for the understanding of the HC and NBTI reliabilities in an advanced ALD-grown gate oxide processes/devices.     

Conduction band-edge States associated with the removal of d-state degeneracies by the Jahn-Teller effect

X-ray absorption spectroscopy (XAS) is used to study band edge electronic structure of high-/spl kappa/ transition metal (TM) and trivalent lanthanide rare earth (RE) oxide gate dielectrics. The lowest conduction band d/sup */-states in TiO/sub 2/, ZrO/sub 2/ and HfO/sub 2/ are correlated with: 1) features in the O K/sub 1/ edge, and 2) transitions from occupied Ti 2p, Zr 3p and Hf 4p states to empty Ti 3d-, Zr 4d-, and Hf 5d-states, respectively. The relative energies of d-state features indicate that the respective optical bandgaps, E/sub opt/ (or equivalently, E/sub g/), and conduction band offset energy with respect to Si, E/sub B/, scale monotonically with the d-state energies of the TM/RE atoms. The multiplicity of d-state features in the Ti L/sub 2,3/ spectrum of TiO/sub 2/, and in the derivative of the O K/sub 1/ spectra for ZrO/sub 2/ and HfO/sub 2/ indicate a removal of d-state degeneracies that results from a static Jahn-Teller effect in these nanocrystalline thin film oxides. Similar removals of d-state degeneracies are demonstrated for complex TM/RE oxides including Zr and Hf titanates, and La, Gd and Dy scandates. Analysis of XAS and band edge spectra indicate an additional band edge state that is assigned Jahn-Teller distortions at internal grain boundaries. These band edges defect states are electronically active in photoconductivity (PC), internal photoemission (IPE), and act as bulk traps in metal oxide semiconductor (MOS) devices, contributing to asymmetries in tunneling and Frenkel-Poole transport that have important consequences for performance and reliability in advanced Si devices.     

A drain avalanche hot carrier lifetime model for n- and p-channel MOSFETs

A simple and physical drain avalanche hot carrier lifetime model has been proposed. The model is based on a mechanism of interface trap generation caused by recombination of hot electrons and hot holes. The lifetime is modeled as /spl tau/(I/sub d//W)/sup 2//spl prop/(I/sub sub//I/sub d/)/sup -m/. The formula is different from the conventional /spl tau/I/sub d//W-I/sub sub//I/sub d/ model in that the exponent of I/sub d//W is 2, which results from the assumed mechanism of the two-carrier recombination. It is shown that the mechanism gives a physical basis of the empirical /spl tau/-I/sub sub//W model for NMOSFETs. The proposed model has been validated experimentally both for NMOSFETs and for PMOSFETs. Model parameters extracted from experimental data show that carrier critical energies for creating damage are lower than the interface potential barriers. It is supposed that oxide band edge tailing enables low-energy carriers to create the damage. The channel hot electron condition becomes the worst case in short channel NMOSFETs, because gate voltage dependence of the maximum channel electric field decreases.     

1/f Noise: threshold voltage and ON-current fluctuations in 45 nm device technology due to charged random traps

Discrete impurity effects in terms of their statistical variations in number and position in the inversion and depletion region of a MOSFET, as the gate length is aggressively scaled, have recently been investigated as being a major cause of reliability degradation observed in intra-die and die-to-die threshold voltage variation on the same chip resulting in significant variation in saturation drive (on) current and transconductance degradation—two key metrics for benchmark performance of digital and analog integrated circuits. In this paper, in addition to random dopant fluctuations (RDF), the influence of random number and position of interface traps lying close to Si/SiO₂ interface has been examined as it poses additional concerns because it leads to enhanced experimentally observed fluctuations in drain current and threshold voltage. In this context, the authors of this article present novel EMC based simulation study on trap induced random telegraph noise (RTN) responsible for statistical fluctuation pattern observed in threshold voltage, its standard deviation and drive current in saturation for 45 nm gate length technology node MOSFET device. From the observed simulation results and their analysis, it can be projected that with continued scaling in gate length and width, RTN effect will eventually supersede as a major reliability bottleneck over the already present RDF phenomenon. The fluctuation patterns observed by EMC simulation outcomes for both drain current and threshold voltage have been analyzed for the cases of single trap and two traps closely adjacent to one another lying in the proximity of the Si/SiO₂ interface between source to drain region of the MOSFET and explained from analytical device physics perspectives.     

Dielectric and conductive spectra of the composite of barium titanate and LiClO/sub 4/-doped polyethylene oxide

Dielectric and conductive frequency spectra in a 10 mHz-10 GHz range have been measured for a composite consisting of barium titanate (BaTiO/sub 3/) inclusions dispersed in a LiClO/sub 4/-doped polyethylene oxide (Li-PEO) matrix with volume fraction /spl Phi/ = 0-40%. Pure Li-PEO behaves as a dielectric showing a segmental-mode dielectric relaxation at high frequencies (dielectric regime) and transfers to an ionic conductor below 10 MHz (conductive regime). BaTiO/sub 3/ is a ferroelectric having a very large dielectric permittivity and spontaneous polarization. The introduction of BaTiO/sub 3/ into Li-PEO caused a rapid increase in permittivity in the dielectric regime. In the conductive regime, the composite exhibited an additional relaxation at a frequency related to the ratio of DC conductivity of Li-PEO and the permittivity of BaTiO/sub 3/. This relaxation was attributed to accumulation of dissociated Li/sup +/ and ClO4/sup o/ns at the inclusion/matrix interface which resulted in an increase of effective permittivity and a decrease of effective conductivity. Quantitative analyses based on mixing laws for the two-phase spherical dispersion system have shown that the Bruggeman equation accurately predicted the /spl Phi/-dependence of the effective permittivity over the entire frequency range. Regarding the effective conductivity, it predicted values lower than the observed. We attributed this discrepancy to the spontaneous polarization of BaTiO/sub 3/, which induced ion trapping to reduce the DC conductivity of Li-PEO matrix.