Extraction of the Effective Mobility of $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs

The extraction of the effective mobility on $hbox{In}_{0.53} hbox{Ga}_{0.47}hbox{As}$ metal–oxide–semiconductor field-effect transistors (MOSFETs) is studied and shown to be greater than 3600 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$. The removal of $C_{rm it}$ response in the split $C$–$V$ measurement of these devices is crucial to the accurate analysis of these devices. Low-temperature split $C$–$V$ can be used to freeze out the $D_{rm it}$ response to the ac signal but maintain its effect on the free carrier density through the substrate potential. Simulations that match this low-temperature data can then be “warmed up” to room temperature and an accurate measure of $Q_{rm inv}$ is achieved. These results confirm the fundamental performance advantages of $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs.      

Positive Bias Temperature Instability (PBTI) Characteristics of Contact-Etch-Stop-Layer-Induced Local-Tensile-Strained $hbox{HfO}_{2}$ nMOSFET

The positive bias temperature instability (PBTI) characteristics of contact-etch-stop-layer (CESL)-strained $hbox{HfO}_{2}$ nMOSFET are thoroughly investigated. For the first time, the effects of CESL on an $hbox{HfO}_{2}$ dielectric are investigated for PBTI characteristics. A roughly 50% reduction of $V_{rm TH}$ shift can be achieved for the 300-nm CESL $hbox{HfO}_{2}$ nMOSFET after 1000-s PBTI stressing without obvious $ hbox{HfO}_{2}/hbox{Si}$ interface degradation, as demonstrated by the negligible charge pumping current increase ($≪$ 4%). In addition, the $hbox{HfO}_{2}$ film of CESL devices has a deeper trapping level (0.83 eV), indicating that most of the shallow traps (0.75 eV) in as-deposited $ hbox{HfO}_{2}$ film can be eliminated for CESL devices.      

High-Density and Low-Leakage-Current MIM Capacitor Using Stacked $hbox{TiO}_{2}/hbox{ZrO}_{2}$ Insulators

We have fabricated high-$kappa hbox{Ni}/hbox{TiO}_{2}/hbox{ZrO}_{2}/ hbox{TiN}$ metal–insulator–metal (MIM) capacitors. A low leakage current of $hbox{8} times hbox{10}^{-8} hbox{A/cm}^{2}$ at 125 $^{circ}hbox{C}$ was obtained with a high 38- $hbox{fF}/muhbox{m}^{2}$ capacitance density and better than the $hbox{ZrO}_{2}$ MIM capacitors. The excellent device performance is due to the lower electric field in 9.5-nm-thick $hbox{TiO}_{2}/ hbox{ZrO}_{2}$ devices to decrease the leakage current and to a higher $kappa$ value of 58 for $ hbox{TiO}_{2}$ as compared with that of $hbox{ZrO}_{2}$ to preserve the high capacitance density.      

A Comparative NBTI Study of $hbox{HfO}_{2}$, $hbox{HfSiO}_{x}$, and SiON p-MOSFETs Using UF-OTF $I_{rm DLIN}$ Technique

The time, temperature, and oxide-field dependence of negative-bias temperature instability is studied in $hbox{HfO}_{2}/hbox{TiN}$, $ hbox{HfSiO}_{x}/hbox{TiN}$, and SiON/poly-Si p-MOSFETs using ultrafast on-the-fly $I_{rm DLIN}$ technique capable of providing measured degradation from very short (approximately microseconds) to long stress time. Similar to rapid thermal nitrided oxide (RTNO) SiON, $hbox{HfO}_{2}$ devices show very high temperature-independent degradation at short (submilliseconds) stress time, not observed for plasma nitrided oxide (PNO) SiON and $hbox{HfSiO}_{x}$ devices. $hbox{HfSiO}_{x}$ shows lower overall degradation, higher long-time power-law exponent, field acceleration, and temperature activation as compared to $hbox{HfO}_{2}$, which are similar to the differences between PNO and RTNO SiON devices, respectively. The difference between $ hbox{HfSiO}_{x}$ and $hbox{HfO}_{2}$ can be attributed to differences in N density in the $hbox{SiO}_{2}$ IL of these devices.      

Comparative Study of the Low-Frequency-Noise Behaviors in a-IGZO Thin-Film Transistors With $hbox{Al}_{2}hbox{O}_{3}$ and $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ Gate Dielectrics

A comparative study is made of the low-frequency noise (LFN) in amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) with $hbox{Al}_{2}hbox{O}_{3}$ and $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ gate dielectrics. The LFN is proportional to $hbox{1}/f^{gamma}$, with $gamma sim hbox{1}$ for both devices, but the normalized noise for the $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ device is two to three orders of magnitude lower than that for the $hbox{Al}_{2} hbox{O}_{3}$ device. The mobility fluctuation is the dominant LFN mechanism in both devices, but the noise from the source/drain contacts becomes comparable to the intrinsic channel noise as the gate overdrive voltage increases in $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ devices. The $hbox{SiN}_{x}$ interfacial layer is considered to be very effective in reducing LFN by suppressing the remote phonon scattering from the $hbox{Al}_{2}hbox{O}_{3}$ dielectric. Hooge's parameter is extracted to $sim !!hbox{6.0} times hbox{10}^{-3}$ in $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ devices.      

Performance Improvement of N-Type $hbox{TiO}_{x}$ Active-Channel TFTs Grown by Low-Temperature Plasma-Enhanced ALD

We report on performance improvement of $n$-type oxide–semiconductor thin-film transistors (TFTs) based on $hbox{TiO}_{x}$ active channels grown at 250 $^{circ}hbox{C}$ by plasma-enhanced atomic layer deposition. TFTs with as-grown $hbox{TiO}_{x}$ films exhibited the saturation mobility $(mu_{rm sat})$ as high as 3.2 $hbox{cm}^{2}/hbox{V}cdothbox{s}$ but suffered from the low on–off ratio $(I_{rm ON}/I_{rm OFF})$ of $hbox{2.0} times hbox{10}^{2}$. $hbox{N}_{2}hbox{O}$ plasma treatment was then attempted to improve $I_{rm ON}/I_{rm OFF}$. Upon treatment, the $hbox{TiO}_{x}$ TFTs exhibited $I_{rm ON}/I_{rm OFF}$ of $hbox{4.7} times hbox{10}^{5}$ and $mu_{rm sat}$ of 1.64 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, showing a much improved performance balance and, thus, demonstrating their potentials for a wide variety of applications such as backplane technology in active-matrix displays and radio-frequency identification tags.      

$hbox{TiN/ZrO}_{2}$/Ti/Al Metal–Insulator–Metal Capacitors With Subnanometer CET Using ALD-Deposited $hbox{ZrO}_{2}$ for DRAM Applications

We provide the first report of the structural and electrical properties of $hbox{TiN/ZrO}_{2}$/Ti/Al metal–insulator–metal capacitor structures, where the $hbox{ZrO}_{2}$ thin film (7–8 nm) is deposited by ALD using the new zirconium precursor ZrD-04, also known as Bis(methylcyclopentadienyl) methoxymethyl. Measured capacitance–voltage ($C$– $V$) and current–voltage ( $I$–$V$) characteristics are reported for premetallization rapid thermal annealing (RTP) in $hbox{N}_{2}$ for 60 s at 400 $^{circ}hbox{C}$, 500 $^{circ}hbox{C}$, or 600 $^{ circ}hbox{C}$. For the RTP at 400 $^{circ}hbox{C}$ , we find very low leakage current densities on the order of nanoamperes per square centimeter at a gate voltage of 1 V and low capacitance equivalent thickness values of $sim$ 0.9 nm at a gate voltage of 0 V. The dielectric constant of $ hbox{ZrO}_{2}$ is 31 $pm$ 2 after RTP treatment at 400 $^{circ}hbox{C}$.      

An Analytical Method to Extract the Physical Parameters of a Solar Cell From Four Points on the Illuminated $J{-}V$ Curve

For a variety of solar cells, it is shown that the single exponential $J{-}V$ model parameters, namely—ideality factor $eta$ , parasitic series resistance $R_{s}$, parasitic shunt resistance $R_{rm sh}$, dark current $J_{0}$, and photogenerated current $J_{rm ph}$ can be extracted simultaneously from just four simple measurements of the bias points corresponding to $V_{rm oc}$, $sim!hbox{0.6}V_{rm oc}$, $J_{rm sc}$, and $sim! hbox{0.6}J_{rm sc}$ on the illuminated $J{-}V$ curve, using closed-form expressions. The extraction method avoids the measurements of the peak power point and any $dJ/dV$ (i.e., slope). The method is based on the power law $J{-}V$ model proposed recently by us.      

Characterization and Modeling of RF-Performance $(f_{T})$ Fluctuation in MOSFETs

The fluctuation of RF performance (particularly for $f_{T}$ : cutoff frequency) in the transistors fabricated by 90-nm CMOS technology has been investigated. The modeling for $f_{T}$ fluctuation is well fitted with the measurement data within approximately 1% error. Low-$V_{t}$ transistors (fabricated by lower doping concentration in the channel) show higher $f_{T}$ fluctuation than normal transistors. Such a higher $f_{T}$ fluctuation results from $C_{rm gg}$ (total gate capacitance) variation rather than $g_{m}$ variation. More detailed analysis shows that $C_{rm gs} + C_{rm gb}$ (charges in the channel and the bulk) are predominant factors over $C_{rm gd}$ (charges in LDD/halo region) to determine $C_{rm gg}$ fluctuation.      

Low-Threshold Strained Quantum-Well GaSb-Based Lasers Emitting in the 2.5- to 2.7-$mu$ m Wavelength Range

GaInAsSb–GaSb strained quantum-well (QW) ridge waveguide diode lasers emitting in the wavelength range from 2.51 to 2.72 $ mu{hbox {m}}$ have been grown by molecular beam epitaxy. The devices show ultralow threshold current densities of 44 $hbox{A}/{hbox {cm}}^{2}$ (${L}rightarrow infty $) for a single QW device at 2.51 $ mu{hbox {m}}$, which is the lowest reported value in continuous-wave operation near room temperature (15 $^{circ}hbox{C}$) at this wavelength. The devices have an internal loss of 3 ${hbox {cm}}^{-1}$ and a characteristic temperature of 42 K. By using broader QWs, wavelengths up to 2.72 $mu{hbox {m}}$ could be achieved.      

Compact Microracetrack Resonator Devices Based on Small SU-8 Polymer Strip Waveguides

Compact microracetrack resonator (MRR) devices are presented with small SU-8 polymer strip waveguides. The SU-8 strip waveguide has an SU-8 polymer core $(n {sim} 1.573)$ , a SiO$_{2}$ buffer $(n {sim} 1.445)$, and an air cladding. The fabricated straight waveguide has a low propagation loss of about 0.1 dB/mm. With such a high index-contrast optical waveguide, a compact MRR with a small bending radius ( $sim$150 $mu$m) are designed and fabricated. The measured spectral responses of the through/drop ports show a $Q$-factor of 8000.      

Breakdown Enhancement of AlGaN/GaN HEMTs on 4-in Silicon by Improving the GaN Quality on Thick Buffer Layers

We have achieved a 9- $muhbox{m}$-thick AlGaN/GaN high-electron mobility transistor (HEMT) epilayer on silicon using thick buffer layers with reduced dislocation density $(D_{D})$. The crack-free 9- $muhbox{m}$-thick epilayer included 2- $muhbox{m}$ i-GaN and 7- $ muhbox{m}$ buffer. The HEMTs fabricated on these devices showed a maximum drain–current density of 625 mA/mm, transconductance of 190 mS/mm, and a high three-terminal OFF breakdown of 403 V for device dimensions of $L_{g}/W_{g}/L_{rm gd} = hbox{1.5/15/3} muhbox{m}$ . Without using a gate field plate, this is the highest $BV$ reported on an AlGaN/GaN HEMT on silicon for a short $L_{rm gd}$ of 3 $muhbox{m}$. A very high $BV$ of 1813 V across 10- $mu hbox{m}$ ohmic gap was achieved for i-GaN grown on thick buffers. As the thickness of buffer layers increased, the decreased $D_{D}$ of GaN and increased resistance between surface electrode and substrate yielded a high breakdown.      

Low-Voltage Organic Field-Effect Transistor With PMMA/$ hbox{ZrO}_{2}$ Bilayer Dielectric

This paper reports on the application of a bilayer polymethylmethacrylate (PMMA)/ $hbox{ZrO}_{2}$ dielectric in copper phthalocyanine (CuPc) organic field-effect transistors (OFETs). By depositing a PMMA layer on $hbox{ZrO}_{2}$, the leakage of the dielectric is reduced by one order of magnitude compared to single-layer $hbox{ZrO}_{2}$. A high-quality interface is obtained between the organic semiconductor and the combined insulators. By integrating the advantages of polymer and high- $k$ dielectrics, the device achieves both high mobility and low threshold voltage. The typical field-effect mobility, threshold voltage, on/off current ratio, and subthreshold slope of OFETs with bilayer dielectric are $hbox{5.6}timeshbox{10}^{-2} hbox{cm}^{2}/hbox{V} cdot hbox{s}$, 0.8 V, $hbox{1.2} times hbox{10}^{3}$, and 2.1 V/dec, respectively. By using the bilayer dielectrics, the hysteresis observed in the devices with single-layer $hbox{ZrO}_{2}$ is no longer present.      

Linear Systems, Sparse Solutions, and Sudoku

In this paper, we show that Sudoku puzzles can be formulated and solved as a sparse linear system of equations. We begin by showing that the Sudoku ruleset can be expressed as an underdetermined linear system: ${mmb{Ax}}={mmb b}$, where ${mmb A}$ is of size $mtimes n$ and $n>m$. We then prove that the Sudoku solution is the sparsest solution of ${mmb{Ax}}={mmb b}$, which can be obtained by $l_{0}$ norm minimization, i.e. $minlimits_{mmb x}Vert{mmb x}Vert_{0}$ s.t. ${mmb{Ax}}={mmb b}$. Instead of this minimization problem, inspired by the sparse representation literature, we solve the much simpler linear programming problem of minimizing the $l_{1}$ norm of ${mmb x}$, i.e. $minlimits_{mmb x}Vert{mmb x}Vert_{1}$ s.t. ${mmb{Ax}}={mmb b}$, and show numerically that this approach solves representative Sudoku puzzles.      

A General and Reliable Model for Charge Pumping—Part I: Model and Basic Charge-Pumping Mechanisms

Starting from a rigorous analysis of the charge-pumping (CP) mechanisms, a general CP model, which accounts for capture time constant distribution (TCD) that exists at $hbox{Si}$ –$hbox{SiO}_{2}$ interface, is derived. By doing so, CP curves of state-of-the-art MOS devices are extremely well simulated. It is remarkable as this is achieved in a large range of experimental conditions, confirming the reliability of the approach. The interpretation of the TCDs in terms of distance from the $hbox{Si}$– $hbox{SiO}_{2}$ interface through carrier tunneling, as used initially, is discussed in the light of recent results which show that the traps which dominate at the $hbox{Si}$–$ hbox{SiO}_{2}$ interface in fully processed devices, at least down to $hbox{10}^{9} hbox{eV}^{-1}cdothbox{cm}^{-2}$, are acceptor-like in the upper part of the bandgap, donor-like in its lower part and are amphoteric, i.e., have the properties of the $P_{b0}$ centers. As the model allows the energy and depth regions probed to be known in all experimental conditions, this paper focuses on the basic CP features at the $hbox{Si}$–$ hbox{SiO}_{2}$ interface and toward the insulator depth. For that, one of the standard CP curves is used.      

Impacts of $hbox{N}_{2}$ and $hbox{NH}_{3}$ Plasma Surface Treatments on High-Performance LTPS-TFT With High-$kappa$ Gate Dielectric

Low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) with high- $kappa$ gate dielectrics and plasma surface treatments are demonstrated for the first time. Significant field-effect mobility $mu_{rm FE}$ improvements of $sim$86.0% and 112.5% are observed for LTPS-TFTs with $hbox{HfO}_{2}$ gate dielectric after $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments, respectively. In addition, the $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments can also reduce surface roughness scattering to enhance the field-effect mobility $mu_{rm FE}$ at high gate bias voltage $V_{G}$, resulting in 217.0% and 219.6% improvements in driving current, respectively. As a result, high-performance LTPS-TFT with low threshold voltage $V_{rm TH} sim hbox{0.33} hbox{V}$, excellent subthreshold swing S.S. $sim$0.156 V/decade, and high field-effect mobility $mu_{rm FE} sim hbox{62.02} hbox{cm}^{2}/hbox{V} cdot hbox{s}$ would be suitable for the application of system-on-panel.      

Electrical Properties of $hbox{Bi}_{5}hbox{Nb}_{3} hbox{O}_{15}$ Thin Film Grown on $hbox{TiN}/hbox{SiO}_{2}/ hbox{Si}$ at Room Temperature for Metal–Insulator–Metal Capacitors

Buckling was observed in $hbox{Bi}_{5}hbox{Nb}_{3}hbox{O}_{15}$ (BiNbO) films grown on $hbox{TiN}/hbox{SiO}_{2}/hbox{Si}$ at 300 $^{circ}hbox{C}$ but not in films grown at room temperature and annealed at 350 $^{circ}hbox{C}$. The 45-nm-thick films showed a high capacitance density and a low dissipation factor of 8.81 $hbox{fF}/muhbox{m}^{2}$ and 0.97% at 100 kHz, respectively, with a low leakage current density of 3.46 $hbox{nA}/hbox{cm}^{2}$ at 2 V. The quadratic and linear voltage coefficients of capacitance of this film were 846 $hbox{ppm}/hbox{V}^{2}$ and 137 ppm/V, respectively, with a low temperature coefficient of capacitance of 226 $hbox{ppm}/^{circ}hbox{C}$ at 100 kHz. This suggests that a BiNbO film grown on a $hbox{TiN}/ hbox{SiO}_{2}/hbox{Si}$ substrate is a good candidate material for high-performance metal–insulator–metal capacitors.      

Low-Temperature-Processed Inorganic Gate Dielectrics for Plastic-Substrate-Based Organic Field-Effect Transistors

Low-temperature-processed inorganic gate dielectrics were employed here to yield high-performance organic field-effect transistors (FETs) on flexible plastic substrates. $hbox{SiN}_{x}$ dielectrics deposited at room temperature and $hbox{SiN}_{x}$ /sol–gel silica dielectric bilayer processed below 100 $^{ circ}hbox{C}$ were demonstrated to be viable gate dielectric materials, with the latter yielding effective field-effect mobilities of $sim!!hbox{1} hbox{cm}^{2}/hbox{V} cdothbox{s}$ at operating voltages of under $-$ 5 V with an on–off current ratio in the range of $hbox{10}^{5}$ . The enhancement in device performance was attributed to an improved semiconductor–dielectric interface and a larger grain size of the pentacene deposited on the bilayer dielectrics. The flexibility of FETs fabricated on polyester substrates was also demonstrated with insignificant changes in device performance upon subjecting the devices to strains of 2.27%.      

Negative Bias Temperature Instability Dominated Degradation of Metal-Induced Laterally Crystallized p-Type Polycrystalline Silicon Thin-Film Transistors

Device degradation of solution-based metal-induced laterally crystallized p-type polycrystalline silicon (poly-Si) thin-film transistors (TFTs) is studied under dc bias stresses. While typical negative bias temperature instability (NBTI) or electron injection (EI) is observed under $-V_{g}$ or $-V_{d}$ only stress, respectively, no typical hot carrier (HC) degradation can be identified under high $-V_{d}$ stress combined with either low or high $-V_{g}$ stress. Instead, mixed NBTI and EI degradation is observed under combined low $-V_{g}$ and $-V_{d}$ stresses; and combined degradation of NBTI and HC occurs under high $-V_{d}$ and moderate $-V_{g}$ stresses. NBTI is the dominant mechanism in both cases. Grain boundary (GB) trap generation is found to correlate with the NBTI degradation with the same time exponent, suggesting the key role of GB trap generation in poly-Si TFTs' degradation.      

2 MHz AO $Q$ -switched ${rm TEM}_{00}$ Grazing Incidence Laser With 3 at.% Neodymium Doped Nd:YVO$_{4}$

We present a detailed experimental and theoretical study of the ultrahigh repetition rate AO $Q$ -switched ${rm TEM}_{00}$ grazing incidence laser. Up to 2.1 MHz $Q$-switching with ${rm TEM}_{00}$ output of 8.6 W and 2.2 MHz $Q$ -switching with multimode output of 10 W were achieved by using an acousto-optics $Q$ -switched grazing-incidence laser with optimum grazing-incidence angle and cavity configuration. The crystal was 3 at.% neodymium doped Nd:YVO$_{4}$ slab. The pulse duration at 2 MHz repetition rate was about 31 ns. The instabilities of pulse energy at 2 MHz repetition rate were less than ${pm}6.7hbox{%}$ with ${rm TEM}_{00}$ operation and ${pm}3.3hbox{%}$ with multimode operation respectively. The modeling of high repetition rate $Q$-switched operation is presented based on the rate equation, and with the solution of the modeling, higher pump power, smaller section area of laser mode, and larger stimulated emission cross section of the gain medium are beneficial to the $Q$-switched operation with ultrahigh repetition rate, which is in consistent with the experimental results.