A study on the correlation between the grain size and the conversion efficiency of Mc-Si solar cells

For grain size estimation, a prototype system was developed by integrating a vision-acquiring hardware and a vision-assistant-processing module based on the platform software package of LabVIEW, to systematically estimate the average grain size of solar-grade multicrystalline (mc)-Si wafers. Three groups of 156 x 156 mm mc-Si wafers were selected to produce the average grain sizes of 3.4 mm (Group 1), 3.8 mm (Group II), and 4.6 mm (Group III), and were used for the fabrication of mc-Si solar cells by employing the standard mc-Si cell fabrication procedure of the 30 MW mass production line. The conversion efficiency including Jsc and Pmax, showed a quasi linear dependence on the mean grain size, with a correlation factor of 0.525%/mm. By combining the EL image and the grain size/position-dependent EQE spectra in a wavelength range of 400-1100 nm, the conversion efficiency of uniformly-surface-texturized mc-Si solar cells with larger grain sizes can be made much higher as a result of the much-reduced spatial density of the nano/microscope grain boundaries acting as recombination centers or traps.     

醋酸铜辅助催化刻蚀制备金刚线切割多晶硅片绒面

金刚线切割多晶硅片表面减反射结构难以制备的问题阻碍着多晶硅光伏的进步。银辅助的酸腐蚀是解决这一问题的较好方法,但银的消耗和废液处理等增加了成本。本研究提出了醋酸铜辅助催化刻蚀金刚线切割多晶硅片方案,考察了刻蚀反应温度和时间对硅片表面形貌的影响,确定了最优的反应温度和时间分别为25℃和5 min。在此条件下,所获得的多晶硅在300～1100 nm波段的平均反射率为15.1%。按照标准太阳电池制备工艺流片后,所获太阳电池的光电转换效率为19.4%。     

A run-to-run controller for product surface quality improvement

In semiconductor manufacturing, the surface quality of silicon wafers has a significant impact on the subsequent processes that produce devices using the wafers as a component. The surface quality of a wafer is characterised by a two-dimensional (2-D) data structure: the geometric requirement for the wafer surface is smooth and flat and the thickness should fall within certain specification limits. Therefore, both low deviation and high uniformity are desirable for control over the wafer quality. In this work, we develop a run-to-run control algorithm for improving wafer quality. Considering the unique 2-D data structure, we first construct a model that encompasses the spatial correlation of the observations on the wafer surface to link the wafer quality with the process variables, and subsequently develop a recursive algorithm to generate optimal set points for the controllable factors. More specifically, a Gaussian-Kriging model is used to characterise the spatial dependence of the thickness measures of the wafer and a recursive least square method is employed to update the estimates of the model parameters. The performance of the new controller is studied via simulation and compared with existing controllers, which demonstrates that the newly proposed controller can effectively reduce the surface variations of the silicon wafers.     

Improvements to the solar cell efficiency and production yields of low-lifetime wafers with effective phosphorus gettering

This research focuses on the improvement of solar cell efficiencies in low-lifetime wafers by implementing an appropriate gettering method of the diffusion process. The study also considers a reduction in the value of the reverse current at −12 V, an important electrical parameter related to the hot-spot heating of solar cells and modules, to improve the product's quality during commercial mass production. A practical solar cell production case study is examined to illustrate the use of the proposed method. The results of this case study indicate that variable-temperature gettering significantly improves solar cell efficiencies by 0.14% compared to constant-temperature methods when the wafer quality is poor. Moreover, this study finds that variable-temperature gettering raises production yields of low quality wafers by more than 30% by restraining the measurement value of the reverse current at −12 V during solar cell manufacturing.     

A Grain Orientation-Independent Single-Step Saw Damage Gettering/Wet texturing Process for Efficient Silicon Solar Cells

Improving electrical and optical properties is important in manufacturing high-efficiency solar cells. Previous studies focused on individual gettering and texturing methods to improve solar cell material quality and reduce reflection loss, respectively. This study presents a novel method called saw damage gettering with texturing that effectively combines both methods for multicrystalline silicon (mc-Si) wafers manufactured using the diamond wire sawing (DWS) method. Although mc-Si is not the Si material currently used in photovoltaic products, the applicability of this method using the mc-Si wafers as it contains all grain orientations is demonstrated. It utilizes saw damage sites on the wafer surfaces for gettering metal impurities during annealing. Additionally, it can crystallize amorphous silicon on wafer surfaces generated during the sawing process to allow conventional acid-based wet texturing. This texturing method and annealing for 10 min allow for the removal of metal impurities and effectively forms a textured DWS Si wafer. The results show that the open-circuit voltage (ΔV_oc = +29 mV), short-circuit current density (ΔJ_sc = +2.5 mA cm⁻²), and efficiency (Δη = +2.1%) improved in the p-type passivated emitter and rear cells (p-PERC) manufactured using this novel method, as compared to those in the reference solar cells.     

Surface integrity and removal mechanism in grinding sapphire wafers with novel vitrified bond diamond plates

In order to improve machining efficiency of sapphire wafer machining using the conventional loose abrasive process, fixed-abrasive diamond plates are investigated in this study for sapphire wafer grinding. Four vitrified bond diamond plates of different grain sizes (40?µm, 20?µm, 7?µm, and 2.5?µm) are developed and evaluated for grinding performance including surface roughness, surface topography, surface and subsurface damage, and material removal rate (MRR) of sapphire wafers. The material removal mechanisms, wafer surface finish, and quality of the diamond plates are also compared and discussed. The experiment results demonstrate that the surface material is removed in brittle mode when sapphire wafers are ground by the diamond plates with a grain size of 40?µm and 20?µm, and in ductile mode when that are ground by the diamond plates of grain sizes of 7?µm and 2.5?µm. The highest MRR value of 145.7?µm/min is acquired with the diamond plate with an abrasive size of 40?µm and the lowest surface roughness values of 3.5?nm in Ra is achieved with the 2.5?µm size.     

Integrated color defect detection method for polysilicon wafers using machine vision

For the typical color defects of polysilicon wafers,i.e.,edge discoloration,color inaccuracy and color non-uniformity,a new integrated machine vision detection method is proposed based on an HSV color model.By transforming RGB image into three-channel HSV images,the HSV model can efficiently reduce the disturbances of complex wafer textures.A fuzzy color clustering method is used to detect edge discoloration by defining membership function for each channel image.The mean-value classifying method and region growing method are used to identify the other two defects,respectively.A vision detection system is developed and applied in the production of polysilicon wafers.     

Shaped silicon-crystal wafers obtained by plastic deformation and their application to silicon-crystal lenses.

Plastic deformation is an unlikely process by which to mould pristine silicon wafers into three-dimensional shapes owing to the inevitable detrimental impact that the resulting mechanically induced defects would have on their electrical properties. However, if one were to find a way of doing so without substantial degradation of these properties, a range of new applications might be opened up. Here we report on the successful plastic deformation of silicon crystal wafers for the preparation of wafers with various shapes. A silicon wafer was set between dies and pressed at high temperatures. One application of shaped wafers is as well-shaped concave silicon crystal lenses or mirrors. The lattice plane of such a crystal lens has a curvature exactly along the surface. A concave spheroidal X-ray lens, in the form of two-dimensional Johann and Johansson's monochromators, is proposed for an X-ray optical component system. We propose and demonstrate a new solar cell system with the concave silicon crystal mirror used as both a solar cell and a focused mirror. This system can make use of the reflected photons from solar cells.     

Mechanical Strength of Silicon Wafers Cut by Loose Abrasive Slurry and Fixed Abrasive Diamond Wire Sawing

This paper reports on the mechanical strength of polycrystalline silicon wafers cut by loose abrasive slurry and fixed abrasive diamond wire sawing processes. Four line bending and biaxial flexure tests are used to evaluate the fracture strength of the wafers. Fracture strength of the wafers depends on the location, size, and orientation of microcracks in the silicon wafer and the distribution and magnitude of applied stresses. Measurement of microcracks at the wafer edge and center shows that edge cracks are typically larger than center cracks. Fixed abrasive diamond wire sawn wafers are found to have a higher crack density but smaller average crack length. Wafer fracture in four line bending is found to be primarily due to the propagation of edge cracks while center cracks are found to be the primary cause of wafer failure in biaxial flexure tests. Fracture mechanics based analyses demonstrate that crack orientation plays a significant role in four line bending, but not in biaxial flexure. Correlations of the wafer fracture strength and critical crack length agree well with microcrack measurements. The fracture strength of diamond cut wafers is found to be comparable or superior to the strength of slurry cut wafers.     

A hierarchical model for characterising spatial wafer variations

Silicon wafers are commonly used materials in the semiconductor manufacturing industry. Their geometric quality directly affects the production cost and yield. Therefore, improvement in the quality of wafers is critical for meeting the current competitive market needs. Conventional summary metrics such as total thickness variation, bow and warp can neither fully reflect the local variability within each wafer nor provide useful insight for root cause diagnosis and quality improvement. The advancement of sensing technology enables two-dimensional (2D) data mapping to characterise the geometric shapes of wafers, which provides more information than summary metrics. The objective of this research is to develop a statistical model to characterise the thickness variation of wafers based on 2D data maps. Specifically, the thickness variation of wafers is decomposed into macro-scale and micro-scale variations, which are modelled as a cubic curve and a first-order intrinsic Gaussian Markov random field, respectively. The models can successfully capture both the macro-scale mean trend and the micro-scale local variation, with important engineering implications for process monitoring, fault diagnosis and run-to-run control. A practical case study from a wafer manufacturing process is performed to show the effectiveness of the proposed methodology.     

Nondestructive evaluation of large-area PZN-8%PT single crystal wafers for medical ultrasound imaging probe applications

A nondestructive quality evaluation and control procedure for large-area, (001)-cut PZN-8%PT wafers is described. The crystals were grown by the flux technique engineered to promote (001) layer growth of the crystals. The wafers were sliced parallel to the (001) layer growth plane. Curie temperature (Tc) variations, measured with matching arrays of dot electrodes (of 5.0 mm in center-to-center spacing), were found to be better than +/- 4.0 degrees C both within wafers and from wafer to wafer. After selective dicing to give final wafers of narrower Tc distributions (e.g., +/- 3.0 degrees C or better), the wafers were coated with complete electrodes and poled at room temperature at 0.7-0.9 kV/mm. Typical overall properties of the poled wafers were: K3T = 5,200 (+/- 10% from wafer to wafer), tan delta < 0.01 (all wafers), and kt = 0.55 (+/- 5%) (all percentage variations are in relative percentages). Then, the distributions of K3S, tan delta, and kt were measured by the array dot electrode technique. The variations in K3S (hence K3T) and kt within individual wafers were found to be within +/- 10% and +/- 5%, respectively. The dielectric loss values, measured at 1 kHz, were consistently low, being < 0.01 throughout the wafers. The kt values determined by the dot electrodes were found to be about 5% smaller than those obtained with the complete electrodes, which can be attributed to an increase in capacitance ratio due to the partial electroding. The k33 values, deduced using the relation K3S approximately (1 - k33(2))K3T, from the mean K3S and overall K3T values, average 0.94 (+/- 2%). The present work shows that the distribution of Tc within wafers can be used as a convenient check for the uniformity in composition and electromechanical properties of PZN-8%PT single crystal wafers. Our results show that, to control deltaK3T and deltakt within individual wafer to < or = 10% and 5%, respectively, the variation in Tc within the wafer should be kept within +/- 3.0 degrees C or better.     

A Novel Defect Inspection Method for Semiconductor Wafer Based on Magneto-Optic Imaging

The defects of semiconductor wafer may be generated from the manufacturing processes. A novel defect inspection method of semiconductor wafer is presented in this paper. The method is based on magneto-optic imaging, which involves inducing eddy current into the wafer under test, and detecting the magnetic flux associated with eddy current distribution in the wafer by exploiting the Faraday rotation effect. The magneto-optic image being generated may contain some noises that degrade the overall image quality, therefore, in this paper, in order to remove the unwanted noise present in the magneto-optic image, the image enhancement approach using multi-scale wavelet is presented, and the image segmentation approach based on the integration of watershed algorithm and clustering strategy is given. The experimental results show that many types of defects in wafer such as hole and scratch etc. can be detected by the method proposed in this paper.     

A new cost effective method of planarisation for multiple metal layers in the sub-100 nm-region

The availability of multiple metal layers has become essential for high-density layouts and economic chip size. The presented paper describes an efficient and low-cost alternative to Chemical-Mechanical-Polishing (CMP). The method uses an auxiliary wafer as a sort of plunger. Starting with a preprocessed wafer, for example from a Complementary-Metal-Oxide-Semiconductor (CMOS) technology, a spin-on glass is applied before the deposition of the first metal layer. Afterwards a second silicon wafer will be covered homogeneously with photo resist and subsequentially coated with aluminum or titanium. This wafer serves as a plunger, while the metal layer protects the photo resist against impression. Whilst the plunger is pressed down on the spin-on glass, the first wafer is cooled down bonding the two wafers together. Separation of the wafers is accomplished by removing the photo resist layer. After the separation step any remaining photo resist as well as the aluminum layer are removed by etching. This process results in a planar surface which is optimally suited for the deposition and structuring of further metal layers which lead to more freedom concerning the complex interconnects in modern analog and digital circuits.     

Ultrathin Crystalline Silicon Nano and Micro Membranes with High Areal Density for Low-Cost Flexible Electronics

Ultrathin crystalline silicon is widely used as an active material for high-performance, flexible, and stretchable electronics, from simple passive and active components to complex integrated circuits, due to its excellent electrical and mechanical properties. However, in contrast to conventional silicon wafer-based devices, ultrathin crystalline silicon-based electronics require an expensive and rather complicated fabrication process. Although silicon-on-insulator (SOI) wafers are commonly used to obtain a single layer of crystalline silicon, they are costly and difficult to process. Therefore, as an alternative to SOI wafers-based thin layers, here, a simple transfer method is proposed for printing ultrathin multiple crystalline silicon sheets with thicknesses between 300 nm to 13 µm and high areal density (>90%) from a single mother wafer. Theoretically, the silicon nano/micro membrane can be generated until the mother wafer is completely consumed. In addition, the electronic applications of silicon membranes are successfully demonstrated through the fabrication of a flexible solar cell and flexible NMOS transistor arrays.     

Grain-size dependence of microcrack initiation in brittle materials

In this paper, the energy criterion is extended to predict the relationship between the temperature of microcrack initiation (T _MB) caused by thermal stressing in brittle materials and the grain size. The relation can be extrapolated to room temperature to provide an estimate of the critical grain size. When the relation was compared to literature data, it was found that: (1) the predicted inverse square root relation of T _MB to grain size is satisfied; (2) the room temperature intercept on the grain-size axis agrees well with the measured critical grain sizes. Also presented is a graphical method, based on the proposed relation, by which an engineering estimate of the critical grain size may be made from a minimal set of data.     

Basic Mechanisms and Models of Multi‐Wire Sawing

More than 80 % of the current solar cell production requires the cutting of large silicon crystals. While in the last years the cost of solar cell processing and module fabrication could be reduced considerably, the sawing costs remain high, about 30 % of the wafer production. At present the large crystals are cut using the multi‐wire slicing technology^[2] which has the advantage of a high throughput (several hundred wafers per day and machine), a small kerf loss of about 200 μm and almost no restrictions on the size of the ingots. Basic knowledge about the microscopic details of the sawing process is required in order to slice crystals in a controlled way. In the following the principles of the sawing process will be described in this review article as far as they are understood today.     

Thermo-Mechanical Failure Criterion at the Micron Scale in Electronic Devices

Thermo-mechanical failures may occur in the passivation layer of micro-electronic devices during the fabrication process. These are in form of cracks which initiate at keyhole corners. In order to predict and eventually prevent these cracks a failure criterion is presented, based on an average value of the elastic strain energy in the vicinity of a reentrant corner of any angle. The proposed strain energy density (SED) failure criterion is validated by a test including 24 full size wafers which have been fabricated with different parameters: the interconnects (metal lines) height, the passivation thickness, and the passivating plasma power which was shown to correlate with the mechanical properties of the passivation layer. For each wafer, a FE model has been constructed, and the SED computed. It has been clearly shown, that above the critical value of SED _cr[R=0.15μm]≈1000 [J/m ³], all wafers manufactured were cracked. The SED criterion seems to correlate well with the empirical observations, and may be used as a standard tool for the mechanical design of failure free micro-electronic devices.     

Interaction between process technology and material quality during the processing of multicrystalline silicon solar cells

Multicrystalline silicon is the most used material for the production of silicon solar cells. The quality of the as grown material depends on the quality of the feedstock and the crystallization process. Bulk impurities, crystal defects like dislocations and of course the grain boundaries determine the material quality and thus the solar cell conversion efficiency. Therefore minority carrier lifetime measurements are often done to characterize the material quality. But the measured values are from limited use because it is known that the solar cell process itself can dramatically change the minority carrier lifetime and the solar cell efficiency. In order to obtain more detailed information of the behaviour of different defect types additionally high-resolution LBIC (light beam induced current)-measurements have been done. Since LBIC needs a pn-junction for photocurrent generation the LBIC technique has been combined with the a-Si/c-Si heterojunction cell process, which makes it possible to manufacture solar cells even from as cut wafers without changing the material quality. With this combination of measurement and preparation techniques it was possible to analyze the influence of the diffusion process and the firing process on the behaviour of the three different defect types: grain boundaries, dislocation networks and bulk impurities.     

金刚石线锯切割多晶硅片表面制绒工艺研

晶体硅片的制绒技术是太阳能电池制造工艺中的关键步骤。本研究以工业中酸制绒方法为基础, 研究了腐蚀时间、浓度对绒面结构以及反射率的影响。此外, 还采用金属催化化学腐蚀法进行制绒, 选用氢氟酸和硝酸银作为腐蚀液。而且对两种制绒方法效果进行了对比。研究获得的最优绒面结构及反射率结果的实验条件为: 氢氟酸浓度4.6 mol/L、硝酸银浓度0.02 mol/L, 室温下反应90 min, 得到的平均反射率为8%, 远低于目前多晶硅片制绒生产标准。     

Annealing High Resistivity CdZnTe Wafers under Controlled Cd/Zn Partial Pressures

In order to improve the performances of CdZnTe 7-ray detector, it is key issue to get the crystal with high quality. Equilibrium partial pressures, pCd and pZn, over Cd1-xZnx melt were estimated based on thermodynamic relationship and then Cd0.9Zn0.1Te wafers were annealed under controlled Cd/Zn partial pressures provided by Cd1-xZnx alloy reservoir. The experimental results show that when CdZnTe wafers are annealed under the equilibrium partial pressures provided by Cd0.99Zn0.01 alloy reservoir for 5 days or more at 1073 K, the resistivity of the wafer can be raised by 6 times and IR transmittance raised by 10% or more, the size and density of Te precipitates are greatly reduced. Moreover, losing of Zn from the surface can be avoided, which Ieads to improvement of the Zn radial distribution. In addition, the relationship between the electrical performances of the wafers and different controlled pressures is also discussed.