4G系统的分步SDR检测

本文研究了空间频率分集MIMO-OFDM系统的DFE-SDR译码算法.提出了一种能充分利用空间分集、空间复用、频率复用增益,且能对抗时间选择性和频率选择性衰落的4G系统,结合判决反馈均衡(DFE)以及半定松弛检测(SDR)的优点,经过推导得到一种应用在该4G系统的DFE-SDR检测方法,该算法能同时得到较理想的系统性能和算法复杂度.系统仿真证明,该方法与普通DFE检测算法相比,误码率性能得到了较大提高,是一种有实用价值的译码算法,可以在4G移动通信系统中广泛应用.     

基于非线性系统的自适应神经网络均衡器特性分析*

针对非线性系统中的时变及参数动态变化引起的非线性失真及频谱衰落,提出了一种自适应神经网络均衡器结构与反向传播的遗传学习算法。均衡器前馈部分采用RBF神经网络,用于对非线性系统信道的逼近,而反馈部分采用基于递归最小二乘算法的判决反馈。实验验证了该判决反馈的自适应神经网络均衡器能有效消除非线性系统信道干扰,在误比特率方面改善了均衡器的性能。     

一种改进的基于MMSE准则信道缩短算法

在离散多音调制/正交频分复用系统中,采用接收端的时域均衡器来缩短信道的冲击响应长度,使得不大于循环前缀的长度,从而来消除ISI/ICI.很多学者给出不少计算最优缩短冲激响应均衡器抽头系数的算法,在这些算法中,要求时域均衡器的抽头长度必须小于或者等于目标冲激响应的记忆长度.文章提出了改进算法克服上述局限性,不仅可以用来计...     

级联式储能电池组均衡器及其自均衡策略

城市环境的特点决定了分布式城市微电网储能系统需要一种电路和控制方式均较为简单的电池均衡器。本文针对这一应用条件特点,提出了一种新颖的级联式电池组均衡器。该均衡器通过由开关管和均衡电感组成的简单均衡电路模块,即可与一个公共均衡电容相连,实现能量的无缝双向流动。同时均衡控制策略简单可靠,舍弃了传统方式中电池组单体的传感器外围电路和实现复杂算法的微处理器,极大地减小了体积并降低成本。在详细描述了工作原理和参数分析后,搭建的验证样机和电池组充电平台均有效验证了所提均衡器的正确性和有效性,因而具有实际工程应用推广价值。     

基于FPGA的盲均衡技术在油井工作状态检测系统中应用研究

无线油井监控系统是油田自动化系统的一个重要组成部分。由于受到带宽的限制，前端数据采集设备刖及检测系统的增加制约了通讯的质量和效率。本系统结合实际需要，将改进的盲均衡算法利用FPGA设计实现，并应用于该系统无线通讯链路中，从而降低了码间串扰及误码率。本论文论述了盲均衡器基本工作原理、GSA盲均衡器设计及其FPGA的实现过程。     

基于新型DNA遗传萤火虫优化的二维图像盲恢复算法研究

针对现有图像恢复算法的不足,提出了基于新型DNA遗传萤火虫优化的二维图像盲恢复算法。该算法首先对传统DNA遗传算法中交叉和变异操作进行改进,得到新型DNA遗传算法后与萤火虫算法相结合,提出了新型DNA遗传萤火虫优化算法;其次将新型DNA遗传萤火虫优化算法应用于二维图像盲恢复,得到的基于新型DNA遗传萤火虫优化的二维图像盲恢复算法具有良好全局搜索能力,优化了盲均衡器的初始权矩阵,模糊图像经过二维盲均衡器处理后,有效增强了图像质量,图像恢复良好。仿真结果验证了算法的有效性。     

π／4 DQPSK解调算法的研究与仿真

针对数字通信系统中符号间干扰（ISI）问题,提出了一种适用于π／4 DQPSK解调的自适应盲均衡和载波恢复算法。T／4 CMA盲均衡器利用接收信号的所有采样点进行迭代,解决了采样相位敏感的问题;改进的载波恢复算法简单易于实现,减小了接收机设计的复杂度和难度。仿真结果表明,这种算法复杂度小、性能好,具有一定的实用价值。     

改进型Buck/Boost锂电池均衡器研究

提出一种基于移相控制策略的改进型Buck/Boost均衡器,能实现各电池单元之间的能量流动,不仅解决了传统Buck/Boost均衡器均衡路径长、均衡效率低的问题,还减少了均衡器元件的数量。在研究该均衡器工作原理的基础上,重点推导了各电池单元的等效均衡电流(均衡路径)表达式。并搭建8节锂电池的仿真模型和实验样机对工作原理和控制策略进行验证。结果表明改进型Buck/Boost均衡器缩短了均衡路径,提高了均衡效率。     

超高符号率数字均衡技术研究与实现

符号传输速率超过500 M波特的超高速数据传输系统中,需利用均衡技术来减小信道失真对信号的影响。通过改进并行横向线性结构和流水乘加等方式,解决CMOS数字电路的时钟速率受限的问题,设计了传输速率超过500 M波特的数字均衡器。经实验测试,该均衡器可将高速数据传输系统的误码率性能提高2 dB。     

一种谐振倍压电路型串联超级电容电压均衡器

提出了一种新型谐振倍压电路型电压均衡器,较之传统主动型均衡器具有可控开关少,控制简单的优点.该均衡器中的所有MOSFET和二极管都能实现软开关,并且在开环配置的情况下能够控制均衡电流的大小.对电压均衡器的工作模式及其稳态特性进行了详细分析,建立了数学模型,给出了电路主要参数的设计方法;制作了电压均衡器样机,对10个串联超级电容进行了均衡实验.实验结果验证了分析的正确性与电压均衡器的均衡效果.     

Compact self‐constructing recurrent fuzzy neural network with decision feedback for quadrature amplitude modulation signaling systems

This paper proposes a novel adaptive decision feedback equalizer (DFE) based on compact self‐constructing recurrent fuzzy neural network (CSRFNN) for quadrature amplitude modulation systems. Without the prior knowledge of channel characteristics, a novel training scheme containing both compact self‐constructing learning (CSL) and real‐time recurrent learning algorithms is derived for the CSRFNN. The proposed CSL algorithm adopts two evaluation criteria to intelligently decide the number of fuzzy rules that are necessary. The real‐time recurrent learning is performed simultaneously with the CSL at each time instant to adjust DFE parameters. The proposed DFE is compared with several neural network‐based DFEs on a nonlinear complex‐valued channel. The results show that the CSRFNN DFE is superior to classical neural network DFEs in terms of symbol‐error rate, convergence speed, and time cost. Copyright © 2011 John Wiley & Sons, Ltd.     

An improved decision feedback equalization using a priori information

This paper addresses the exhaustive computational complexity of the maximum‐a‐posteriori equalizer and the inefficiency of the conventional decision feedback equalizer (DFE) algorithm in iterative equalization, especially when the higher‐level modulation is used with severely distorted Inter Symbol Interference channels. The new method proposed here improves the bit error rate (BER) performance by computing the extra metric r_n+1 using the feedback symbols from previous iteration and combining it with a priori information of the symbols. After each iteration, the hard‐detected symbols are saved in the memory as a priori data for next iteration. We verified the proposed algorithm for Binary Phase Shift Keying and 8‐phase shift keying modulation. The promising simulation results show that the BER performance given by the proposed low complexity DFE algorithm improved dramatically throughout the iterations when the conventional DFE has only insignificant improvement in the process of iterative equalization. Copyright © 2009 John Wiley & Sons, Ltd.     

Fractionally spaced blind equalization with low‐complexity concurrent constant modulus algorithm and soft decision‐directed scheme

The paper proposes a low‐complexity concurrent constant modulus algorithm (CMA) and soft decision‐directed (SDD) scheme for fractionally spaced blind equalization of high‐order quadrature amplitude modulation channels. We compare our proposed blind equalizer with the recently introduced state‐of‐art concurrent CMA and decision‐directed (DD) scheme. The proposed CMA+SDD blind equalizer is shown to have simpler computational complexity per weight update, faster convergence speed, and slightly improved steady‐state equalization performance, compared with the existing CMA+DD blind equalizer. Copyright © 2004 John Wiley & Sons, Ltd.     

A 6‐Gbps/lane receiver for a clock‐forwarded link in 65‐nm CMOS process

For a 6‐Gbps/lane clock‐forwarded link, a wireline receiver has been developed. The phases of the sampling clocks are aligned to the center of the input data eye by a clock and data recovery (CDR) circuit. In the CDR circuit, the sampling clock phases are rotated by a phase rotating phase locked loop (PLL). A three‐tap decision feedback equalizer (DFE) compensates for the loss of cable together with a continuous‐time linear equalizer (CTLE) to ensure sufficient eye opening for the CDR circuit to find the optimum sampling phase. The DFE coefficients are adaptively calculated based on the data and edge samples. Implemented in a 65‐nm CMOS process, the three‐lane 6‐Gbps/lane receiver for a clock‐forwarded link occupies 0.63 mm² including pads and consumes 288 mA from a 1.2‐V supply. Copyright © 2015 John Wiley & Sons, Ltd.     

Semi‐blind fast equalization of QAM channels using concurrent gradient‐Newton CMA and soft decision‐directed scheme

This contribution considers semi‐blind adaptive equalization for communication systems that employ high‐throughput quadrature amplitude modulation signalling. A minimum number of training symbols, approximately equal to the dimension of the equalizer, are first utilized to provide a rough initial least‐squares estimate of the equalizer's weight vector. A novel gradient‐Newton concurrent constant modulus algorithm and soft decision‐directed scheme are then applied to adapt the equalizer. The proposed semi‐blind adaptive algorithm is capable of converging fast and accurately to the optimal minimum mean‐square error equalization solution. Simulation results obtained demonstrate that the convergence speed of this semi‐blind adaptive algorithm is close to that of the training‐based recursive least‐square algorithm. Copyright © 2009 John Wiley & Sons, Ltd.     

32位快速乘法器设计

本文介绍了一种通过符号位扩展,可以分别完成32位有符号/无符号二进制数乘法的高性能乘法器设计。该乘法器采用高基Booth算法,简化部分积的符号扩展,通过采用较之常规Wallace树具有更规则和更简洁的连接复杂度的阵列结构以及一种新型超前进位加法器来进一步提高乘法器的运算速度。整个设计采用4级流水线结构,在FPGA上进行了验证,并成功地应用于时/频联合均衡器工作中。     

一种双超级电容倍压式串联蓄电池系统并行均衡器

传统电容式串行均衡器利用串联单体蓄电池间的电压差实现单体蓄电池间的串行均衡,由于串联单体蓄电池之间电压差小,该均衡器能量均衡效率低、均衡速度慢.为此,提出一种双超级电容倍压式串联蓄电池系统并行均衡器,该均衡器具有以下2种工作模式:多个单体蓄电池并行均衡放电的双超级电容并联储能、多个单体蓄电池并行均衡充电的双超级电容串联释能.所提出的并行均衡策略能够极大地提高均衡速度,同时双电容使电容均衡的储能能力加倍,且均衡性能不受单体蓄电池间电压差小的限制.详细介绍了均衡器结构、工作原理和控制策略.搭建了4个串联锂离子蓄电池均衡器实验平台并设计了样机进行实验,结果证明了所提均衡器的可行性与优越性.     

A 5‐Gbps USB3.0 transmitter and receiver linear equalizer

A USB3.0 compatible transmitter and the linear equalizer of the corresponding receiver are presented in this paper. The architecture and circuit design techniques used to meet the strict requirements of the overall link design are explored. Output voltage amplitude and de‐emphasis levels are programmable, whereas the output impedance is calibrated to 50Ω. A programmable receiver equalizer is also presented with its main purpose being to compensate for the channel losses; this is employed together with a DC offset compensation scheme. The 6.25‐GHz equalizer provides a 10 dB overall gain equalization and 5.5‐dB peaking at the maximum gain setting. Designed using a mature and well established 65 nm complementary metal oxide semiconductor process, the layout area is 400 µm × 210 µm for the transmitter core, and 140 µm × 70 µm for the equalizer core. The power consumption is 55 and 4 mW, respectively, from a 1.2 V supply at a data rate of 5 Gbps. The target application for such high‐speed blocks is to implement the critical part of the physical layer that defines the signaling technology of SuperSpeed USB3 PHY. However, identical iterations of the circuitry discussed can be used for similar high‐speed applications like the PCI express (PCIe). Copyright © 2014 John Wiley & Sons, Ltd.     

一种大规模蓄电池储能系统多目标并行有源能量均衡器

针对大规模锂离子蓄电池储能系统,提出具有两层均衡的模块化多目标并行有源能量均衡器.第一层均衡以蓄电池单元作为均衡目标,蓄电池单元内主控开关采用带死区互补导通控制,所有蓄电池单元可同时工作,均衡速度快且不受串联单体蓄电池数量的影响.第二层均衡由多组选通矩阵和一个具有能量双向且连续的有源均衡主电路组成,通过选通矩阵可并行实...