High temperature characteristics of bipolar mode power JFET operation

The high-temperature operating characteristics of high-voltage JFET devices operated in the bipolar mode are evaluated. Good forward blocking capability with no degradation in blocking gain is observed at up to 200°C. The on-resistance and gate turnoff time of the devices was found to double from 25°C to 200°C, and the current gain was found to decrease by 30 percent. Despite the increase in gate drive requirements with increasing temperature, these devices should still be attractive for high-speed power switching applications because their on-resistance per unit area is at least 10 time lower than that of the power MOSFET.     

High-voltage normally off GaN MOSFETs on sapphire substrates

Gallium nitride self-aligned MOSFETs were fabricated using low-pressure chemical vapor-deposited silicon dioxide as the gate dielectric and polysilicon as the gate material. Silicon was implanted into an unintentionally doped GaN layer using the polysilicon gate to define the source and drain regions, with implant activation at 1100/spl deg/C for 5 min in nitrogen. The GaN MOSFETs have a low gate leakage current of less than 50 pA for circular devices with W/L=800/128 /spl mu/m. Devices are normally off with a threshold voltage of +2.7 V and a field-effect mobility of 45 cm/sup 2//Vs at room temperature. The minimum on-resistance measured is 1.9 m/spl Omega//spl middot/cm/sup 2/ with a gate voltage of 34 V (W/L=800/2 /spl mu/m). High-voltage lateral devices had a breakdown voltage of 700 V with gate-drain spacing of 9 /spl mu/m (80 V//spl mu/m), showing the feasibility of self-aligned GaN MOSFETs for high-voltage integrated circuits.     

On-state modeling of power JFET structures in the bipolar mode

An analytical model for the on-state operation of the bipolar-mode power JFET is proposed. A closed-form solution in the low-voltage rnage of the output characteristics is obtained as a function of device parameters.The model shows that the hole-reflecting properties of the high-low drain transition are very important in order to achieve a lower on-state voltage drop. This allows us to explain the presence of an offset voltage in the output characteristics due to the recombination velocity effect at this transition.The effects of device parameters on the on-state operation, such as epi-thickness, lifetime and extent of heavy doping of source and drain are analyzed in detail and found in good agreement with experimental results.     

Physical modeling of bipolar mode JFET for CAE/CAD simulation

A circuit model of a power bipolar JFET, based on a specific formulation of its charge control model,is presented. The circuit obtained accurately describes both unipolar and bipolar modes of operation of the device, and is presented in a form suitable to be incorporated in circuit CAD (computer-aided design) simulators. The model was developed on a physical basis, and its parameters can in principle be directly computed from geometrical and physical characteristics of the device. The author also presents the implementation of the model into the version 4.02 of PSPICE obtained by modifying a device subroutine     

A quasi-one-dimensional analysis of vertical JFET devices operated in the bipolar mode

“Bipolar operation”, namely forward-basing the gate-source diode of a JFET, has been proposed in the literature as a means to reduce the on-state resistance of such devices.In this paper, the physics of bipolar operation of power JFET's is analysed in detail and closed-form solutions of its output characteristics are derived as a function of the device geometry and of physical parameters of the semiconductor.From that model, it turns out that the low value of the saturation voltage originates from the existence of an high-density electron-hole plasma that fills the space between source and drain. In the active region of the output characteristics, the control of the gate current the drain current is due to the possibility to control the level of majority-carrier injection from the source transition. The closed-form expression for the current gain allows to identify the structure parameters that affect it. It shown that, under suitable conditions, a substantial current amplification can be observed.The model has been found to be in good agreement with the results obtained on experimental devices.     

A JFET/bipolar eight-channel analog multiplexer

Describes the design and fabrication of the first of a new generation of analog multiplexers using the bipolar/ionimplanted JFET process. The switch configuration used is especially suited to this process, and consequently results in a moderate size bipolar IC. The design of the switch, aided by the process characteristics, produces a high-performance monolithic multiplexer which can withstand input signals of greater than the power supplies and does not require special care in handling. A high degree of optimization is attained in the design of the bias circuits, and this plays a major role in achieving high fabrication yield, and subsequently low production costs.     

Micropower monolithic filters using bipolar/JFET technology

Two approaches for the implementation of micropower monolithic filters operating from a 1.3-V supply were investigated. The filters were fabricated using a bipolar/JFET compatible technology. The characteristics and limitations of each of the filtering approaches are discussed and a comparison between the two, based on the performance of second-order bandpass filter realizations, is presented.     

A low-voltage micropower JFET/bipolar operational amplifier

A single cell supply (operable down to 1.2 V) micropower operational amplifier using compatible low pinchoff voltage JFET's (V/SUB p/=0.4 V) in conjunction with standard bipolar technology has been developed. The subvolt pinchoff JFET's have proved useful in the common-mode feedback-assisted biasing of a simple p-n-p input stage to permit single supply operation, the design of a low-voltage high-performance current mirror and a differential to single-ended converter. The amplifier exhibits excellent ac performance (unity gain slew rate=0.25 V//spl mu/s, unity gain bandwidth=850 kHz) with low power dissipation (245 /spl mu/W).     

Micropower monolithic filters using bipolar/JFET technology

Two approaches for the implementation of micropower monolithic filters operating from a 1.3-V supply were investigated. The filters were fabricated using a bipolar/JFET compatible technology. The characteristics and limitations of each of the filtering approaches are discussed and a comparison between the two, based on the performance of second-order bandpass filter realizations, is presented.     

A new 4H-SiC normally off lateral channel vertical JFET with extremely low power losses: source inserted double-gate structure with a supplementary highly doped region

A novel silicon carbide (SiC) normally off lateral channel vertical junction field-effect transistor (LC-VJFET), namely a source-inserted double-gate structure with a supplementary highly doped region (SHDR), was proposed for achieving extremely low power losses in high-power switching applications. The proposed architecture was based on the combination of an additional source electrode inserted between two adjacent surface gate electrodes and a unique SHDR in the vertical channel region. Two-dimensional numerical simulations for the static and resistive switching characteristics were performed to analyze and optimize the SiC LC-VJFET structures for this purpose. Based on the simulation results, the excellent performance of the proposed structure was compared with optimized conventional structures with regard to total power losses. Finally, the proposed structure showed about a 20% reduction in on-state loss (P/sub on/) compared to the conventional structures, due to the effective suppression of the JFET effect. Furthermore, the switching loss (P/sub sw/) of the proposed structure was found to be much lower than the results of the conventional structures, about a 75% /spl sim/ 95% reduction, by significantly reducing both input capacitance (C/sub iss/) and reverse transfer capacitance (C/sub rss/) of the device.     

Threshold voltages of normally off MESFET's

The threshold voltage of "normally off" Si-MESFET's for simple dc-coupled circuits is defined and computed with a two-dimensional device model, taking into account carrier velocity saturation and diffusion. The influence of the main parameters, gate length, conducting-layer thickness, and doping is investigated outside the range of Shockley's equations. A threshold voltage of a MESFET with a 1-µm gate lengthU_{T} = 0.2V±10 percent requires a conducting-layer thickness toleranced =0.15µm±3 percent.     

JFET optical detectors in the charge storage mode

The operation of a JFET as an optical detector in the charge storage mode is described and it is shown that due to the nondestructive readout, this device is particularly useful when high charge gains are required. On silicon, for example, it is calculated that small device structures should give charge gains > 10⁶. A method of resetting devices using the punchthrough effect is shown to reduce gain variations across an array and this principle is extended to a double punchthrough structure with a buried gate which can be read selectively. Measurements on lateral and longitudinal JFET structures verify these features and it is shown that they may be operated as two-terminal devices, a large voltage pulse being applied to the drain to reset and a small voltage to read.     

Performance analysis of a bipolar mode FET (BMFET) with normallyoff characteristics

The fabrication and characterization of a family of power bipolar-mode junction FETs (BMFETs) are reported. Blocking voltages up to 1000 V or currents up to 18 A (corresponding to 800 A/cm²) have been obtained. The experimental results are used to get an insight into the physics of BMFET operation and to extract the basic design criteria for these structures. The performance of the BMFET is compared with that of the bipolar transistor, showing it to be superior     

Self-aligned normally off GaAs MESFET using Sn-doped SiO2 glass

An improved normally-off GaAs MESFET was fabricated by employing Sn-doped SiO2 glass, which was used as an Sn-diffusant for making the N+ layer. An N+ layer with Rs=100$/? and Ns=3×1013 cm?2 was successfully obtained under 800°C, 20 min diffusion conditions. A new self-alignment technique, using doped-SiO2 film, provided a high performance normally-off GaAs FET.     

430-V 12.4-$hboxmOmegacdot hboxcm^2$Normally off 4H-SiC Lateral JFET

This letter reports the experimental demonstration of the first 4H-SiC normally off high-voltage lateral junction field-effect transistor. The design and fabrication of such a device have been investigated. The fabricated device has a vertical channel length of 1.8$muhboxm$created by tilted aluminum implantation on the sidewalls of deep trenches and a lateral drift-region length of 5$muhboxm$. Normally off operation$(V_ GS=hbox0 V)$with a blocking voltage$V_ br$of 430 V has been achieved with a specific on-resistance$R_ onhbox- sp$of 12.4$hboxmOmega cdot hboxcm^2$, which is the lowest specific on-resistance for 4H-SiC lateral power switches reported to date, resulting in a$V_ br^2/R_ onhbox- sp$value of 15$hboxMW/cm^2$. This is among the best$V_ br^2/R_ onhbox- sp$figure-of-merit reported to date for 4H-SiC lateral high-voltage devices.     

A normally off GaN n-MOSFET with Schottky-barrier source and drain on a Si-auto-doped p-GaN/Si

We have fabricated an enhancement-mode n-channel Schottky-barrier-MOSFET (SB-MOSFET) for the first time on a high mobility p-type GaN film grown on silicon substrate. The metal contacts were formed by depositing Al for source/drain contact and Au for gate contact, respectively. Fabricated SB-MOSFET exhibited a threshold voltage of 1.65 V, and a maximum transconductance(g/sub m/) of 1.6 mS/mm at V/sub DS/=5V, which belongs to one of the highest value in GaN MOSFET. The maximum drain current was higher than 3 mA/mm and the off-state drain current was as low as 3 nA/mm.     

JFET/SOS devices. I. Transistor characteristics and modelingresults

A process for fabricating n-channel junction field-effect transistors (JFET) on silicon-on-sapphire (SOS) wafers has been developed. Both enhancement-mode and depletion-mode transistors were fabricated, and their characteristics were measured and are discussed. All dopants were ion implanted. A number of calculational tools, including SUPREME-II, were used to estimate the junction depths and the mode of device operation. Calculations were also performed using PISCES-II, a device-modeling program that predicts operating characteristics. The mobilities used in these calculations were reduced from bulk silicon values to account for the degraded mobility of the SOS material. The mobility of the SOS material was measured using capacitance-voltage and conductance-voltage techniques on a device with a long gate. A decrease in mobility with decreasing temperature is deduced from device behavior at low temperatures     

Fully ion-implanted InP JFET with buried p-layer

Implementation of a buried p-layer in a fully ion implanted InP JFET is discussed. Using Be coimplanted with Si, a sharp channel profile is obtained. The saturation current has been reduced, and the pinch-off characteristic has been improved, with a slight decrease in transconductance and cutoff frequency. The equivalent circuits for the JFET with and without the buried p-layer are compared     

Investigation of MOSFET operation in bipolar mode

The work is concerned with the properties of conventional MOSFET in bipolar mode of operation. It is shown that the base current can provide useful information about interface trap density at the Si–SiO₂ interface. The new device characteristics are found promising for use in low-voltage low-power logic circuits.     

A monolithic field emitter array with a JFET

This paper proposes a novel structure of the conical Si field emitters monolithically incorporating a vertical-type junction field effect transistor (JFET) and demonstrates the emission control in field emission from the emitters. The proposal has many attractive advantages in the display application and reliable fabrication, because the structure needs neither additional area for the JFET nor additional process except ion implantation. The experimental results of the emitters show excellent controllability and stability in the emission current