软核嵌入处理器MicroBlaze

MicroBlaze是Xilinx的软核嵌入处理器,使用开发工具ISE/XPS和相关IP-Core,利用FPGA内的通用资源,用户可以参数化地设计CPU、总线、接口等组件,在FPGA内部实现一个完整的高性能处理器,且支持多核处理器,同时可在XPS中完成操作系统配置和应用软件的设计调试。软核嵌入处理器广泛适用于各个领域。文章介绍软核嵌入处理器MicroBlaze及其设计方法。     

VGA汉字显示的FPGA设计与实现

VGA是显示器接口的一种工业标准.以往大多采用通用处理器控制VGA接口来实现汉字及其它信息的显示,但是以通用处理器为核心的体系结构不易修改,体积偏大,不适合小型便携式设备的设计.由于FPGA具有可重构、体积小等优势,采用FPGA来控制VGA的汉字显示.依据VGA的显示原理,提出了一种基于Xilinx Spartan-3的彩条信号显示方法,并利用FPGA内部的块RAM,实现了VGA的汉字显示.实验结果表明,由FPGA来控制汉字的显示,达到了预期的效果,克服了通用处理器的弊端.     

基于嵌入式SOPC的ABS控制器设计

SOPC作为一种特殊的嵌入式微处理器,它融合了SOC和FPGA各自的优点,并具备软硬件在系统可编程、可裁减、可扩充、可升级等功能。利用EDK工具在FPGA上设计了以NIOSII为处理器的嵌入式ABS控制器,说明了控制器的硬件和软件设计,并介绍SOPC嵌入式系统软硬件协同开发的设计方法和流程。     

基于PowerPC和FPGA的小型无人直升机飞行控制计算机系统设计

针对小型无人直升机体积小、负载轻和飞行控制计算量大、实时性要求高的特点,提出了一种基于PowerPC和FPGA主从处理器结构的飞行控制计算机系统设计方法,该设计主处理器采用MPC8280通用嵌入式双核处理器,从处理器采用XC3S400FPGA处理器;PowerPC多任务软件基于VxWorks实时操作系统,FPGA软件采用多进程结构;相比传统的飞行控制计算机系统,基于PowerPC和FPGA主从处理器结构的飞行控制计算机系统具有结构紧凑、功耗低、处理能力强、实时性好和资源利用率高的特点;采用基于Pow-erPC和FPGA的飞行控制计算机系统的小型无人直升机实现了自主飞行,验证了该飞行控制计算机系统设计的有效性和合理性。     

基于NiosII的SOPC多处理器系统设计方法

详细地阐述基于NiosII和FPGA的多处理器系统的实现机制,讨论利用硬件互斥核实现多处理器资源共享的方法,并给出硬件设计的具体步骤以及软件设计、调试方法和关键技术;利用Altera公司提供的QuartusII、SOPC Builder和NiosII IDE等开发工具,通过一个3处理器系统设计实例,验证了设计方法的正确性,实现了3处理器对存储器资源的共享。     

FPGA中嵌入最小资源配置的微处理器的实现方法

针对在FPGA内集成嵌入式处理器消耗资源大的特点,提出了在FPGA内嵌入最小资源配置软核的新方法,减少了在FPGA内嵌入处理器内核所占用的资源,降低了损耗功率,扩展了可以应用软核的FPGA类型。经过仿真和下载测试,此方法具有配置灵活、节省资源的优点。     

基于SOPC的CAN_RS232接口转换器设计

使用Altera公司的Cyclone Ⅱ系列FPGA,利用SOPC平台下的NIOS Ⅱ处理器,实现了CAN 2.0和RS232的接口转换器的设计,为实现片上集成其它协议接口转换器的设计奠定了基础。     

浅谈基于WinCE环境下的ARM+FPGA系统

ARM嵌入式单片机和FPGA逻辑电路组成的系统平台是实现仪器仪表便携式、智能化发展的重要方法。系统设计的核心为ARM对FPGA进行管理控制。通过分析ARM的外围总线和与GPIO研究,设计出FPGA通过数据总线交换数据、GPIO完成状态传递的直接连接方式,有效利用了ARM处理器的地址资源,简化了接口电路;通过研究Windows CE系统驱动程序原理和编程,设计了简化的Windows CE对数据总线和GPIO驱动过程,节省了系统资源,完成了ARM+FPGA系统的多通道数据采集系统应用开发。     

基于NiosⅡ的SOPC多处理器系统设计方法

详细地阐述基于NiosⅡ和FPGA的多处理器系统的实现机制,讨论利用硬件互斥核实现多处理器资源共享的方法,并给出硬件设计的具体步骤以及软件设计、调试方法和关键技术;利用Altera公司提供的QuartusⅡ、SOPC Builder和NiosⅡ IDE等开发工具,通过一个3处理器系统设计实例,验证了设计方法的正确性,实现了3处理器对存储器资源的共享.     

面向异构多核处理器的FPGA验证

随着处理器架构的发展,高性能异构多核处理器不断涌现.由于高性能异构多核处理器的设计十分复杂,为了降低设计风险,缩短验证周期,提前进行软件开发,复现硅后问题等,通常需要搭建现场可编程门阵列(field programmable gate array,FPGA)的原型验证平台,并基于FPGA平台开展种类繁多,功能各异的软硬协同验证和调试工作,提出的基于同构FPGA平台对异构多核高性能处理器的FPGA调试、验证方法,有效地利用了异构多核处理器的架构特征,同构FPGA的对称特点,以层次化的方法自顶向下划分FPGA,自底向上构建FPGA平台.结合差速桥、自适应延迟调节、内嵌的虚拟逻辑分析仪(virtual logic analyzer,VLA)等技术可快速完成FPGA平台的点亮(bring-up)和部署.所提出的多核互补,核间替换模拟的调试SHELL等方法可以快速完整地对目标高性能异构多核处理器进行FPGA验证.通过该FPGA原型验证平台,成功地完成了硅前验证,软硬件协同开发和测试,硅后问题复现工作,并为下一代处理器架构设计提供了快速的硬件平台.     

A digital signal processor with IEEE floating-point arithmetic

A overview is given of Motorola's DSP96002, a digital signal processor that implements IEEE-standard floating-point arithmetic. It is designed for graphics, image processing, spectral analysis and scientific computing applications. Performance peaks at 40.5 Mflops (million floating-point operations per second) and 13.5 MIPS (million instructions per second) and 18 Mflops on assembly-language benchmarks. The DSP is software-compatible with the fixed-point 56000/1 family architecture and instruction set. The 96002 achieves compatibility with other processors and databases, higher mathematical accuracy, and better error handling than implementations that do not conform to the IEEE standard. The 96002's on-chip memories, dual-bus architecture, and transparent DMA are suitable for multiprocessor systems in which many 96002s connect with minimum external components. These features result in a smaller-footprint, lower-cost system than other microprocessors or data-path chips. On-chip support for the fast access modes of external memories achieves near-SRAM (static random-access memory) performance with high-density DRAM/VRAM (dynamic RAM/virtual RAM) devices. An on-chip circuit emulation controller provides full access and control of the machine state for system debugging. A variety of software and hardware development tools support the 96002     

高吞吐率浮点FFT处理器的FPGA实现研究

受浮点操作的长流水线延迟及FPGA片上RAM端口数目的限制,传统H可处理器的吞吐率通常只能达到每周期输出一个复数结果。本文用FPGA设计并实现了一种高吞吐率的IEEE754标准单精度浮点FFT处理器,通过改进蝶形计算单元的结构并重新组织FPGA片上RAM的访问,该处理器每周期平均可输出约两个复数计算结果,吞吐率约为传统FFT处理器吞吐率的两倍。对于1024点FFT变换,可在（512＋10）＊10=5220周期内完成。     

基于双口RAM的ARM与DSP通信接口设计

提出了一种基于双口RAM的ARM与DSP通信接口的设计方案。该接口以ARM为主处理器、DSP为协处理器,ARM通过在Linux系统上建立的DSP任务管理线程实现DSP任务的管理和调度工作,DSP完成ARM下发的数据计算和处理工作,两者通过双口RAM交换数据。实际应用表明,该接口充分利用了两个处理器的功能特性,数据传输速度快,适用于ARM与DSP间需要进行大量数据交换的场合。     

Finding Euler tours in parallel

The problem of finding Euler tours in directed and undirected Euler graphs is considered. O(log |V|) time algorithms are given using a linear number of processors on a concurrent-read concurrent-write parallel RAM.     

Parallel algorithms for shortest path problems in polygons

Given ann-vertex simple polygon we address the following problems: (i) find the shortest path between two pointss andd insideP, and (ii) compute the shortestpath tree between a single points and each vertex ofP (which implicitly represents all the shortest paths). We show how to solve the first problem inO(logn) time usingO(n) processors, and the more general second problem inO(log² n) time usingO(n) processors, and the more general second problem inO(log² n) time usingO(n) processors for any simple polygonP. We assume the CREW RAM shared memory model of computation in which concurrent reads are allowed, but no two processors should attempt to simultaneously write in the same memory location. The algorithms are based on the divide-and-conquer paradigm and are quite different from the known sequential algorithmsResearch supported by the Faculty of Graduate Studies and Research (McGill University) grant 276-07     

Design of servo control systems with quadratic optimal control and observed-state feedback control for mems-based storage device

MicroElectroMechanical Systems (MEMS) are very tiny mechanical devices (on the order of 10–1000 μm) such as sensors, valves, gears, and actuators fabricated on the surface of silicon wafers. These microstructures are created using the same photolithographic processes used in manufacturing other semiconductor devices. Therefore, it is possible to integrate several semiconductor devices (e.g., processors and memory) directly with the nonvolatile storage device. The hierarchy gap between RAM and disks is creating a performance bottleneck in computer systems. MEMS-based storage can improve computer systems performance and fill significant assess time, power dissipation, mass, and cost gaps between RAM and disks. MEMS-based storage is very young technology so there are many possibilities for designing, modeling, and performance. We focus on the system-level performance characteristics. This paper explores control systems with quadratic optimal control and observed-state feedback control for MEMS-based storage device. A closed-loop control system actively damps the oscillations using the actuators and reduces seek time by reducing settling time. Optimizations of the control loop can provide better I/O performance. Accurate model of system components is important for analysis of system performance because these devices do not exist yet. At the beginning of development, our control models may provide reasonable feedback and design trade-offs to both hardware and software designers.     

多核DSP和FPGA之间的高速SRIO通信

在高速采样系统中,大量数据需要实时传输到处理器.尤其是系统中存在多个处理器协同工作,就需要高速的总线来交换数据.SRIO总线由于存在连线少、传输速度高等优点,使用较为广泛.本文介绍了多核DSP和FPGA之间使用SRIO进行数据交换的软硬件设计方法,在不同数据需求下,介绍了FPGA将数据直接传输到DSP的DDR3、片内RAM或者多核的共享RAM中.本文研制了硬件系统,给出了各种方式的软件操作方法和实际硬件平台验证,SRIO传输速率达到4 Gbps.     

Parallel simulation of three-dimensional complex flows: Application to two-phase compressible flows and turbulent wakes

In this paper, we present parallel simulations of three-dimensional complex flows obtained on an ORIGIN 3800 computer and on homogeneous and heterogeneous (processors of different speeds and RAM) computational grids. The solver under consideration, which is representative of modern numerics used in industrial computational fluid dynamics (CFD) software, is based on a mixed element-volume method on unstructured tedrahedrisations. The parallelisation strategy combines mesh partitioning techniques, a message-passing programming model and an additive Schwarz algorithm. The parallelisation performances are analysed on a two-phase compressible flow and a turbulent flow past a square cylinder.     

Optimal communication algorithms for hypercubes

We consider the following basic communication problems in a hypercube network of processors: the problem of a single processor sending a different packet to each of the other processors, the problem of simultaneous broadcast of the same packet from every processor to all other processors, and the problem of simultaneous exchange of different packets between every pair of processors. The algorithms proposed for these problems are optimal in terms of execution time and communication resource requirements; that is, they require the minimum possible number of time steps and packet transmissions. In contrast, algorithms in the literature are optimal only within an additive or multiplicative factor.     

Robust alternative minimization for matrix completion

Recently, much attention has been drawn to the problem of matrix completion, which arises in a number of fields, including computer vision, pattern recognition, sensor network, and recommendation systems. This paper proposes a novel algorithm, named robust alternative minimization (RAM), which is based on the constraint of low rank to complete an unknown matrix. The proposed RAM algorithm can effectively reduce the relative reconstruction error of the recovered matrix. It is numerically easier to minimize the objective function and more stable for large-scale matrix completion compared with other existing methods. It is robust and efficient for low-rank matrix completion, and the convergence of the RAM algorithm is also established. Numerical results showed that both the recovery accuracy and running time of the RAM algorithm are competitive with other reported methods. Moreover, the applications of the RAM algorithm to low-rank image recovery demonstrated that it achieves satisfactory performance.