Hydrogenated amorphous silicon thin-film transistor on plastic with an organic gate insulator

We developed a high-performance, hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) on plastic substrate using an organic gate insulator. The TFT with a silicon-nitride (SiN/sub x/) gate insulator exhibited a field-effect mobility of 0.3 cm/sup 2//Vs and a threshold voltage of 5 V. On the other hand, an a-Si:H TFT with an organic gate insulator of BCB (benzocyclobutene) has a field-effect mobility of 0.4 cm/sup 2//Vs and a threshold voltage of 0.7 V. The leakage currents through the gate insulator of an a-Si:H TFT with an organic gate insulator is about two orders of magnitude lower than that of an a-Si:H TFT with a SiN/sub x/ gate insulator.     

A novel coplanar amorphous silicon thin-film transistor usingsilicide layers

A novel, coplanar, hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) was fabricated by depositing a triple layer consisting of a-Si:H, silicon-nitride, and a-Si:H. After patterning the top two layers in the gate stack, the devices were doped and a 30 nm Ni layer was deposited. The devices were then annealed for 1 h at 230°C to form self-aligned, low resistive Ni-silicide. The fabricated coplanar a-Si:H TFT exhibits a field effect mobility of 0.6 cm²/Vs, a threshold voltage of 2 V, a subthreshold slope of 0.4 V/dec, and an on/off current ratio of ~10⁷     

Hydrogen dilution effect on the properties of coplanar amorphoussilicon thin-film transistors fabricated by inductively-coupled plasmaCVD

The electrical and optical properties of the hydrogenated amorphous silicon (a-Si:H) films deposited by inductively-coupled plasma (ICP) chemical vapor deposition (CVD) with a variation of H₂ flow rate have been studied. The photosensitivity of a-Si:H is ~10⁷ when the H₂/SiH₄ ratio is between 3 and 8. With increasing H₂/SiH₄, the SiH₂ mode infrared absorption has a minimum at a H₂/SiH₄ ratio of 8. Coplanar a-Si:H thin-film transistors (TFT's) were fabricated using a triple layer of thin a-Si:H, silicon-nitride, and a-Si:H deposited by ICP-CVD using ion doping and low resistivity Ni silicide. After patterning the thin a-Si:H/silicon-nitride layers on the channel region, the gate and source/drain regions were ion-doped and then heated at 230°C to form Ni silicide layers. The low resistive Ni silicide formed on the a-Si:H reduces the offset length between gate and source/drain, leads to a coplanar a-Si:H TFT. The TFT exhibited a field effect mobility of 0.6 cm²/Vs and a threshold voltage of 2.3 V at the H₂/SiH₄ ratio of 8. The effect of H₂ dilution in SiH₄ on the coplanar a-Si:H TFT performance has been investigated. We found that the performance of the TFT is the best when the SiH₂ mode density in a-Si:H is the minimum. The coplanar TFT is very suitable for large-area, high density TFT displays because of its low parasitic capacitance between gate and source/drain contacts     

A polycrystalline silicon thin-film transistor with a thinamorphous buffer

We have developed a novel, low off-state leakage current polycrystalline silicon (poly-Si) thin-film transistor (TFT) by introducing a very thin hydrogenated amorphous silicon (a-Si:H) buffer on the poly-Si active layer. The a-Si:H buffer is formed on the whole poly-Si and thus no additional mask step is needed. With an a-Si:H buffer on poly-Si, the off-state leakage current of a coplanar TFT is remarkably reduced, while the reduction of the on-state current is relatively small. The poly-Si TFT with an a-Si:H buffer exhibited a field effect mobility of 12 cm²/Vs and an off-state leakage current of 3 fA/μm at the drain voltage of 1 V and the gate voltage of -5 V     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V     

Copper gate hydrogenated amorphous silicon TFT with thin bufferlayers

We demonstrated a Cu gate hydrogenated amorphous silicon thin-film transistor (TFT) with buffer layers. We introduced an AlN/Cu/Al₂ O₃ multilayer for a gate of an a-Si:H TFT. The Al₂ O₃ improves the adhesion to glass substrate and AlN protect the Cu diffusion to the TFT and plasma damage to Cu during plasma enhanced chemical vapor deposition of silicon-nitride. An a-Si:H TFT with a Cu gate exhibited a field effect mobility of 1.18 cm² V/s, a gate voltage swing of 0.87 V/dec., and a threshold voltage of 3.5 V     

Gated-four-probe a-Si:H TFT structure: a new technique to measurethe intrinsic performance of a-Si:H TFT

In this letter, a new technique based on gated-four-probe hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) structure is proposed. This new technique allows the determination of the intrinsic performance of a-Si:H TFT without any influence from source/drain series resistances. In this method, two probes within a conventional a-Si:H TFT are used to measure the voltage difference within a channel. By correlating this voltage difference with the drain-source current induced by applied gate bias, the a-Si:H TFT intrinsic performance, such as mobility, threshold voltage, and field-effect conductance activation energy, can be accurately determined without any influence from source/drain series resistances     

a—SiNx：H薄膜对a—Si：H TFT阈值电压的影响

介绍了测定a－Si：HTFT闽值电压的实验方法。重点研究了改变a－SiNx：H薄膜淀积时反应气体NH3／SiH4流速比以及a－SiNx:H膜厚对a－Si：HTFT阈值电压的影响。对实验结果进行了分析。实验结果表明：a－Si:HTFT的阈值电压随a－SiNx：H的膜厚增加而增大；增大X－SiNx：H薄膜淀积时NH3／SiH4气体流速比，可明显减小a-Si:HTFT的阈值电压。     

Hydrogenated amorphous silicon thin film transistor fabricated onplasma treated silicon nitride

We have demonstrated that the performance of the inverted staggered, hydrogenated amorphous silicon thin film transistor (a-Si:H TFT) is improved by a He, H₂, NH₃ or N₂ plasma treatment for a short time on the surface of silicon nitride (SiN _x) before a-Si:H deposition. With increasing plasma exposure time, the field-effect mobility increase at first and then decrease, but the threshold voltage changes little. The a-Si:H TFT with a 6-min N₂ plasma treatment on SiN_x exhibited a field effect mobility of 1.37 cm²/Vs, a threshold voltage of 4.2 V and a subthreshold slope of 0.34 V/dec. It is found that surface roughness of SiN_x is decreased and N concentration in the SiN _x at the surface region decreases using the plasma treatment     

Planarized copper gate hydrogenated amorphous-silicon thin-filmtransistors for AM-LCDs

We report the first fabrication of inverted-staggered back-channel-etch hydrogenated amorphous-silicon (a-Si:H) thin-film transistors (TFTs) with a planarized Cu gate electrode. The Cu gate-planarized (GP) a-Si:H TFTs, incorporating benzocyclobutene and a-SiN_x:H as a double-layer gate insulator, had a field-effect mobility of 0.75 cm²/V-s, a threshold voltage of 4.92 V, and a subthreshold swing (S) of 0.48 V/dec. These results demonstrate that the GP-TFTs can have an electrical performance comparable with the conventional TFTs without gate planarization. Thus, the gate planarization technology is suitable for application in large-area and high-resolution active-matrix liquid-crystal displays     

Static characteristics of a-Si:H dual-gate TFTs

This paper examines the effect of the top gate on the static characteristics of dual-gate hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs). Both forward and reverse regimes of operation are considered. The top gate has a distinct effect on the threshold voltage, subthreshold slope, drive-current capability, and the leakage current of the TFT. In particular, the threshold voltage is found to linearly decrease with increasing top-gate bias. Specific bias configurations of the dual gate TFT critical to vertical integration of on-pixel electronics for imaging and display applications are also presented.     

High field-effect-mobility a-Si:H TFT based on high deposition-ratePECVD materials

The hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFT's) having a field-effect mobility of 1.45 ±0.05 cm² /V·s and threshold voltage of 2.0±0.2 V have been fabricated from the high deposition-rate plasma-enhanced chemical vapor deposited (PECVD) materials. For this TFT, the deposition rates of a-Si:H and N-rich hydrogenated amorphous silicon nitride (a-SiN_1.5 :H) are about 50 and 190 nm/min, respectively. The TFT has a very high ON/OFF-current ratio (of more than 10⁷), sharp subthreshold slope (0.3±0.03 V/decade), and very low source-drain current activation energy (50±5 meV). All these parameters are consistent with a high mobility value obtained for our a-Si:H TFT structures. To our best knowledge, this is the highest field-effect mobility ever reported for an a-Si:H TFT fabricated from high deposition-rate PECVD materials     

Dependence of Threshold Voltage of a-Si:H TFT on a-SiNx:H Film^①

The relation between threshold voltage for hydrogenated amorphous silicon thin film transistors(a-Si:HTFTs)and deposition conditions for hydrogenated amorphous silicon nitride(a-SiNx:H)films is investigated.It is observed that the threshold voltage,Vth,of a-Si:HTFT increases with the increase of the thickness of a-SiNx:H film,and the threshold voltage is reduced apparently with the increase of NH3/SiH4 gas flow rate ratio.     

Dependence of Threshold Voltage of a-Si:H TFT on a-SiN_x:H Film

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AMOLED电流镜像像素电路的稳定性分析

a—Si：HTFT在长时间施加直流栅偏压下将导致晶体管闽值电压漂移,造成OLED的发光亮度下降,影响其使用寿命。而多管的像素电路设计可以补偿或消除阂值电压的漂移。本文分析了电流控制电流镜像像素电路的工作原理。结合a—Si：HTFT阈值漂移模型仿真了电路在长时间工作下阈值漂移对驱动电流稳定性的影响,并提出了相应的解决办法。研究结果表明合理的像素电路设计可以有效改善驱动电流的稳定性。     

薄有源层非晶硅薄膜晶体管特性的研究

本文研究了薄ａ－Ｓｉ：Ｈ有源层结构的ａ－Ｓｉ：Ｈ ＴＦＴ的特性，实验结果表明，当ａ－Ｓｉ：Ｈ层的厚度小于一个临界值时，ａ－Ｓｉ：Ｈ厚度的变化对ａ－Ｓｉ：Ｈ ＴＦＴ静态特性的影响明显增大，本文中详细分析了有源层背面空间电荷层对ａ－Ｓｉ：Ｈ ＴＦＴ特性的影响，从表面有效空间电荷层的概念出发，从理论上分析了有源层厚度与阈值电压的关系，计算的临界有源层厚度为１３０ｎｍ，这与实验结果基本一致。     

High field effect mobility deuterated amorphous silicon thin-filmtransistors based on the substitution of hydrogen with deuterium

The characteristics of amorphous silicon hydrogen and deuterium thin-film transistors (a-Si:H/a-Si:D TFT) were studied. The deuterated and hydrogenated amorphous silicon channels were prepared by first annealing the as-deposited a-Si:H layer at 550°C in N₂ environment to expel all the hydrogen atoms out of the films, then the D ₂ or H₂ plasma were applied to treat the amorphous silicon layers. The field effect mobility of the conventional hydrogen TFT is usually smaller than 1 cm²/V-s. It was found that substitution of hydrogen with deuterium improved the field effect mobility of the TFT. The maximum field effect mobility of a-Si:D TFT obtained from the saturation region was 1.77 cm²/V-s     

新型SiO2栅介质非晶硅薄膜晶体管室温红外探测器

对用作室温红外探测敏感单元的非晶硅薄膜晶体管进行了研究，提出了一种新型SiO2栅介质非晶硅薄膜晶体管室温红外探测器。该探测器的基本工作机理与传统的SiNx栅介质薄膜晶体管相类似，但在器件性能方面不仅具有较高的响应度，而且具有更好的温度稳定性；在制作工艺方面具有更高的工艺重复性和栅介质淀积的均匀性。     

新型SiO2栅介质非晶硅薄膜晶体管室温红外探测器

对用作室温红外探测敏感单元的非晶硅薄膜晶体管进行了研究,提出了一种新型SiO2栅介质非晶硅薄膜晶体管室温红外探测器。该探测器的基本工作机理与传统的SiN2栅介质薄膜晶体管相类似,但在器件性能方面不仅具有较高的响应度,而且具有更好的温度稳定性;在制作工艺方面具有更高的工艺重复性和栅介质淀积的均匀性。     

Self-aligned amorphous-silicon TFTs on clear plastic substrates

We fabricated the first bottom-gate amorphous silicon (a-Si:H) thin-film transistors (TFTs) on a clear plastic substrate with source and drain self-aligned to the gate. The top source and drain are self-aligned to the bottom gate by backside exposure photolithography through the plastic substrate and the TFT tri-layer. The a-Si:H channel in the tri-layer is made only 30 nm thick to ensure high optical transparency at the exposure wavelength of 405 nm. The TFTs have a threshold voltage of /spl sim/3 V, subthreshold slope of /spl sim/0.5 V/dec, linear mobility of /spl sim/1 cm/sup 2/V/sup -1/ s/sup -1/, saturation mobility of /spl sim/0.8 cm/sup 2/V/sup -1/s/sup -1/, and on/off current ratio of >10/sup 6/. These results show that self-alignment by backside exposure provides a solution to the fundamental challenge of making electronics on plastics: overlay misalignment.