Noise in digital dynamic CMOS circuits

Dynamic logic is an attractive circuit technique giving reduced area and increased speed for CMOS circuits. Static logic has a major advantage: its superior noise margins. To be able to choose between a static and a dynamic implementation of a design, we need to know the requirements for dynamic logic. Here we try to identify possible errors, estimate the limits and discuss some possible solutions when considering noise in dynamic circuits     

On-chip sampling in CMOS integrated circuits

This paper presents a technique for precise crosstalk delay measurement based on on-chip sampling. Results obtained on a test chip fabricated in 0.7-μm CMOS technology exhibit a 100% delay increase in a long coupled line configuration     

Process technology for radiation-hardened CMOS integrated circuits

A process technology for radiation-hardened CMOS integrated circuits has been defined. Process parameters for the SiO/SUB 2/ gate insulator have been optimized for radiation hardness, and circuit latch-up due to parasitic p-n-p-n structures on the integrated circuits has been prevented by gold-doping the silicon substrate to reduce carrier lifetime. The device yields for the hardened technology have been evaluated and the reliability has been characterized by bias-temperature life testing.     

A CMOS integrated three-axis accelerometer fabricated withcommercial submicrometer CMOS technology and bulk-micromachining

In this paper, a bulk-micromachined three-axis accelerometer fabricated with commercial submicrometer CMOS wafers has been developed for low-cost realization of smart accelerometers and improvement of device performance. The signal processing circuits for three-axis detection were formed using a commercial 0.8-μm CMOS technology. After that, micromachining processes were performed to the complete CMOS wafers to form accelerometer structures. The important technologies to separate micromachining processes from the CMOS process are wafer thickness control after CMOS fabrication and backside polishing with chemical spin etching. Accelerometers with 3×3 mm² and 6×6 mm² die size were fabricated with the developed fabrication technology. As a result of device evaluation, 2.0 mg_rms resolution of Z-axis acceleration, and 10.8 mg_rms resolution of X and Y-axis acceleration were obtained by the accelerometers with 6×6 mm² die size. Comparing for the same die area, the 6×6 mm² size accelerometer showed about 21.3 times higher resolution of Z-axis acceleration and 37.8 times higher resolution of X, Y-axis acceleration as compared to our previous three-axis accelerometer fabricated with 5.0-μm CMOS technology. Temperature dependence and reliability for repetitive vibration loads were also evaluated. Through these evaluations, basic performance of the CMOS integrated three-axis accelerometer has been confirmed     

Noise margins in digital integrated circuits

Many integrated circuit logic gates, especially the complete monolithic type, operate at very low signal levels. For this reason, the sensitivity of such circuits to noise is very important. The general definition of noise margin leads to a discussion of dc and ac noise margins for a simple inverting gate, and specific test data of an RCTL gate. A standard definition for input ac noise margin for a simple logic gate is proposed.     

Fabrication of submicrometer CMOS circuits using a new trilayer photolithographic process

CMOS circuits with submicrometer gate lengths were fabricated using a new trilayer photolithographic process. A transparent and electrically conductive film of indium tin oxide was used as the middle layer in the trilayer resist with unique advantages. The shortest on-mask gate length for which CMOS circuits were successfully fabricated was 0.75 µm. The corresponding effective channel lengths for NMOS and PMOS were on the order of 0.55 and 0.4 µm, respectively. A propagation delay of 106 ps at 5 V was achieved for CMOS ring oscillators fabricated using this process technology.     

Analysis of crosstalk interference in CMOS integrated circuits

The authors show how crosstalk coupling between transmission lines inside CMOS integrated circuits can provoke faulty behavior by affecting the propagation delay of the logic and analog cells. A simplified model for the evaluation of parasitic capacitive coupling effects is proposed, and the influence of crosstalk on the behavior of basic functions such as logic gates, latches, RAM memory, and analog-to-digital converters is evaluated     

Stacked CMOS circuits integrated in laser-recrystallized silicon films

Laser-recrystallized poly-silicon films are used as a substrate for the integration of MOS transistors and CMOS circuits. Ring oscillators and frequency divider circuits up to 100 transistors operate well with a yield of about 80%. For the integration of stacked CMOS circuits already tested bulk structures are covered with a dielectric layer and a poly-silicon film which is recrystallized at low temperature. The SOI integration technique, with a maximum temperature treatment of 960°C, is employed to manufacture the second active area as a 3-D technology. After the integration process SOI and bulk CMOS transistors operate independently at two different active levels.     

RTD/CMOS nanoelectronic circuits: thin-film InP-based resonanttunneling diodes integrated with CMOS circuits

The combination of resonant tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) silicon circuitry can offer substantial improvement in speed, power dissipation, and circuit complexity over CMOS-only circuits. We demonstrate the first integrated resonant tunneling CMOS circuit, a clocked 1-bit comparator with a device count of six, compared with 21 in a comparable all-CMOS design. A hybrid integration process is developed for InP-based RTDs which are transferred and bonded to CMOS chips. The prototype comparator shows sensitivity in excess of 10⁶ VIA, and achieves error-free performance in functionality testing. An optimized integration process, under development, can yield high-speed, low power circuits by lowering the high parasitic capacitance associated with the prototype circuit     

Modelling of coupled interconnect lines for integrated circuits

A coupled interconnect model is developed using even mode and odd mode capacitance analysis. Signal coupling is presented in terms of interconnect width, substrate thickness, interconnect line spacing, and frequency. Picosecond photoconductor based measurements of coupled transmission lines on the integrated circuit support the even and odd mode signal transmission simulation results. SPICE circuit simulation is used to demonstrate the model utility and explore the sensitivity of the self- and mutual capacitances and inductances in signal crosstalk.     

Selective epitaxial growth for the fabrication of CMOS integrated circuits

A process is described for the fabrication of CMOS integrated circuits which combines the epitaxial lateral overgrowth (ELO) technique with the concept of selective epitaxy. The resulting epitaxial material is shown to have a low defect density. Transistors fabricated in the selective epitaxy are shown to have characteristics which are a function of the epitaxial deposition conditions, the substrate orientation and dopant concentration, and the epitaxial layer thickness. Minimum device leakage currents were 250 pA/µm of channel width for n-channel devices fabricated in a p-well and 1.0 pA/µm for devices fabricated on p-substrates. The higher leakage currents for devices fabricated in a well are believed to be a result of the narrow vertical spacing (0.3-0.5 µm) between the n⁺source-drain regions and the n⁺substrate.     

Laser beam backside probing of CMOS integrated circuits

We have developed a new, fully integrated circuit timing analysis tool that provides measurements of electrical waveforms by direct access to the diffusion nodes through the backside of CMOS integrated circuits. The system, known as the IDS 2000, allows the device to be driven at full speed by a wide variety of testers. Utilising an actively modelocked infrared laser beam, the system can detect waveforms with ultrahigh bandwidth ( 10 GHz) from CMOS devices using stroboscopic sampling. The system has proven to be an powerful tool for design debug and failure analysis of flip chip packaged IC as well as any other packaged IC where the silicon side can be thinned and directly accessed.     

Investigation of gate oxide breakdown in CMOS integrated circuits

Investigation of gate oxide breakdown in CMOS integrated circuits, aimed at establishing its dependence on substrate doping (type and level) and its acceleration by an electric field, has been performed in this paper. In order to do this, time-zero-dielectric-breakdown (ramp-voltage-stressed I-V) and time-dependent-dielectric-breakdown (constant-voltage-stressed I-t) tests were carried out and the gate oxide breakdown histograms and electric field acceleration factor were determined and discussed in detail.     

Physical design of testable CMOS digital integrated circuits

A methodology for physical testability assessment and enhancement, implemented with a set of test tools, is presented. The methodology, which can improve the physical design of testable CMOS digital ICs, is supported in realistic fault-list generation and classification. Two measures of physical testability, weighted class fault coverage and fault incidence, and one measure of fault hardness are introduced. The testability is evaluated prior to fault simulation; difficult-to-detect faults are located on the layout and correlated with the physical defects which originate them; and suggestions for layout reconfiguration are provided. Several design examples are described, ascertaining the usefulness of the proposed methodology. The proposed methodology demonstrated that stuck-at test sets only partially cover the realistic faults in digital CMOS designs. Moreover, it is shown that classical fault models of arbitrary faults are insufficient to describe the realistic fault set. Simulation results have shown that the fault set strongly depends on the technology and on the layout style     

Analysis of printed transmission lines for monolithic integrated circuits

Planar transmission lines formed with MIS and Schottky barrier contacts are analysed based on the spectral domain technique. Depending on the frequency and the resistivity of the substrates, three different types of fundamental modes are predicted. The calculated slow-wave factors and attenuation constants agree well with experimental results.     

ESD protection design for CMOS RF integrated circuits using polysilicon diodes

ESD protection design for CMOS RF integrated circuits is proposed in this paper by using the stacked polysilicon diodes as the input ESD protection devices to reduce the total input capacitance and to avoid the noise coupling from the common substrate. The ESD level of the stacked polysilicon diodes on the I/O pad is restored by using the turn-on efficient power-rail ESD clamp circuit, which is constructed by substrate-triggered technique. This polysilicon diode is fully process compatible to general sub-quarter-micron CMOS processes.