MOCVD TiN薄膜厚度漂移对于W填充能力的影响

在大规模集成电路的制造过程中，MOCVD TiN因为其优良的覆盖性能和一致性而被广泛用作W和Al材料的扩散阻挡层和连接层材料。本文介绍了MOCVD TiN厚度对于W填充能力的影响。     

The influence of HfO2 film thickness on the interface state density and low field mobility of n channel HfO2/TiN gate MOSFETs

The influence of HfO₂ thickness (1.6 to 3nm) on interface state density and low field mobility in HfO₂/TiN gate n channel MOSFETs have been studied by analyzing experimental data from charge pumping, split CV, DC I_d-V_g, pulsed I_d-V_g and Y-function methods. It is found that there is no HfO₂ thickness dependence on the interface state density, whereas there is continuous electron mobility degradation with HfO₂ thickness. The devices exhibited no detectable fast transient charge trapping, allowing the relative contributions of phonon and Coulomb scattering to be examined over temperature. The dependence of the low field mobility on temperature from 50 K to 400 K indicates HfO₂ remote phonon scattering as the dominant cause of the mobility degradation.     

The influence of light propagation direction on the stress-induced polarization dependence of silicon waveguides

This letter studies the effects of light propagation direction on the stress-induced polarization dependence of silicon-based waveguides. Silicon is an anisotropic material, so the stresses and the corresponding change of polarization dependence vary with the light propagation directions. The analyses show that when the light propagates in <010> directions on (100) silicon, the stress-induced changes of refractive index and the birefringence in effective index are about 20% more sensitive to the stresses than those when the light propagates in <011> directions.     

The influence of the glass-cover thickness on the magnetoimpedance of amorphous microwires

The influence of the glass-cover thickness on the magnetoimpedance of amorphous cobalt-based microwires is studied. Microwires with different values of the glass thickness were obtained by etching off the glass cover with fluorhydric acid. It was found that, as the cover thickness decreases, the magnetoimpedance ratio does not substantially change, while the intensity of the external magnetic field in which the impedance attains its maximum also decreases. The experimental results are explained using a model taking into account changes in the radial distribution of the anisotropy axes with a decrease in the glass-cover thickness.     

On the impact of TiN film thickness variations on the effective work function of poly-Si/TiN/SiO/sub 2/ and poly-Si/TiN/HfSiON gate stacks

The impact of TiN film thickness variations on the effective work function (WF) of poly-Si/TiN/SiO/sub 2/ and poly-Si/TiN/HfSiON interfaces has been investigated. The electrical signatures of these gate stacks indicate that the concentration of Hf-Ti and Ti-Si bonds at the (poly-Si/TiN)/HfSiON and (poly-Si/TiN)/SiO/sub 2/ interface plays a significant role on the control of the gate stacks' WF. The density of these interfacial bonds and the related work function changes are correlated to the degree of nucleation of the TiN film on the dielectric.     

Case study: Root cause of fluorine detection during TiN ARC layer corrosion of AlSiCu metal lines

The present study examines the cause of fluorine detection during the corrosion of the TiN antireflection coat (ARC) layer of AlSiCu metal lines. When a crack is generated in the tetraethyl orthosilicate (TEOS) oxide or spin-on-glass (SOG) film of an LSI device, the corrosion of the TiN ARC layer (TiO_xN_y-oxidation) may occur due to residual moisture inside the device. In this case, concentrated fluorine is detected around the corroded TiN ARC layer by energy-dispersive X-ray spectroscopy (EDX) analysis. Fluorine concentration was correlated with the degree of corrosion on the TiN ARC layer, suggesting the contribution of fluorine to the corrosion of this layer. When a wider distribution of fluorine concentrations was evaluated, however, the concentration of fluorine and the degree of corrosion on the TiN ARC layer did not match; instead, a higher concentration of fluorine was observed near the crack of the TEOS oxide film. The corroded TiN ARC layer of the sample was then removed, and the Al line of the underlying layer was observed. Etching was observed on the Al line surface where a high concentration of fluorine was detected. More specifically, EDX analysis detected that fluorine reacted with the Al line in the underlying layer after diffusion through the TiO_xN_y film, causing decreased film density due to the corrosion of the TiN ARC layer.     

The influence of thickness and ammonia flow rate on the properties of AlN layers

Undoped AlN layers have been grown on c-plane sapphire substrates by metal-organic chemical vapor deposition in order to study the effects of ammonia (NH₃) flow rate and layer thickness on the structural quality and surface morphology of AlN layers by high-resolution X-ray diffraction, scanning electron microscopy, and atomic force microscopy. Lower NH₃ flow rate improves crystallinity of the symmetric (0 0 0 2) plane in AlN layers. Ammonia flow rate is also correlated with surface quality; pit-free and smooth AlN surfaces have been obtained at a flow rate of 70 standard cm³ per minute. Thicker AlN films improve the crystallinity of the asymmetric (1 0 1̄ 2) plane.     

The influence of nitride thickness variations on the switching speed of MNOS memory transistors

The influence of nitride thickness variations on the switching speed of MNOS memory transistors is examined. The switching time constant is calculated as a function of the nitride thickness using a model of modified Fowler-Nordheim injection. The calculated characteristics compare well with measured characteristics and show a strong dependence on the nitride thickness.     

PCB设置接地回路导通孔对信号传输性能的影响

文章概述了在较高频信号传输中,靠近信号导通孔设置接地回路导通孔可以降低传输信号的损失和噪音。     

The influence of metallization thickness on the characteristics ofcascaded junction discontinuities of shielded coplanar type transmissionline

A full-wave analysis based on the mode-matching technique is applied to analyze cascaded junction discontinuities of coplanar-type transmission lines, coplanar waveguide (CPW) and finline. Results for a CPW-finline transition, a shielded CPW gap and a symmetric notch incorporating the finite metallization thickness effect are presented. The influence of metallization thickness on the coupling effect exhibited by cascaded junction discontinuities is also presented and discussed     

Influence of the sidewall crystal orientation, HfSiO nitridation and TiN metal gate thickness on n-MuGFETs under analog operation

This work characterizes the analog performance of SOI n-MuGFETs with HfSiO gate dielectric and TiN metal gate with respect to the influence of the high-k post-nitridation, TiN thickness and device rotation. A thinner TiN metal gate is found favorable for improved analog characteristics showing an increase in intrinsic voltage gain. The devices where the high-k material is subjected to a nitridation step indicated a degradation of the Early voltage (V_EA) values which resulted in a lower voltage gain. The 45° rotated devices have a smaller V_EA than the standard ones when a HfSiO dielectric is used. However, the higher transconductance of these devices, due to the increased mobility in the (1 0 0) sidewall orientation, compensates this V_EA degradation of the voltage gain, keeping it nearly equal to the voltage gain values of the standard devices.     

OSP表面与孔内膜厚对焊接性能影响研究

近年来,受无铅化RoSH指令和WEEE的影响,印制线路板的表面处理正由传统的热风整平工艺逐步转向其它无铅化表面处理。OSP(organic solderability preservatives)因其特有的优点,在诸多无铅化表面处理中占据了一定的市场份额。对于OSP的可焊性,行业内多数只对回流次数与润湿性能变化做表征研究,鲜见有关于不同热时效下膜厚与润湿性能关系及其三者内在关系的报道。此外,对于表面膜厚与孔内膜厚的差异及其变化对焊接性能的影响也鲜见报道。本文将结合生产实际,阐述不同热时效下膜厚与润湿性能的关系,分析孔内膜厚与爬锡性能的关系,为OSP的无铅化推广提供理论依据。     

The effects of etching and deposition on the performance and stress evolution of open through silicon vias

The effects of silicon etching using the Bosch process and LPCVD oxide deposition on the performance of open TSVs are analyzed through simulation. Using an in-house process simulator, a structure is generated which contains scalloped sidewalls as a result of the Bosch etch process. During the LPCVD deposition step, oxide is expected to be thinner at the trench bottom when compared to the top; however, additional localized thinning is observed around each scallop. The scalloped structure is compared to a structure where the etching step is not performed, but rather a flat trench profile is assumed. Both structures are imported into a finite element tool in order to analyze the effects of processing on device performance. The scalloped structure is shown to have an increased resistance and capacitance when compared to the flat TSV. Additionally, the scalloped TSV does not perform as well at high frequencies, where the signal loss is shown to increase. However, the scallops allow the TSV to respond better to an applied stress. This is due to the scallops’ enhanced range of motion and displacement, meaning they can compensate for the stress along the entire sidewall and not only on the TSV top, as in the flat structure.     

ARC网格中间件的研究与实现

首先将arc和现有的使用最为广泛的globus做了简单的比较,深入探讨的arc的性能优点以及各个组件之间的逻辑联系,并进一步的分析arc的实现要点以及在系统的运行过程中的注意事项,文章最后给出了arc目前还没有解决的问题,并提出了自己的看法和改进的意见。     

高层盲埋孔厚铜板制作探讨

随着电子科技的不断发展,高层厚铜线路板应运而生。文章从高层厚铜板的制作设计、工艺流程、制作要点等进行经验总结,为生产设计提供数据支持。     

Study on crosstalk characteristic of carbon nanotube through silicon vias for three dimensional integration

Coupling noise induced by through silicon vias (TSVs) is expected to be a major concern for three dimensional integrated circuits (3-D ICs) system design. Using equivalent electrical parameters for carbon nanotube (CNT) TSV interconnects, a lumped crosstalk noise model is introduced to capture the TSV-to-TSV coupling noise in CNT via based 3-D ICs and validated with multiple conductor transmission line (MTL) simulation results. The effect of geometrical and material parameters involved on the noise transfer function and peak crosstalk noise, such as insulation thickness, TSV–TSV spacing, TSV height, TSV radius, substrate conductivity and metallic CNT density, is investigated with the proposed model. Simulation results show that the TSV coupling can be divided into three frequency behavior regions. Three approaches using driver sizing, grounded vias shielding and air gap-based silicon-on-insulator (SOI) technique are proposed to mitigate TSV crosstalk coupling noise. The proposed approaches are demonstrated in frequency- and time- domain simulations. They provide the reduction in full-band noise transfer function by an average of 11.71 dB, 24.85 dB and 3.46 dB, and the decrease in 1 GHz peak noise voltage by 53.24 mV, 40.72 mV and 15.1 mV.     

TiN/TaN 厚度变化对nMOSCAP栅叠层有效功函数的影响

We evaluated the TiN/TaN/TiA1 triple-layer to modulate the effective work function （EWF） of a metal gate stack for the n-type metal-oxide-semiconductor （NMOS） devices application by varying the TiN/TaN thickness. In this paper, the effective work function of EWF ranges from 4.22 to 4.56 eV with different thicknesses of TiN and TaN. The thinner TiN and/or thinner in situ TaN capping, the closer to conduction band of silicon the EWF is, which is appropriate for 2-D planar NMOS. Mid-gap work function behavior is observed with thicker TiN, thicker in situ TaN capping, indicating a strong potential candidate of metal gate material for replacement gate processed three-dimensional devices such as FIN shaped field effect transistors. The physical understandings of the sensitivity of EWF to TiN and TaN thickness are proposed. The thicker TiN prevents the A1 diffusion then induces the EWF to shift to mid-gap. However, the TaN plays a different role in effective work function tuning from TiN, due to the Ta-O dipoles formed at the interface between the metal gate and the high-k layer.     

PCB板厚控制简述

PCB板厚控制是一个系统且涉及面广的工程,本文运用统计分析以及理论计算相结合的方法,从PCB板厚工程设计、层压板厚控制以及其它工序对板厚的影响等方面入手,系统阐述了PCB板厚的一些控制要点,为PCB板厚控制提供理论依据。     

焊层空洞对IGBT芯片温度的影响

焊层空洞是造成IGBT模块散热不良的主要因素,基于IGBT的七层结构,建立了IGBT模块封装结构的三维有限元模型并对其进行热分析,研究焊层空洞对IGBT芯片温度的影响。对比了有无焊层空洞时IGBT模块的整体温度分布,分析了空洞类型、空洞大小、空洞形状、空洞数量及空洞分布对IGBT芯片温度分布的影响。研究结果表明:芯片焊层空洞对芯片温度的影响较大,衬板焊层空洞对芯片温度的影响较小;贯穿型空洞对芯片温度的影响要大于非贯穿型空洞;单个空洞越大,IGBT芯片温度越高;相同形状的空洞,处于边角位置比处于焊层内部对芯片温度影响大;多个空洞分布越集中,芯片温度越高;焊层缝隙对芯片温度的影响要小于空洞对芯片温度的影响。因此,在封装过程中应避免出现芯片焊层空洞,以提高IGBT的可靠性。     

Schottky barrier height of sputtered TiN contacts on silicon

The Schottky barrier height of sputtered TiN on both p- and n-type silicon was determined by I-V and C-V measurements. The barrier height is found to increase on n-Si and to decrease on p-Si, upon thermal annealing. The experimental results are explained in terms of sputtering damage. This damage is modeled by donor-like traps whose concentration decays exponentially from the silicon surface. A characteristic length equal to 45 Å accounts for the observed characteristics. The trap-free values of the barrier height were obtained by I-V measurements after sequential thermal annealing up to 600°C. These values are φ_Bn = 0.55 V on n-type and φ_Bp = 0.57 V on p-type silicon.