Electrical properties of high permittivity ZrO2 gate dielectrics on strained-Si

Deposition and electrical properties of high dielectric constant (high-k) ultrathin ZrO₂ films on tensilely strained silicon (strained-Si) substrate are reported. ZrO₂ thin films have been deposited using a microwave plasma enhanced chemical vapor deposition technique at a low temperature (150 °C). Metal insulator semiconductor (MIS) structures are used for high frequency capacitance–voltage (C–V), current–voltage (I–V), and conductance–voltage (G–V) characterization. Using MIS capacitor structures, the reliability and the leakage current characteristics have been studied both at room and high temperature. Schottky conduction mechanism is found to dominate the current conduction at a high temperature. Observed good electrical and reliability properties suggest the suitability of deposited ZrO₂ thin films as an alternative as gate dielectrics. Compatibility of ZrO₂ as a gate dielectric on strained-Si is shown.     

Analysis of I–V measurements on PtSi-Si Schottky structures in a wide temperature range

I–V Measurements on PtSi-Si Schottky structures in a wide temperature range from 90 to 350 K were carried out. The contributions of thermionic-emission current and various other current-transport mechanisms were assumed when evaluating the Schottky barrier height Φ₀. Thus the generation-recombination, tunneling and leak currents caused by inhomogeneities and defects at the metal-semiconductor interface were taken into account.

Taking the above-mentioned mechanisms and their temperature dependence into consideration in the Schottky diode model, an outstanding agreement between theory and experiment was achieved in a wide temperature range.

Excluding the secondary current-transport mechanisms from the total current, a more exact value of the thermionic-emission saturation current I_te and thus a more accurate value ofΦ_b was reached.

The barrier height Φ_b and the modified Richardson constant A^** were calculated from the plot of thermionic-emission saturation current I_te as a function of temperature too. The proposed method of finding Φ_b is independent of the exact values of the metal-semiconductor contact area A and of the modified Richardson constant A^**. This fact can be used for determination of Φ_b in new Schottky structures based on multicomponent semiconductor materials.

Using the experimentally evaluated value A^** = 1.796 × 10⁶ Am⁻²K⁻² for the barrier height determination from I–V characteristics the value of Φ_b = 0.881 ± 0.002 eV was reached independent of temperature.

The more exact value of barrier height Φ_b is a relevant input parameter for Schottky diode computer-aided modeling and simulation, which provided a closer correlation between the experimental and theoretical characteristics.     

Comment on “Negative Schottky barrier between titanium and n-type Si(0 0 1) for low-resistance ohmic contacts”

It is shown in this letter that recently published statements [Solid-State Electron 2004;48(2):335] on negative Schottky barrier height between titanium and n-type Si(0 0 1) are not satisfactorily experimentally approved and may not be true. The rectification effect of the Schottky barrier is overshadowed by high series resistance which influences I–V characteristic already in reverse bias and disables to extract true Schottky barrier height from the characteristics in the bias range studied. On the basis of published data it is probably not possible to speak about negative Schottky barrier height.     

Noise studies in internal field emission diodes

The breakdown process of a zener diode in reverse direction is governed by internal field emission at low voltage and by impact ionization at higher voltage. For breakdown voltage in the transition range between 3 and 6 V, both physical processes appear in combination. Measuring the I–V characteristic and the noise current fluctuations spectral density it is possible to show the zener current multiplication by the multiplication effect described by Tager. In addition the I–V characteristic can be written empirically I = Vⁿ.     

Optoelectronic properties of Zn0.52Se0.48/Si Schottky diodes

Zn_0.52Se_0.48/Si Schottky diodes are fabricated by depositing zinc selenide (Zn_0.52Se_0.48) thin films onto Si(1 0 0) substrates by vacuum evaporation technique. Rutherford backscattering spectrometry (RBS) analysis shows that the deposited films are nearly stoichiometric in nature. X-ray diffractogram of the films reveals the preferential orientation of the films along (1 1 1) direction. Structural parameters such as crystallite size (D), dislocation density (δ), strain (ε), and the lattice parameter are calculated as 29.13 nm, 1.187 × 10⁻¹⁵ lin/m², 1.354 × 10⁻³ lin⁻² m⁻⁴ and 5.676 × 10⁻¹⁰ m respectively. From the I–V measurements on the Zn_0.52Se_0.48/p-Si Schottky diodes, ideality and diode rectification factors are evaluated, as 1.749 (305 K) and 1.04 × 10⁴ (305 K) respectively. The built-in potential, effective carrier concentration (N_A) and barrier height were also evaluated from C–V measurement, which are found to be 1.02 V, 5.907 × 10¹⁵ cm⁻³ and 1.359 eV respectively.     

p-n heterojunctions

A classical kinetic emission model coupled with an assumed energy band diagram which includes the effects of a discontinuity in the electron affinity, effective mass, permittivity and the energy gap at the junction interface is used as the basis for an analysis of the static current-voltage characteristic of the abrupt p-n heterojunction. The derived characteristic is then used to determine regions of quasi-equilibrium within the depletion layer and to predict the position dependence of the quasi-Femri levels.

Two distinct modes of operation are predicted for the heterojunctions I–V characteristic: Metal-semiconductor type operation where the current is limited by the ability of the carriers to surmount the potential barrier at the junction interface and homojunction type operation where the current is limited by the ability of the carriers to diffuse away from the junction depletion region. The predicted extrapolated saturation current for the former type of operation, is in general, significantly less than that for the latter. The position dependence of the quasi-Fermi levels is also different for the two types of operation. For metal-semiconductor type operation a drop in the quasi-Fermi level across the depletion layer is expected, whereas for homodiode type operation there is a negligible variation of the quasi-Fermi level in this region.

The heterojunction I–V characteristic presented here, which differs significantly from previous models, agrees favourably with experimental data on Ge-GaAs heterojunctions reported in the literature and with others recently fabricated by the present authors.     

Correlation between barrier heights and ideality factors of H-terminated Sn/p-Si(1 0 0) Schottky barrier diodes

Schottky barrier diodes (SBDs) were prepared by evaporation on H-terminated p-Si(1 0 0) surfaces. The Si(1 0 0)-H surfaces were obtained by wet chemical etching in diluted hydrofluoric acid. The current–voltage (I–V) characteristics of real SBDs are described by using two fitting parameters that are the effective barrier height (EBH) and ideality factor n. They were determined from I–V characteristics of SBDs (30 diodes) fabricated under experimentally identical conditions. The obtained values of EBHs varied from 0.729 to 0.749 eV, and the values of ideality factors varied from 1.083 to 1.119. The results showed that both parameters of SBDs differ from one diode to another even if they are identically prepared. The EBH distributions were fitted by two Gaussian distribution functions, and their mean values were found to be 0.739 ± 0.003 eV and 0.733 ± 0.001 eV, respectively. The homogeneous barrier height of SBDs was found to be 0.770 eV from the linear relationship between EBHs () and ideality factors (n).     

Temperature-dependence of steady-state characteristics of SCR-type ESD protection circuits

Experimental analysis of the temperature-dependent I–V characteristics of various SCR (Silicon-Controlled Rectifier) electrostatic discharges (ESD) protection circuits have been carried out. These circuits include diode-chain-triggering SCR (DCTSCR), low-voltage zener diode trigger SCR (ZDSCR), low-voltage trigger SCR (LVTSCR) and gate-coupled low-voltage trigger SCR (GCSCR) circuits. The ZDSCR uses the zener breakdown mechanism of a reverse-biased p⁺–n⁺ diode as a trigger mechanism, the DCTSCR uses the current flowing through forward-biased diode chain as a trigger mechanism, the LVTSCR uses the grounded-gate MOSFET breakdown current as the trigger mechanism and the steady-state I–V characteristics of GCSCR also uses the avalanche breakdown as a triggering mechanism. The trigger voltage can decrease or increase with increasing temperature depending upon the triggering mechanism used in the circuit, however the holding voltages of these SCRs decrease with increasing temperature.     

Breakdown degradation associated with elementary screw dislocations in 4H-SiC pn junction rectifiers

It is well-known that SiC wafer quality deficiencies are delaying the realization of outstandingly superior 4H-SiC power electronics. While efforts to date have centered on eradicating micropipes (i.e., hollow core super-screw dislocations with Burgers vector>2c), 4H-SiC wafers and epilayers also contain elementary screw dislocations (i.e., Burgers vector=1c with no hollow core) in densities on the order of thousands per cm², nearly 100-fold micropipe densities. This paper describes an initial study into the impact of elementary screw dislocations on the reverse-bias current–voltage (I–V) characteristics of 4H-SiC p⁺n diodes. First, synchrotron white beam X-ray topography (SWBXT) was employed to map the exact locations of elementary screw dislocations within small-area 4H-SiC p⁺n mesa diodes. Then the high-field reverse leakage and breakdown properties of these diodes were subsequently characterized on a probing station outfitted with a dark box and video camera. Most devices without screw dislocations exhibited excellent characteristics, with no detectable leakage current prior to breakdown, a sharp breakdown I–V knee, and no visible concentration of breakdown current. In contrast, devices that contained at least one elementary screw dislocation exhibited 5–35% reduction in breakdown voltage, a softer breakdown I–V knee, and visible microplasmas in which highly localized breakdown current was concentrated. The locations of observed breakdown microplasmas corresponded exactly to the locations of elementary screw dislocations identified by SWBXT mapping. While not as detrimental to SiC device performance as micropipes, the undesirable breakdown characteristics of elementary screw dislocations could nevertheless adversely affect the performance and reliability of 4H-SiC power devices.     

Optically controlled current-voltage characteristics of ion-implanted MESFETs

Optically controlled MESFETs are useful as optical devices for optical communications, and as photodetectors. In this paper, a theoretical model for the I–V characteristics of these MESFETs is presented. The model considers the nonuniform Gaussian doping for ion-implanted channels. It takes both the photogenerated carriers as well as the doping generated residual carriers into account. It is noted that the density of photogenerated carriers in the channel due to diffusion is much less than that due to drift. Treatment both under gradual channel approximation and saturation velocity approximation has been presented. The gradual channel and the velocity saturation approximations are applied to study the I–V characteristics of long-channel and short-channel MESFETs, respectively. Results for both long-channel and short-channel MESFETs indicate that drain saturation current and transconductance can be improved by properly fixing the optical flux, and the absorption coefficient of the material.     

On the effect of non-degenerate doping of polysilicon gate in thin oxide MOS-devices—Analytical modeling

A one-dimensional model of the polysilicon-gate-oxide-bulk structure is presented in order to analyze the implanted gate MOS-devices. The influence of the ionized impurity concentration in the polysilicon-gate near the oxide and the charge at the polysilicon-oxide interface on the flat-band voltage, threshold voltage, inversion layer charge and the quasi-static C–V characteristic is quantitatively studied. The calculations show a considerable degradation of the inversion layer charge due to the voltage drop in the gate, especially in thin oxide devices. The calculated quasi-static C–V curves agree with the recently published data of implanted gate devices.     

A novel silicide nanopatterning method for the fabrication of ultra-short channel Schottky-tunneling MOSFETs

A novel nanometer patterning technique was developed to pattern epitaxial CoSi₂ layers and to fabricate Schottky-tunneling MOSFETs. The nanopatterning method is based on the local oxidation of silicide layers. A feature size as small as 50 nm was obtained for 20 nm epitaxial CoSi₂ layers on Si(100) after patterning by local rapid thermal oxidation in dry oxygen. A Schottky-tunneling MOSFET with epitaxial CoSi₂ Schottky contacts at both the source and the drain was fabricated using this nanopatterning method to make the 100 nm gate. The device shows good I–V characteristics at 300 K.     

A circuit-compatible analytical device model for ballistic nanowire transistors

Silicon nanowire transistors (SNWTs) have attracted broad attention as a promising device structure for future integrated circuits. Silicon nanowires with a diameter as small as 2 nm and having high carrier mobility have been achieved. Consequently, to develop TCAD tools for SNWT design and to model SNWT for circuit-level simulations have become increasingly important. This paper presents a circuit-compatible closed-form analytical model for ballistic SNWTs. Both the current–voltage (I–V) and capacitance–voltage (C–V) characteristics are modeled in terms of device parameters and terminal voltages. Such a model can be efficiently used in a conventional circuit simulator like SPICE to facilitate transistor-level simulation of large-scale nanowire or mixed nanowire-CMOS circuits and systems.     

A complete analytical model of GaN MESFET for microwave frequency applications

A simple physics-based analytical model for a non-self-aligned GaN MESFET suitable for microwave frequency applications is presented. The model includes the effect of parasitic source/drain resistances and the gate length modulation. The model is then extended to evaluate I–V and C–V characteristics, transconductance, cut-off frequency, transit time, RC time constant, optimum noise figure and maximum power density. The transconductance of about 21 mS/mm is obtained for GaN MESFET using the present theory in comparison to 23 mS/mm of the reported data. The cut-off frequency of more than 1 GHz, optimum noise figure of 6 dB and maximum output power density of more than 1 W/mm are predicted.     

Novel Delta-Doped InAlGaP/GaAs Heterojunction Bipolar Transistor

The first successful demonstration of a delta-doped InAlGaP/GaAs heterojunction bipolar transistor (HBT) is reported. A comparison to a baseline InAlGaP/GaAs HBT without a delta-doping layer is made. Both of these devices exhibit near-ideal current gain (beta) versus the collector current (I _C) characteristics (i.e., beta independent of I _C) at high currents. The delta-InAlGaP/GaAs HBT exhibits a 40% reduction in offset voltage (V _{CE, offset}) and a 250-mV reduction in knee voltage (V _k) without sacrificing beta compared with the baseline InAlGaP/GaAs HBT. At a higher I _C, the decrease in beta of the InAlGaP/GaAs HBTs with increasing temperature is significantly smaller than the corresponding effect measured in the formerly reported GaAs-based HBTs. The rather temperature-insensitive characteristics of these two InAlGaP/GaAs HBTs originate from their large valence-band discontinuity (DeltaE _V) at the emitter-base (E-B) junction. Furthermore, at intermediate base current I _B levels (0.4-1.6 mA), V _{CE, offset} falls as I _B increases, which is a trend contrary to that of most HBTs in the literature. Finally, the experimental dependence of V _{CE, offset} on temperature, I _B, and the effective barrier height at the E-B junction is explained with reference to an extended large-signal model.     

Effect of oxide resistance on the characterization of interface trap density in MOS structures

The oxide resistance in a practical MOS capacitor is generally not high enough to be negligible in the evaluation of interface trap density based on the qruasi-static capacitance-voltage (C–V) curve. The importance of the effects of oxide resistance ranging from 10¹³ to 10¹⁶ Ω on the C–V curve and the corresponding interface trap density is theoretically shown. To obtain the oxide resistance in MOS structures the newly reported charge-then-decay method is suggested. From the oxide resistance found, one can compare the distribution curves of interface trap density before and after removing the oxide resistance effect. It is found that the results obtained after removing the oxide resistance effect are more consistent than those without removing it. It addition, the removal of the oxide resistance effect for a sample having a hysteresis C–V behavior is also discussed.     

Procedure for determining diode parameters at very low forward voltage

A technique is proposed to extract the reverse saturation current parameter and ideality factor of semiconductor junctions from the low forward voltage region of the device’s characteristics. The method involves performing a mathematical operation on the experimental data that allows to calculate the parameters at values of forward current smaller than the reverse saturation current. The procedure was tested and its accuracy verified on synthetic I–V characteristics, with and without added simulated experimental error or noise. Good agreement is obtained between the parameters used in modeling and the extracted values. The procedure was also applied to experimentally measured I_B–V_BE characteristics of a real power BJT.     

An analytical model for the power bipolar-MOS transistor

This paper presents an analytical model for the I–V characteristics of the bipolar-MOS power transistor, also known as IGT or COMFET. Good agreement between this model and experiments is found over a wide range of carrier lifetime and current density. The predicted trade-off between the forward voltage drop and device turn-off time (0.4–10 μsec) has been verified by experiment. For even shorter switching time, the model predicts only a moderate increase in V_F. Adding a more heavily doped buffer epitaxial layer is shown to only slightly increase V_F but offers several important benefits. The comparison between n-channel and p-channel devices is discussed using the model and the forward voltage drops for the two types of devices are shown to differ by only a small percentage in spite of the large difference in electron and hole mobilities.     

Sensing behavior and mechanism of titanium dioxide-based MOS hydrogen sensor

A Pd/TiO₂/Si MOS sensor (Pdtisin sensor) is proposed for the detection of hydrogen gas. The sensor is fabricated on a p-type 1 1 1 silicon wafer having resistivity of 3–6 Ω cm. The thickness of TiO₂ in this structure is about 600 nm. The capacitance–voltage (C–V) and conductance–voltage (G–V) characteristics of the device is observed on the exposure of hydrogen gas at room temperature. The mechanism of hydrogen sensing of titanium dioxide-based MOS sensor (MOS capacitor) has been investigated by evaluating the change in flat-band voltage (V_FB) and fixed surface state density of the device in presence of hydrogen gas. The device exhibits very large parallel shift in C–V as well in G–V characteristics. The possible mechanism on Pd/TiO₂ and TiO₂/Si surface in presence of hydrogen gas has been proposed. The response and recovery time of the device is also measured at room temperature.     

Strain relaxation and dopant distribution in the rapid thermal annealing of Co with Si/Si1−xGex/Si heterostructure

The reaction of cobalt with the Si-sacrificial cap in the strained Si/Si_1−xGe_x/Si MBE grown heterostructure was studied. The Si-cap is added to prevent the relaxation of the SiGe and to guarantee uniform and reliable silicidation reaction. The Si_1−xGe_x epilayer, with Ge content between 18 and 28 at%, was highly B doped, while the Si-cap was undoped or B doped either during growth or by ion implantation. Cobalt evaporation was followed by rapid thermal annealing at 450–700°C for 30 sec in N₂ or Ar+10%H₂. When the silicide penetrated the Si-cap/Si_1−xGe_x interface, noticeable out-diffusion of Ge and B to the surface was observed. In spite of the presence of the Si-cap significant strain relaxation was observed in three cases: (1) in the implanted samples, although the implantation was confined to the Si-cap, (2) when the Co layer was too thick, such that the silicide penetrated the SiGe layer and (3) when the Ge content in the SiGe layer was relatively high (27.5%).