A 14-b, 100-MS/s CMOS DAC designed for spectral performance

A 14-bit, 100-MS/s CMOS digital-to-analog converter (DAC) designed for spectral performance corresponding more closely to the 14-bit specification than current implementations is presented. This DAC utilizes a nonlinearity-reducing output stage to achieve low output harmonic distortion. The output stage implements a return-to-zero (RZ) action, which tracks the DAC once it has settled and then returns to zero. This RZ circuit is designed so that the resulting RZ waveform exhibits high dynamic linearity. It also avoids the use of a hold capacitor and output buffer as in conventional track/hold circuits. At 60 MS/s, DAC spurious-free dynamic range is 80 dB for 5.1-MHz input signals and is down only to 75 dB for 25.5-MHz input signals. The chip is implemented in a 0.8-μm CMOS process, occupies 3.69×3.91 mm ² of die area, and consumes 750 mW at 5-V power supply and 100-MS/s clock speed     

Design and Measurement of a CT $DeltaSigma$ ADC With Switched-Capacitor Switched-Resistor Feedback

The performance of traditional continuous-time (CT) delta-sigma (DeltaSigma) analog-to-digital converters (ADCs) is limited by their large sensitivity to feedback pulse-width variations caused by clock jitter in their feedback digital-to-analog converters (DACs). To mitigate that effect, we propose a modified switched-capacitor (SC) feedback DAC technique, with a variable switched series resistor (SR). The architecture has the additional benefit of reducing the typically high SC DAC output peak currents, resulting in reduced slew-rate requirements for the loop-filter integrators. A theoretical investigation is carried out which provides new insight into the synthesis of switched-capacitor with switched series resistor (SCSR) DACs with a specified reduction of the pulse-width jitter sensitivity and minimal power consumption and complexity. To demonstrate the concept and to verify the reduced pulse-width jitter sensitivity a 5 mW, 312 MHz, second order, low-pass, 1-bit, CT DeltaSigma modulator with SCSR feedback was implemented in a 1.2 V, 90 nm, RF-CMOS process. An SNR of 66.4 dB and an SNDR of 62.4 dB were measured in a 1.92 MHz bandwidth. The sensitivity to wideband clock phase noise was reduced by 30 dB compared to a traditional switched-current (SI) return-to-zero (RZ) DAC.     

A broad-band amplifier using GaAs/GaAlAs heterojunction bipolartransistors

A compact wideband amplifier (or gain block) designed around a Darlington pair of GaAs/GaAlAs heterojunction bipolar transistors (HBTs) is discussed. This circuit has been fabricated by an ion-implanted process with a transistor f_t of 40 GHz. Two variants of the circuit gave either a 8.5-dB gain with a DC-to-5-GHz 3-dB bandwidth or a 13-dB gain with a DC-to-3-GHz bandwidth. These amplifiers gave 11.8- and 18.3-dBm output, respectively, at 1-dB gain compression     

Wide-band GaInAs MISFET amplifiers

The authors present the first reported results on wideband GaInAs MISFET amplifiers. Using 1-μm-gate-length, 0.56-mm-gate-width GaInAs MISFETs, they obtained: (a) a power output of 230±30 mW (0.41 W/mm) with 33±3% power-added efficiency; (b) a power output of 265±15 mW (0.47 W/mm) with 30±3% power-added efficiency (both over the 7-11-GHz band), and (c) a power output of 220±45 mW (0.39 W/mm) with 32±4% power-added efficiency over the 6-12-GHz band. With a 0.7-μm-gate-length GaInAs MISFET, a small-signal gain of 5±0.5 dB over the 11.4-22.6-GHz band was obtained. These data include all connector, bias network, and circuit losses. The authors present an equivalent circuit model of these MISFETs based on S-parameter measurements. The model is essentially that of a MISFET with capacitors representing gate-to-source and gate-to-drain overlap capacitances added at input and output     

A high-power wideband traveling-wave tube with stepwise changes in the diameter of the drift channel

Results of the design of a high-power wideband (in the band 8–18 GHz) traveling-wave tube (TWT) with stepwise changes in the diameter of the drift channel are presented. The TWT is stable against self-excitation by a backward wave at high values of the accelerating voltage. It is shown that the output section of the device can be increased by a factor of 1.5 and the operating current can be raised by a factor of 1.3. These increases are attained owing to the 1.27-GHz diversity of the π-type frequencies of sections with different values of the channel diameter and owing to growth of the starting current corresponding to self-excitation by the backward wave. Application of the TWT with the interaction space that has steps of the channel diameter improved the electron efficiency by a factor of 1.2 and increased the output power by a factor of 1.6.     

A low glitch 14-b 100-MHz D/A converter

A low glitch 14-b 100-MHz current output digital-to-analog converter (DAC) is described. In addition to segmentation of the four most significant bits (MSB's) into 15 equally weighted current sources, a proportional-to-absolute-temperature (PTAT) switching voltage is applied to the current steering devices to minimize glitch over temperature. A bidirectional thin-film trim network and high β n-p-n devices reduce the amount of laser trimming required to achieve 14-b accuracy, resulting in less post-trim degradation of DAC linearity over temperature and the life of the chip. The converter has been fabricated in a 4-GHz/1.4-μm BiCMOS technology and exhibits a measured glitch energy of 0.5 pV·s (singlet). Settling time to within ±0.012% of the final value is ⩽20 ns for both rising and falling edges of a full scale step. Spurious free dynamic range (SFDR) for the described converter is 87 dBc at an update rate (f_CLK) of 10 MHz and an output frequency (f_OUT) of 2.03 MHz. The converter operates from +5 V and -5.2 V supplies and consumes 650 mW independent of conversion rate. The chip size is 4.09×4.09 mm including bond pads and electrostatic discharge (ESD) protection devices     

InP D-HBT ICs for 40-Gb/s and higher bitrate lightwave transceivers

The combination of device speed (f/sub T/, f/sub max/ > 150 GHz) and breakdown voltage (V/sub bceo/ > 8 V) makes the double heterojunction bipolar InP-based transistor (D-HBT) an attractive technology to implement the most demanding analog functions of 40-Gb/s transceivers. This is illustrated by the performance of a number of analog circuits realized in an InP D-HBT technology with an 1.2- or 1.6-/spl mu/m-wide emitter finger: a low phase noise push-push voltage-controlled oscillator with -7-dBm output power at 146 GHz, a 40-GHz bandwidth and low-jitter 40-Gb/s limiting amplifier, a lumped 40-Gb/s limiting driver amplifier with 4.5-V/sub pp/ differential output swing, a distributed 40-Gb/s driver amplifier with 6-V/sub pp/ differential output swing, and a number of distributed preamplifiers with up to 1.3-THz gain-bandwidth product.     

A current-steering self-calibration 14-bit 100-MSPs DAC

This paper presents the design and implementation of a 14-bit,100 MS/s CMOS digital-to-analog converter(DAC).Analog background self-calibration based on the concept of analog current trimming is introduced.A constant clock load switch driver,a calibration period randomization circuit and a return-to-zero output stage have been adopted to improve the dynamic performance.The chip has been manufactured in a SMIC 0.13-μm process and occupies 1.33× 0.97 mm2 of the core area.The current consumption is 50 mA under 1.2/3.3 V dual power supplies for digital and analog,respectively.The measured differential and integral nonlinearity is 3.1 LSB and 4.3 LSB,respectively.The SFDR is 72.8 dB at a 1 MHz signal and a 100 MHz sampling frequency.     

A 12-bit 1-Gword/s GaAs digital-to-analog converter system

The circuitry for a 12-b 1-Gword/s digital-to-analog converter (DAC) IC is described. A DC linearity of /spl plusmn/1/8 LSB has been preserved with this all-depletion GaAs MESFET chip. Dynamic measurements in the frequency domain indicate nonlinearities of less than -62 dBc at a 1-GHz clock rate. The DAC uses a very fast FET analog current switch that exhibits sufficiently low leakage currents for a 12-b linearity. The limited on-chip matching capabilities require the precision DC currents to be generated external to the GaAs chip. A current-switching DAC that partitions the high-speed functions onto a single GaAs chip while the high-precision bit currents are realized off-chip is described. The GaAs chip contains 12 1-b cells, each of which switches an analog bit current into a single sampler circuit that is shared by all the switches. The sampler is used to increase the dynamic linearity in the DAC.     

Monolithic integrated blanking up-converter

A novel GaAs monolithic integrated DC-coupled up-converter is presented. It up-converts a 0.1- to 0.5-GHz signal to 0.6 to 1.75 GHz. The high level of integration has been achieved in a small chip size of 1.22 mm×1.22 mm by utilizing active matching techniques. A wideband local oscillator (LO) amplifier, an active 180° splitter, a double-balanced mixer, an RF amplifier, an actively matched IF amplifier, and an RF blanking circuit are integrated on a GaAs chip. The up-converter exhibits an 8-dB conversion gain, a maximum input/output voltage standing wave ratio (VSWR) of less than 1.6, and a 40-dB RF blanking for an IF of 0.1 to 0.5 GHz and LO of 0.5-1.25 GHz. The measured results are in good agreement with the simulated results     

A CMOS 10-gb/s SONET transceiver

This paper presents a single-chip SONET OC-192 transceiver (transmitter and receiver) fabricated in a 90-nm mixed-signal CMOS process. The transmitter consists of a 10-GHz clock multiplier unit (CMU), 16:1 multiplexer, and 10-Gb/s output buffer. The receiver consists of a 10-Gb/s limiting input amplifier, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. Both transmit and receive phase-locked loops employ a 10-GHz on-chip LC voltage-controlled oscillator (VCO). This transceiver exceeds all SONET OC-192 specifications with ample margin. Jitter generation at 10.66-Gb/s data rate is 18 mUI/sub pp/ (unit interval, peak-to-peak) and jitter tolerance is 0.6 UI/sub pp/ at 4-MHz jitter frequency. This transceiver requires 1.2V for the core logic and 1.8 V for input/output LVDS buffers. Multiple power supply domains are implemented here to mitigate crosstalk between receiver and transmitter. The overall power dissipation of this chip is 1.65 W.     

A 28-GHz monolithic integrated quadrature oscillator in SiGe bipolar technology

This paper presents a 28-GHz monolithic quadrature voltage-controlled oscillator (QVCO) realized in a preproduction 0.4-/spl mu/m SiGe bipolar technology with 85-GHz transit frequency. QVCOs efficiently drive quadrature modulators and demodulators in receivers or transmitters. At 28.9 GHz, the circuit provides -14.7 dBm of output power and phase noise of -84.2 dBc/Hz at a 1-MHz offset. The two output signals are in quadrature with phase error of about 5/spl deg/. Tuning of the QVCO may be done in the frequency range from 24.8 to 28.9 GHz with nearly constant output power. The circuit consumes 25.8 mA from the 5 V voltage supply.     

一种DC-DC开关电源片上软启动电路

提出了一种基于DAC(digital-to-analog converter)控制的数字软启动电路,利用DAC控制和软启动电压检测技术,有效抑制了DC-DC开关电源启动过程中产生的浪涌电流和输出电压过冲,实现了输出电压从零到调整值的平坦上升.在启动完成后启动电路的偏置电流被彻底关断,实现了低功耗没计.该软启动电路采用CMOS器件设计,无需任何外围元件,便于被DC-DC开关电源集成.该电路已成功集成到一款Buck型PWM(pulse width modulation)控制器当中,测试结果表明:在整个负载范围内,DC-DC在启动过程中电感电流平稳变化,输出电压平滑上升、无过冲,启动时间控制在1.2ms.     

宽带低杂散LFM信号的产生方法与系统设计

针对宽带雷达线性调频信号产生,采用FPGA电路和宽带DAC电路直接产生50 MHz~550 MHz 的线性调频中频信号。将中频信号上变频到2 GHz~2. 5 GHz 的射频频段,再经过2 倍频获得4 GHz~5 GHz的宽频带线性调频信号。为进一步提高射频输出信号的幅度/相位特性,采用幅/相预失真校准方法,并精心设计信号产生系统的中频电路和射频电路,进行了实验研究与分析。对实际系统的测试结果表明,系统产生LFM信号的带外杂散优于-55 dB,带内起伏小于依2 dB,且系统稳定、可靠。     

A 1.8-GHz Spur-Cancelled Fractional-N Frequency Synthesizer With LMS-Based DAC Gain Calibration

A 1.8-GHz wideband DeltaSigma fractional-N frequency synthesizer achieves the phase noise performance of an integer-N synthesizer using a spur-cancellation digital-to-analog converter (DAC). The DAC gain is adaptively calibrated with a least-mean-square (LMS) sign-sign correlation algorithm for better than 1% DAC and charge pump (CP) gain matching. The proposed synthesizer phase-locked loop (PLL) is demonstrated with a wide 400-kHz loop bandwidth while using a low 14.3-MHz reference clock, and offers a better phase noise and bandwidth tradeoff. Using an 8-bit gain-calibrated DAC, DeltaSigma-shaped divider ratio noise is suppressed by as much as 30 dB. The second-order DeltaSigma fractional-N PLL exhibits in-band and integrated phase noises of -98 dBc/Hz and 0.8deg. The chip, fabricated in 0.18-mum CMOS, occupies 2 mm², and consumes 29 mW at 1.8-V supply. The spur cancellation and correlation function consumes 30% additional power     

A low-Voltage 10-bit CMOS DAC in 0.01-mm/sup 2/ die area

A low-voltage 10-bit digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.18-/spl mu/m CMOS process. The DAC is optimized for large integrated circuit systems where possibly dozens of such DAC would be employed for the purpose of digitally controlled analog circuit calibration. The DAC occupies 110 /spl mu/m/spl times/94 /spl mu/m die area. A segmented R-2R architecture is used for the DAC core in order to maximize matching accuracy for a minimal use of die area. A pseudocommon centroid layout is introduced to overcome the layout restrictions of conventional common centroid techniques. A linear current mirror is proposed in order to achieve linear output current with reduced voltage headroom. The measured differential nonlinearity by integral nonlinearity (DNL/INL) is better than 0.7/0.75 LSB and 0.8/2 LSB for 1.8-V and 1.4-V power supplies, respectively. The DAC remains monotonic (|DNL|<1 LSB) as INL reaches 4 LSB down to 1.3-V operation. The DAC consumes 2.2 mA of current at all supply voltage settings.     

A 5-GHz programmable frequency divider in 0.18-μM CMOS technology

A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented.The divider based on a dual-modulus prescaler (DMP) and pulse-swallow counter is designed to reduce power consumption and chip area.Implemented in the 0.18-μm mixed-signal CMOS process,the divider operates over a wide range of 1-7.4 GHz with an input signal of 7.5 dBm; the programmable divider output phase noise is -125.3 dBc/Hz at an offset of 100 kHz.The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm2.The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.     

基于现场可更换组件结构的宽带波形产生设计

给出了一种基于现场可更换组件(LRM)结构的4通道宽带波形产生板卡设计。板卡上集成了一款高性能的现场可编程逻辑阵列(FPGA)以及4片高速数模转换器(DAC)芯片。DAC和FPGA之间为高速低电压差分信号(LVDS)接口,板卡输入输出接口选用标准二代LRM连接器。DAC采样率为4 Gsps,在2.4 GHz中频(IF)上瞬时带宽达到了1.2 GHz,信噪比(SNR)优于50 dB。该设计可广泛应用于电子战和宽带雷达系统中。     

Design of a 1.1 GSps 12 bit digital to analog convertor with 56 dBc SFDR at Nyquist frequency

High speed digital to analog convertor (DAC) is a key component in software defined radio systems, digital radars and wide band arbitrary waveform generators. In those applications, the performance of the DAC, especially the wideband dynamic range, is important in determining the system performance. In this paper we present a high speed 12 bit current steering DAC with optimized wideband performance. Theoretical analysis and optimizing strategy are present in this paper along with circuit details and measurement results. Experimental results reveal the proposed circuit is capable to operate up to 1.1 GSps. The measured spurious free dynamic range (SFDR) at low frequency is above 70 dBc at 1.1 GHz of sample rate. The SFDR is better than 56 dBc from DC to Nyquist frequency.     

Low-voltage temperature sensor for micro-power harvesters in silicon-on-sapphire CMOS

A low-voltage temperature sensor designed for MEMS power harvesting systems is fabricated. The core of the sensor is a bandgap voltage reference circuit operating with a supply voltage in the range 1-1.5 V. The prototype was fabricated on a conventional 0.5 /spl mu/m silicon-on-sapphire (SOS) process. The sensor design consumes 15 /spl mu/A of current at 1 V. The internal reference voltage is 550 mV. The temperature sensor has a digital square wave output the frequency of which is proportional to temperature. A linear model of the dependency of output frequency with temperature has a conversion factor of 1.6 kHz//spl deg/C. The output is also independent of supply voltage in the range 1-1.5 V. Measured results and targeted applications for the proposed circuit are reported.