High-transconductance InAs/AlSb heterojunction field-effecttransistors with δ-doped AlSb upper barriers

The authors report the fabrication and temperature-dependent characterization of InAs/AlSb quantum-well heterojunction field-effect transistors (HFETs). Devices with electron sheet concentrations of 3.8×10¹² cm^-2 and low-field electron mobilities of 21000 cm²/V-s have been realized through the use of Te δ-doping sheets in the upper AlSb barrier. One device with a 2.0-μm gate length showed a peak extrinsic transconductance of 473 mS/mm at room temperature. Gate leakage current, operating current density, and extrinsic transconductance were found to decrease with decreasing temperature     

High-transconductance n-type Si/SiGe modulation-doped field-effecttransistors

The authors report on the fabrication and the resultant device characteristics of the first 0.25-μm gate-length field-effect transistor based on n-type modulation-doped Si/SiGe. Prepared using ultrahigh vacuum/chemical vapor deposition (UHV/CVD), the mobility and electron sheet charge density in the strained Si channel are 1500 (9500) cm²/V-s and 2.5×10¹² (1.5×10¹² ) cm^-2 at 300 K (77 K). At 77 K, the devices have a current and transconductance of 325 mA/mm and 600 mS/mm, respectively. These values far exceed those found in Si MESFETs and are comparable to the best results achieved in GaAs/AlGaAs modulation-doped transistors     

Anisotype-gate self-aligned p-channel heterostructure field-effecttransistors

A new self-aligned p-channel HFET structure was evaluated for application to complementary HFET circuits. The AlGaAs/InGaAs HFET structure uses an anisotype graded n⁺ InGaAs/GaAs semiconductor gate to enhance the barrier height of the FET, resulting in a significant reduction in gate leakage current at low voltages. With AlGaAs composition of x=0.3, and a thin AlAs spacer of 60 Å, leakage current was reduced by a factor of about 1000 at gate voltage of 1 V, when compared to AlGaAs/InGaAs HIGFET of aluminum content x=0.75. The anisotype PFET maintains high device transconductance, typically 50 mS/mm for 1.3×10 μm PFETs, high reverse breakdown voltages 9-10 V, and low capacitance. Microwave S -parameter characterization resulted in F_t of 5 GHz for a 1×50 μm PFET     

Low flicker-noise GaN/AlGaN heterostructure field-effecttransistors for microwave communications

We report a detailed investigation of flicker noise in novel GaN/AlGaN heterostructure field-effect transistors (GaN HFET). Low values of 1/f noise found in these devices (i.e., the Hooge parameter is on the order of 10^-1) open up the possibility for applications in communication systems. We have examined the scaling of the noise spectral density with the device dimensions in order to optimize their performance. It was also found that the slope γ of the 1/f^γ noise density spectrum is in the 1.0-1.3 range for all devices and decreases with the decreasing (i.e., more negative) gate bias. The results are important for low-noise electronic technologies requiring a low phase-noise level     

GaAs enhancement/depletion n-channel MOSFET

The state of the art in the development of GaAs n-channel enhancement/depletion MOSFETs is presented. The static, non-equilibrium and dynamic characteristics are discussed and compared with the behaviour of large-area MOS diodes and a simple theory. It can be concluded, that the device is basically feasible for high speed logic enhancement circuits, pulse recovery purposes and for power applications, although some major oxide/semiconductor interface problems have still to be sorted out.     

MBE growth and photoluminescent properties of InAsSb/AlSbAs quantum wells

Heterostructures with a single InAs_1−x Sb_x/AlSb_1−y As_y quantum well (QW) on (001) GaSb substrates have been grown by MBE and studied using X-ray diffraction, transmission electron microscopy, and photoluminescence (PL) spectroscopy. High-intensity PL was observed at a temperature of 80 K, with a peak half-width of 30–50 meV and a peak wavelength in the range from 2 to 4.5 μm, depending on the QW width, which varied between 4 and 20 nm, respectively. The fundamental absorption edge of such QWs was calculated for a wide range of alloy compositions, x and y. Good correlation between the experimental and calculated dependences of the band gap on the InAsSb/AlSbAs QW thickness was obtained. __________ Translated from Fizika i Tekhnika Poluprovodnikov, Vol. 36, No. 12, 2002, pp. 1470–1474. Original Russian Text Copyright ? 2002 by Solov’ev, Terent’ev, Toropov, Meltser, Semenov, Sitnikova, Ivanov, Meyer, Kop’ev.     

High-breakdown-voltage Ga0.51In0.49P channelMESFET's grown by GSMBE

The first Ga_0.51In_0.49P channel MESFETs grown on a (100) GaAs substrate by GSMBE have been fabricated. A high gate-to-drain breakdown voltage of 42 V with a high maximum current density (320 mA/mm) was achieved. This result demonstrates that high-breakdown voltage could be attained by using Ga_0.51In _0.49P as the channel material. We also measured a high-maximum oscillation frequency (f_max) of 30 GHz for a 1.5 μm gate-length device. This value is quite high compared with other high-breakdown-voltage GaAs MESFET's or MISFET's with the same gate length     

Modeling InAs/GaSb and InAs/InAsSb Superlattice Infrared Detectors

InAs/GaSb and InAs/InAsSb type II superlattices have been proposed as promising alternatives to HgCdTe for the photon-absorbing layer of an infrared detector. When combined with a barrier layer based on an InAs/AlSb superlattice or an AlSbAs alloy, respectively, they can be used to make diffusion-limited “barrier” detectors with very low dark currents. In this work we compare theoretical simulations with experimental bandgap and photoabsorption data for such superlattices, spanning from the mid to the long-wave infra-red (2.3–12 μm). The spectral response of detectors based on these materials is also simulated. The simulations are based on a version of the k · p model developed by one of the authors, which takes interface contributions and bandgap bowing into account. Our results provide a way of assessing the relative merits of InAs/GaSb and InAs/InAsSb superlattices as potential detector materials.     

Interfacial gate resistance in Schottky-barrier-gate field-effecttransistors

We discuss in depth a previously overlooked component in the gate resistance R_g of Schottky-Barrier-Gate FETs, in particular, 0.1-μm gate-length AlInAs/GaInAs MODFETs. The high-frequency noise and power gain of these FETs depend critically on R_g. This has been the motivation for the development of T-gates that keep the gate finger metallization resistance R_ga (proportional to the gate width W_g) low, even for very short gate length L_g . R_ga increases with frequency due to the skin effect, but our three-dimensional (3-D) numerical modeling shows conclusively that this effect is negligible. We show that the always “larger-than-expected” R_g is instead caused by a component R_gi that scales inversely with W_g. We interpret R_gi as a metal-semiconductor interfacial gate resistance. The dominance of R_gi profoundly affects device optimization and model scaling. For GaAs and InP-based SBGFETs, there appears to exist a smallest practically achievable normalized interfacial gate resistance r_gi on the order of 10^-7 Ω cm²     

High-temperature operation of polycrystalline diamond field-effecttransistors

Operation of polycrystalline diamond field-effect transistors (FETs) at temperatures up to 285°C and drain-to-source voltages of up to 100 V has been demonstrated. The devices were fabricated from B-doped polycrystalline diamond grown by a microwave plasma-enhanced chemical vapor deposition (CVD) technique. At 150°C, the devices exhibited saturation of drain current and a peak transconductance of 65 nS/mm. These are the first polycrystalline diamond devices to demonstrate saturation. Device characteristics at 250°C also show saturation and increased transconductance of 300 nS/mm. Characterization was not performed at temperatures exceeding 285°C due to gate leakage current above 10 nA     

Impact of interface impurities on heterostructure field-effecttransistors

The influence of C and Si impurities at the substrate/epitaxy interface on the threshold voltage of GaAs/AlGaAs selectively doped heterostructure transistors has been investigated both experimentally and theoretically using a one-dimensional simulation. The presence of C raises the conduction band relative to the Fermi level and reduces the electron density in the channel. This results in a positive shift of the depletion-mode (DFET) threshold voltage as the interfacial C concentration increases. For low C concentrations the DFET threshold voltage decreases with increasing Si at the interface. The impact of interfacial C and Si is small on the enhancement-mode (EFET) threshold voltage     

Cyclotron resonance of dirac fermions in InAs/GaSb/InAs quantum wells

The band structure of three-layer symmetric InAs/GaSb/InAs quantum wells confined between AlSb barriers is analyzed theoretically. It is shown that, depending on the thicknesses of the InAs and GaSb layers, a normal band structure, a gapless state with a Dirac cone at the center of the Brillouin zone, or inverted band structure (two-dimensional topological insulator) can be realized in this system. Measurements of the cyclotron resonance in structures with gapless band spectra carried out for different electron concentrations confirm the existence of massless Dirac fermions in InAs/GaSb/InAs quantum wells.     

The n-channel SiGe/Si modulation-doped field-effect transistor

At the heterointerface of Si1-xGex/Si the existence of two-dimensional carrier gas has recently been demonstrated. The electrons are confined inside the large-gap material Si. We report the first fabrication of n-channel modulation-doped SiGe/Si hetero field-effect transistors by use of molecular-beam epitaxial growth. Though neither layer sequence nor parasitic resistances were optimized, these first transistors exhibit an extrinsic transconductance of 40 mS/mm for a gate length of 1.6 µm. This value is higher than that of conventional Si MESFET's of comparable carrier concentration. Technological processing steps and device evaluation are described.     

An improved model for four-terminal junction field-effecttransistors

The junction field-effect transistor (JFET) has isolated top- and bottom-gate terminals and therefore is useful for signal mixing applications. Existing models for the four-terminal JFET often have the same form as the three-terminal JFET model, however, in which only a single pinch-off voltage is used to describe the current-voltage characteristics. In this paper, a more general four-terminal JFET model is developed. Two different pinch-off voltages are involved in the improved model to account more comprehensively for the effects of both depletion regions associated with the top- and bottom-gate junctions. Results simulated from a device simulator are also included in support of the model     

Investigation of negative differential resistance phenomena inGaSb/AlSb/InAs/GaSb/AlSb/InAs structures

The negative differential resistance (NDR) phenomena were observed in GaSb/AlSb/InAs/-GaSb/AlSb/InAs resonant interband tunnel structures. Electrons have resonantly achieved interband tunneling through the InAs/GaSb broken-gap quantum well. The InAs well width causes significant variations of the peak current density and NDR behaviors. The peak current density varies exponentially with the AlSb barrier thickness. The multiple NDR behavior was observed with appropriate InAs well and AlSb barrier thicknesses, e.g., 30 Å thick AlSb barrier and 240 Å wide InAs well. Only single negative resistance has, otherwise, been seen. The three-band model was used to interpret the effect of the InAs well and AlSb barrier on the current-voltage characteristics of GaSb/AlSb/InAs/GaSb/AlSb/InAs structures     

An InAlAs/InAs MODFET

An InAs modulation-doped field-effect transistor (MODFET) using an epitaxial heterostructure based entirely on arsenides is reported. The heterostructure was grown by MBE on InP and contains a 30-Å InAs channel. A 2-μm-gate-length device displays well-behaved characteristics, showing sharp pinch-off (V_th=0.8 V) and small output conductance (5 mS/mm) at 300 K. The maximum transconductance is 170 mS mm with a maximum drain current of 312 mA/mm. Strong channel quantization results in a breakdown voltage of -9.6 V, a severalfold improvement over previous InAs MODFETs based on antimonides. Low-temperature magnetic field measurements show strong Shubnikov-de Haas oscillations which, over a certain range of gate voltage, strongly indicate that the electron channel resides in the InAs layer     

1/f noise in n-channel silicon-gate MOS transistors

It is found that equivalent gate noise power for l/f noise in n-channel silicon-gate MOS transistors at near zero drain voltage at room temperature is empirically described by two noise terms, which vary asK_{1}(q/C_{ox}) (V_{G} -V_{T})/f and K_{2}(q/C_{ox})^{2}/f, where V_{G}is gate voltage, VTis threshold Voltage, and Coxis gate-oxide capacitance per unit area. Unification of carrier-density fluctuation (McWhorter's model)and mobility fluctuation (Hooge's model) can account for the experimental data. The comparison between the theory and experiment shows that the carrier fluctuation term K2is proportional to oxide-trap density at Fermi-level. The mobility fluctuation term K1is correlated to K2, being proportional toradic K_{2}. The origin of this correlation is yet to be clarified.     

InAs/AlSb dual-gate HFETs

We report the first implementation of InAs/AlSb dual-gate (DG) HFETs. The devices were fabricated by conventional optical lithography and consist of two electrically distinct 1-μm gates, with a 1-μm intergate separation. The DG-HFETs feature well-behaved, kink-free drain characteristics, and exhibit both high transconductance and low output conductance. We find that DG operation significantly reduces the short-channel effects that have so far plagued InAs/AlSb devices, and increases the maximum allowable drain bias. We estimate that cutoff frequencies as high as 30 GHz-μm may be possible for such devices based on simple equivalent circuit models and previously published experimental data on single-gate InAs/AlSb HFETs     

Velocity saturation effects in n-channel deep-depletion SOS/MOSFET's

We use the n-channel deep-depletion SOS/MOSFET to measure carrier velocity of electrons in thin SOS films. The data are presented as a function of electric field up to the point where the velocity saturates. We show the consistency of these data across devices of different gate lengths and manufacture operating at different gate voltages. These results lead to the concept of a "universal curve" for the carrier velocity versus electric field relationship which can be applied to the modeling of velocity-saturation effects in n-channel SOS/MOSFET's. We develop a technique for such an application. In addition, by compensating for the effect of surface scattering on mobility, we have been able to show that the velocity versus field relationship at the surface of thin SOS films agrees very closely to that obtained from bulk silicon.     

High-breakdown-voltage AlInAs/GaInAs junction-modulated HEMT's(JHEMT's) with regrown ohmic contacts by MOCVD

A technology for increasing both the two-terminal gate-drain breakdown and subsequently the three-terminal-off-state breakdown of AlInAs/GaInAs high-electron-mobility transistors (HEMTs) to record values without substantial impact on other parameters is presented. The breakdown in these structures is dependent on the multiplication of electrons injected from the source (channel current) and the gate (gate leakage) into the channel. In addition, holes are generated by high fields at the drain and are injected back into the gate and source electrodes. These phenomena can be suppressed by increasing the gate barrier height and alleviating the fields at the drain. Both have been achieved by incorporating a p⁺-2DEG junction as the gate that modulates the 2DEG gas and by utilizing selective regrowth of the source and drain regions by MOCVD. The 1-μm-gate-length devices fabricated have two-terminal gate-drain and three-terminal-off-state breakdown voltages of 31 V and 28 V, respectively